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CMOS STATIC RAM 64K (16K x 4-BIT)
Integrated Device Technology, Inc.
IDT7188S IDT7188L
FEATURES:
* High-speed (equal access and cycle times) -- Military: 25/35/45/55/70/85ns (max.) * Low power consumption * Battery backup operation -- 2V data retention (L version only) * Available in high-density industry standard 22-pin, 300 mil ceramic DIP * Produced with advanced CMOS technology * Inputs/outputs TTL-compatible * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7188 is a 65,536-bit high-speed static RAM organized as 16K x 4. It is fabricated using IDT's highperformance, high-reliability technology -- CMOS. This stateof-the-art technology, combined with innovative circuit design
techniques, provides a cost effective approach for memory intensive applications. Access times as fast as 25ns are available. The IDT7188 offers a reduced power standby mode, ISB1, which is activated when CS goes HIGH. This capability significantly decreases power while enhancing system reliability. The low-power version (L) version also offers a battery backup data retention capability where the circuit typically consumes only 30W operating from a 2V battery. All inputs and outputs are TTL-compatible and operate from a single 5V supply. The IDT7188 is packaged in 22-pin, 300 mil ceramic DIP providing excellent board-level packing densities. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0 VCC GND 65,536-BIT MEMORY ARRAY
DECODER
A13
I/O0 I/O1 I/O2 I/O3
COLUMN I/O INPUT DATA CONTROL
CS WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2989 drw 01
MILITARY TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
AUGUST 1996
6.3
DSC-2989/7
1
IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Com'l. Mil. -0.5 to +7.0 Unit V Terminal Voltage -0.5 to +7.0 with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current 0 to +70 -55 to +125 -55 to +125 1.0 50
A0 A1 A2 A3 A4 A5 A6 A7 A8 CS GND
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18
D22-1
17 16 15 14 13 12
VCC A13 A12 A11 A10 A9 I/O 3 I/O 2 I/O 1 I/O 0 WE
2989 drw 02
TA TBIAS TSTG PT IOUT
-55 to +125 -65 to +135 -65 to +150 1.0 50
C C C W mA
DIP TOP VIEW
NOTE: 2989 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, f = 1.0MHz, VCC = 0v))
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 6 Unit pF pF
PIN DESCRIPTIONS
Name A0-A13
CS WE
Description Address Inputs Chip Select Write Enable Data Input/Output Power Ground
2989 tbl 01
NOTE: 2989 tbl 04 1. This parameter is determined by device characterization, but is not production tested.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
I/O0-3 VCC GND
Typ. 5.0 0 -- --
Max. Unit 5.5 0 6.0 0.8 V V V V
NOTE: 2989 tbl 05 1. VIL (min.) = -3.0V for pulse width less than 20ns,once per cycle.
TRUTH TABLE(1)
Mode Standby Read Write
CS WE
I/O High Z DOUT DIN
Power Standby Active Active
2989 tbl 02
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Commercial Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5V 10% 5V 10%
2989 tbl 06
H L L
X H L
NOTE: 1. H = VIH, L = VIL, X = don't care.
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IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%
IDT7188S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 10mA, VCC = Min. IOL = 8mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. -- 2.4 MIL. COM'L. MIL. COM'L. Min. -- -- -- -- Max. 10 5 10 5 0.5 0.4 -- IDT7188L Min. -- -- -- -- -- -- 2.4 Max. 5 2 5 2 0.5 0.4 -- V
2989 tbl 07
Unit A A V
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7188S25 7188L25 Symbol ICC1 Parameter Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS VHC, VCC=Max., VIN VHC or VIN VLC, f = 0(2) Power S L S L S L S
Com'l. Mil.
7188S35 7188L35
Com'l. Mil.
7188S45 7188L45
Com'l. Mil.
7188S55/70 7188L55/70
Com'l. Mil.
7188S85 7188L85
Com'l. Mil.
Unit mA
-- -- -- -- -- -- --
105 80 155 120 60 40 20
-- -- -- -- -- -- --
105 80 140 115 50 40 20
-- -- -- -- -- -- --
105 80 140 110 50 35 20
-- -- -- -- -- -- --
105 80 140 110 50 35 20
-- -- -- -- -- -- --
105 80 140 105 50 35 20
ICC2
mA
ISB
mA
ISB1
mA
L
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
2989 tbl 08
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
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3
IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VHC = VCC - 0.2V
Typ. (1) VCC @ Symbol VDR ICCDR tCDR(3) tR(3) |ILI|
(3)
Max. VCC @ 2.0V -- 600 150 -- -- 2 3.0V -- 900 225 -- -- 2 Unit V A ns ns A
2989 tbl 09
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Input Leakage Current
Test Condition -- MIL. COM'L.
CS
Min. 2.0 -- -- 0 tRC(2) --
2.0v -- 10 10 -- -- --
3.0V -- 15 15 -- -- --
VHC VIN VHC or VLC
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but is not production tested.
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE 4.5V t CDR CS VIH VDR2V VDR VIH
2989 drw 03
VCC
4.5V tR
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2989 tbl 10
5V 480 DATAOUT 255 30pF*
5V 480 DATAOUT 255 5pF*
2989 drw 04
2989 drw 05
Figure 1. AC Test Load *Includes scope and jig capacitances
Figure 2. AC Test Load (for tHZ, tLZ, tWZ, tOHZ and tOW)
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4
IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
7188S25 7188L25 7188S35/45 7188L35/45 7188S55/70 7188L55/70 7188S85 7188L85
Symbol Read Cycle tRC tAA tACS tOH tLZ
(1) (1) (1) (1)
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Selection to Output in Low-Z Chip Deselect to Output in High-Z Chip Select to Power Up Time Chip Deselect to Power Down Time
25 -- -- 5 5 -- 0 --
-- 25 25 -- -- 10 -- 25
35/45 -- -- 5 5 -- 0 --
-- 35/45 35/45 -- -- 14 -- 35/45
55/70 -- -- 5 5 -- 0 --
-- 55/70 55/70 -- -- 20/25 -- 55/70
85 -- -- 5 5 -- 0 --
-- 85 85 -- -- 30 -- 85
ns ns ns ns ns ns ns ns
2989 tbl 11
tHZ
tPU tPD
NOTES: 1. This parameter is guaranteed by device characterization but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1, 2)
tRC (5) ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID
2989 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 3)
tRC (5)
CS
tACS tLZ (4) DATAOUT tPU ICC VCC SUPPLY CURRENT ISB DATA VALID
tHZ (4)
HIGH IMPEDANCE
tPD
2989 drw 07
NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured 200mV from steady state voltage. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.3
5
IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
7188S25 7188L25 7188S35/45 7188L35/45 7188S55/70 7188L55/70 7188S85 7188L85
Symbol Write Cycle tWC tCW tAW tAS tWP tWR tDW tDH tWZ
(1) (1)
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write
20 20 20 0 20 0 13 0 -- 5
-- 30/40 -- 25/35 -- 25/35 -- 0
-- -- -- -- -- -- -- -- 10/15 --
50/60 50/60 50/60 0 50/60 0 25/30 0 -- 5
-- -- -- -- -- -- -- -- 25/30 --
75 75 75 0 75 0 35 0 -- 5
-- -- -- -- -- -- -- -- 40 --
ns ns ns ns ns ns ns ns ns ns
2989 tbl 12
-- 25/35 -- 0
-- 15/20 -- 7 -- 0 -- 5
tOW
NOTES: 1. This parameter is guaranteed by device characterization.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2 ,3) WE
tWC ADDRESS tAW
CS1, CS2
tAS
WE
tWP
(7)
tWR
tWZ (6) DATAOUT
(4)
tOW (6)
(4)
tDW DATAIN
tDH
DATA VALID
2989 drw 08
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state.
6.3
6
IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,3,5) CS
tWC ADDRESS tAW
CS
tAS
WE
tCW
t WR
tDW DATAIN DATA VALID
tDH
2989 drw 09
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state.
ORDERING INFORMATION
IDT7188 Device Type X Power XX Speed X Package X Process/ Temperature Range
B
Military (-55C to +125C) Compliant to MIL-STD-883, Class B
D
300 mil Ceramic DIP (D22-1)
25 35 45 55 70 85
Speed in nanoseconds
S L
Standard Power Low Power
2989 drw 10
6.3
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