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| RF1K49224 Data Sheet August 1999 File Number 4330.1 3.5A/2.5A, 30V, 0.060/0.150 Ohms, Complementary LittleFETTM Power MOSFET The RF1K49224 complementary power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This device can be operated directly from intergrated circuits. Formerly developmental type TA49224. Features * 3.5A, 30V (N-Channel) 2.5A, 30V (P-Channel) * rDS(ON) = 0.060 (N-Channel) rDS(ON) = 0.150 (P-Channel) * Temperature Compensating PSPICE(R) Model * Thermal Impedance PSPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER RF1K49224 PACKAGE MS-012AA BRAND RF1K49224 Symbol D1(8) D1(7) S1(1) G1(2) NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e. RF1K4922496. D2(6) D2(5) S2(3) G2(4) Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 4 9-16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. LittleFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RF1K49224 TA = 25oC Unless Otherwise Specified N-CHANNEL 30 Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS= 20k ) . . . . . . . . . . . . . . .VDGR 30 Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VGS 20 Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . ID 3.5 Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Refer to Peak Current Curve Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 2 Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.016 Operating and Storage Temperature . . . . . . . . . . . . TJ, TSTG -55 to 150 Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . TL 300 Package Body for 10s, See Techbrief 334 . . . . . . . . . .Tpkg 260 Absolute Maximum Ratings P-CHANNEL -30 -30 20 2.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 UNITS V V V A W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. N-Channel Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = 30V, VGS = 0V VGS = 20V ID = 3.5A VGS = 10V VGS = 4.5V Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJA Pulse width = 1s Device mounted on FR-4 material VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 24V, ID 3.5A, RL = 6.86 Ig(REF) = 1.0mA VDD = 15V, ID 3.5A, RL = 4.29, VGS = 10V, RGS = 25 10 30 60 45 35 13 2.3 575 275 100 TA = 25o C TA = 150o C MIN 30 1 TYP MAX 3 1 50 100 0.060 0.132 50 130 45 17 2.9 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) VDS = 25V, VGS = 0V, f = 1MHz N-Channel Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 3.5A ISD = 3.5A, dISD/dt = 100A/s MIN TYP MAX 1.25 45 UNITS V ns 9-17 RF1K49224 P-Channel Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = -30V, VGS = 0V VGS = 20V ID = 2.5A VGS = -10V VGS = -4.5v Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at -10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-10) Qg(TH) CISS COSS CRSS RJA Pulse width = 1s Device mounted on FR-4 material VGS = 0V to -20V VGS = 0V to -10V VGS = 0V to -2V VDD = -24V, ID 2.5A, RL = 9.6 Ig(REF) = -1.0mA VDD = -15V, ID 2.5A, RL = 6, VGS = -10V, RGS = 25 9 19 60 34 28 15 1.5 580 260 38 TA = 25o C TA = 150o C MIN -30 -1 TYP MAX -3 -1 -50 100 0.150 0.360 40 140 35 19 1.9 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) VDS = -25V, VGS = 0V, f = 1MHz P-Channel Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = -2.5A ISD = -2.5A, dISD/dt = -100A/s MIN TYP MAX -1.25 49 UNITS V ns Typical Performance Curves (N-Channel) 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0.8 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 0 25 75 100 125 50 TA, AMBIENT TEMPERATURE (oC) 150 0.6 0.4 0.2 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 9-18 RF1K49224 Typical Performance Curves (N-Channel) 10 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 (Continued) THERMAL IMPEDANCE ZJA, NORMALIZED 1 PDM 0.1 t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 10-2 t, RECTANGULAR PULSE DURATION (s) 101 102 103 SINGLE PULSE 0.001 10-5 10-4 10-3 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 TJ = MAX RATED TA = 25oC IDM, PEAK CURRENT (A) 200 100 VGS = 10V TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I ID, DRAIN CURRENT (A) 10 = I25 150 - TA 125 1 5ms 10ms 100ms 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) VDSS(MAX) = 30V 1s DC 100 0.01 0.1 1 10 1 10-5 10-4 10-3 10-2 10-1 100 101 VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 20 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 25 VGS = 20V VGS = 10V VGS = 5V 20 15 VGS = 4.5V STARTING TJ = 25oC 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 4V 5 STARTING TJ = 150oC 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 0 0 1 VGS = 3V 4 5 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 7. SATURATION CHARACTERISTICS FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 9-19 RF1K49224 Typical Performance Curves (N-Channel) 25 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 25oC VDD = 15V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 200 ID = 7.0A ID = 3.5A ID = 1.75A (Continued) 250 20 -55oC 15 150oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 150 10 100 ID = 0.5A 50 5 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5 0 3 4 5 6 7 8 9 10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 3.5A THRESHOLD VOLTAGE NORMALIZED GATE 2.0 VGS = VDS, ID = 250A 1.5 1.5 1.0 1.0 0.5 0.5 0 -80 -40 0 40 80 120 160 0 -80 -40 TJ, JUNCTION TEMPERATURE (oC) 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.5 1000 C, CAPACITANCE (pF) 750 CISS 500 COSS 250 CRSS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 1.0 0.5 0 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 0 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 25 FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 9-20 RF1K49224 Typical Performance Curves (N-Channel) VDS , DRAIN TO SOURCE VOLTAGE (V) 30 VDD = BVDSS 22.5 RL = 8.57 Ig(REF) = 0.75mA VGS = 10V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I g ( REF ) 20 ----------------------I g ( ACT ) t, TIME (ms) I g ( REF ) 80 ----------------------I g ( ACT ) VDD = BVDSS 7.5 (Continued) 15 5.0 7.5 2.5 0 0 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms (N-Channel) VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VGS VDS + VGS , GATE TO SOURCE VOLTAGE (V) 10.0 tOFF td(OFF) tf 90% VDS 90% DUT RGS VGS VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS 9-21 RF1K49224 Test Circuits and Waveforms (N-Channel) VDS RL (Continued) VDD VDS Qg(TOT) VGS = 20V VGS + Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V DUT Ig(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM Typical Performance Curves (P-Channel) 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 ID, DRAIN CURRENT (A) -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 25 75 100 125 50 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 21. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 22. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 10 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 THERMAL IMPEDANCE ZJA, NORMALIZED 1 PDM 0.1 t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 10-2 t, RECTANGULAR PULSE DURATION (s) 101 102 103 SINGLE PULSE 0.001 10-5 10-4 10-3 FIGURE 23. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 9-22 RF1K49224 Typical Performance Curves (P-Channel) -50 (Continued) TJ = MAX RATED TA = 25oC IDM, PEAK CURRENT (A) -100 ID, DRAIN CURRENT (A) -10 VGS = -20V TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = -10V I = I25 150 - TA 125 -1 5ms 10ms -10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100ms -0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1s VDSS(MAX) = -30V -10 DC -100 -0.01 -0.1 -1 -1 10-5 10-4 10-3 10-2 10-1 100 101 VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s) FIGURE 24. FORWARD BIAS SAFE OPERATING AREA -15 IAS, AVALANCHE CURRENT (A) -10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC -20 FIGURE 25. PEAK CURRENT CAPABILITY VGS = -20V VGS = -10V VGS = -8V ID, DRAIN CURRENT (A) -16 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = -7V VGS = -6V -12 VGS = -5V STARTING TJ = 150oC -8 VGS = -4.5V -4 -1 0.1 0 1 10 tAV, TIME IN AVALANCHE (ms) 100 0 -1.5 -3.0 -4.5 -6.0 -7.5 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 26. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 27. SATURATION CHARACTERISTICS -20 ID(ON), ON-STATE DRAIN CURRENT (A) rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) -16 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -15V -55oC 25oC 500 150oC 400 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -15V ID = -5.0A ID = -2.5A -12 300 ID = -1.25A 200 ID = -0.625A 100 -8 -4 0 0 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) -10 0 -2 -4 -6 -8 -10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 28. TRANSFER CHARACTERISTICS FIGURE 29. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 9-23 RF1K49224 Typical Performance Curves (P-Channel) 2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V, ID = -2.5A 1.5 NORMALIZED GATE THRESHOLD VOLTAGE 1.0 (Continued) 1.2 VGS = VDS, ID = -250A 1.0 0.8 0.5 0.6 0 -80 -40 0 40 80 120 160 0.4 -80 -40 TJ, JUNCTION TEMPERATURE (oC) 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 FIGURE 30. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 31. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = -250A C, CAPACITANCE (pF) 750 CISS 600 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 1.1 450 COSS 300 1.0 0.9 150 CRSS 0.8 -80 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 0 -5 -10 -15 -20 -25 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 32. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -30.0 VDD = BVDSS -22.5 FIGURE 33. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VDS , DRAIN TO SOURCE VOLTAGE (V) VDD = BVDSS -7.5 -15.0 -7.5 0 RL = 12 Ig(REF) = -0.26mA VGS = -10V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I g ( REF ) 20 ----------------------I g ( ACT ) t, TIME (s) -5.0 -2.5 0 80 -------------------I g ( ACT ) I g ( REF ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 34. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT 9-24 VGS , GATE TO SOURCE VOLTAGE (V) -10.0 RF1K49224 Test Circuits and Waveforms (P-Channel) VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 35. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 36. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VGS VDS 0 10% tOFF td(OFF) tf 10% VDD + VDS VGS 0 90% 90% VGS RGS DUT 10% 50% PULSE WIDTH 90% 50% FIGURE 37. SWITCHING TIME TEST CIRCUIT FIGURE 38. RESISTIVE SWITCHING WAVEFORMS VDS RL 0 VGS= -2V VGS VDD + Qg(TH) VDS -VGS Qg(-10) VDD Qg(TOT) 0 Ig(REF) VGS= -10V DUT Ig(REF) VGS= -20V FIGURE 39. GATE CHARGE TEST CIRCUIT FIGURE 40. GATE CHARGE WAVEFORMS 9-25 RF1K49224 Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. 9-26 RF1K49224 PSPICE Electrical Model (N-Channel) SUBCKT RF1K49224 2 1 3 ; CA 12 8 1.75e-9 CB 15 14 1.80e-9 CIN 6 8 1.20e-9 DPLCAP 5 LDRAIN N-Channel Model rev 12/15/94 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 33.29 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 GATE 1 EVTO 9 20 + 18 8 LGATE RGATE 10 DRAIN 2 DBREAK RDRAIN ESG + 6 8 VTO + 6 11 16 EBREAK 17 18 + DBODY 21 MOS1 MOS2 RIN CIN 8 RSOURCE 7 LSOURCE 3 SOURCE MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 1.83 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 13.5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD S1A 12 S1B CA + EGS 6 8 EDS 13 8 14 13 13 CB + 14 5 8 S2A 15 RBREAK 17 18 RVTO IT 19 VBAT + S2B VBAT 8 19 DC 1 VTO 21 6 0.1 .MODEL DBDMOD D (IS = 2.50e-13 RS = 1.35e-2 TRS1 = 4.31e-5 TRS2 = 2.15e-5 CJO = 9.33e-10 TT = 2.08e-8) .MODEL DBKMOD D (RS = 1.14 TRS1 = 2.23e-3 TRS2 = -8.91e-6) .MODEL DPLCAPMOD D (CJO = 7.99e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.15 KP = 6.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.74e-4 TC2 = 1.13e-6) .MODEL RDSMOD RES (TC1 = 4.5e-3 TC2 = -7.45e-7) .MODEL RVTOMOD RES (TC1 = -4.16e-3 TC2 = 2.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.15 VOFF= -5.15) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.15 VOFF= -7.15) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.6 VOFF= 2.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.4 VOFF= -2.6) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. 9-27 RF1K49224 PSPICE Electrical Model (P-Channel) SUBCKT RF1K49224 2 1 3 ; CA 12 8 7.29e-10 CB 15 14 5.01e-10 CIN 6 8 5.55e-10 P-Channel Model rev 4/7/97 ESG LDRAIN + 5 RLDRAIN + 17 18 DRAIN 2 RSLC1 51 ESLC 50 DBODY EBREAK DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -35.46 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 LGATE 10 8 6 RSLC2 5 51 DPLCAP EVTHRES + 19 8 6 EVTEMP RGATE 9 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.27e-9 LSOURCE 3 7 4.20e-10 GATE 1 RLGATE - 20 18 + 22 CIN MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 19.3e-3 RGATE 9 20 7.44 RLDRAIN 2 5 10 RLGATE 1 9 12.7 RLSOURCE 3 7 4.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 65.37e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD 12 S1A 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*48),2.5))} .MODEL DBODYMOD D (IS = 3.30e-13 RS = 4.56e-2 TRS1 =6.98e-4 TRS2 =8.08e-7 CJO = 8.21e-10 TT = 3.51e-8 M=0.4) .MODEL DBREAKMOD D (RS = 8.18e-1 TRS1 =5.28e-3 TRS2 = -7.18e-5 .MODEL DPLCAPMOD D (CJO = 2.52e-10 IS = 1e-30 N = 10 M=0.6) .MODEL MMEDMOD PMOS (VTO= -1.95 KP=0.75 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=7.44) .MODEL MSTROMOD PMOS (VTO= -2.44 KP= 7.25 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MWEAKMOD PMOS (VTO= -1.68 KP=0.045 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=74.4 RS=0.1) .MODEL RBREAKMOD RES (TC1 = 9.45e-4 TC2 = -1.01e-7) .MODEL RDRAINMOD RES (TC1 = 3.69e-3 TC2 = 5.90e-6) .MODEL RSLCMOD RES (TC1=3.46e-3 TC2= 1.26e-6) .MODEL RSOURCEMOD RES (TC1=3.69e-3 TC2=5.90e-6) .MODEL RVTHRESMOD RES (TC=-5.19e-4 TC2= 5.02e-6) .MODEL RVTEMPMOD RES (TC1 = -3.54e-3 TC2 = -6.53e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .ENDS NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 6.94 VOFF= 3.94) VON = 3.94 VOFF= 6.94) VON = 0.40 VOFF= -2.60) VON = -2.60 VOFF= 0.40) 9-28 + - - RDRAIN 21 16 MWEAK MMED MSTRO 8 RSOURCE DBREAK 11 LSOURCE 7 RLSOURCE RBREAK 18 RVTEMP 19 SOURCE 3 VBAT + 8 22 RVTHRES RF1K49224 PSpice Thermal Model REV 28 Feb 97 RF1K49224 CTHERM1 7 6 1.00e-7 CTHERM2 6 5 9.00e-4 CTHERM3 5 4 3.00e-3 CTHERM4 4 3 4.00e-2 CTHERM5 3 2 5.20e-3 CTHERM6 2 1 1.90e-2 RTHERM1 7 6 7.10e-2 RTHERM2 6 5 1.90e-1 RTHERM3 5 4 5.95e-1 RTHERM4 4 3 4.27 RTHERM5 3 2 1.2e1 RTHERM6 2 1 1.04e2 7 JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 1 CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9-29 |
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