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| 5-BIT 2:1 MUX-LATCH SY10E154 SY100E154 FEATURES s s s s s s s 750ps max. LEN to output Extended 100E VEE range of -4.2V to -5.5V 700ps max. D to output Differential outputs Asynchronous Master Reset Dual latch-enables Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E154 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. When both LEN1 and LEN2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the SEL(Select) signal which selects one of the two bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. BLOCK DIAGRAM PIN CONFIGURATION VCCO Q4 Q4 D4b D4a D3b D3a D0a MUX D0b D1a MUX D1b D2a MUX D2b D3a MUX D3b D4a MUX D4b SEL LEN1 LEN2 MR SEL SEL SEL SEL SEL D Q Q0 Q0 SEL 26 27 28 1 2 3 4 EQ NR D Q 25 24 23 22 21 20 19 18 17 Q3 Q3 VCC Q2 Q2 Q1 Q1 Q1 Q1 LEN1 LEN2 VEE MR D0a EQ NR D Q PLCC TOP VIEW J28-1 16 15 14 13 12 Q2 Q2 D0b EQ NR D Q 5 6 7 8 9 10 11 D1a D1b VCCO Q0 D2a D2b Q3 Q3 EQ NR D Q PIN NAMES Q4 Q4 Pin D0a-D4a D0b-D4b SEL LEN1, LEN2 MR Q0-Q4 Q0-Q4 VCCO Function Input Data a Input Data b Data Select Input Latch Enables Master Reset True Outputs Inverted Outputs VCC to Output Rev.: C Amendment: /1 EQ NR 1 Q0 Issue Date: February, 1998 Micrel SY10E154 SY100E154 TRUTH TABLES SEL H L Data a b LEN1 L H X LEN2 L X H Latch Transparent Latched Latched DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 76 76 91 91 -- -- 76 76 91 91 -- -- 76 87 91 105 TA = +25C TA = +85C Max. 150 Unit A mA Condition -- -- Min. Typ. Max. Min. Typ. -- -- 150 -- -- Max. Min. Typ. 150 -- -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D SEL LEN MR Set-up Time D SEL Hold Time D SEL Reset Recovery Time Minimum Pulse Width, MR Within-Device Skew Rise/Fall Time 20% to 80% TA = +25C TA = +85C Max. 700 925 750 800 ps 300 500 300 200 800 400 -- 300 100 250 -100 -250 600 -- 50 475 -- -- -- -- -- -- -- 800 300 500 300 200 800 400 -- 300 100 250 -100 -250 600 -- 50 475 -- -- -- -- -- -- -- 800 300 500 300 200 800 400 -- 300 100 250 -100 -250 600 -- 50 475 -- -- ps -- -- -- -- -- 800 ps ps ps ps -- -- 1 -- -- -- Unit ps 325 475 350 450 500 650 500 600 700 925 750 800 325 475 350 450 500 650 500 600 700 925 750 800 325 475 350 450 500 650 500 600 Condition -- Min. Typ. Max. Min. Typ. Max. Min. Typ. tS tH tRR tPW tskew tr tf NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E154JC SY10E154JCTR SY100E154JC SY100E154JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 2 Micrel SY10E154 SY100E154 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E154 SY100E154 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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