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TEA6422
BUS-CONTROLLED AUDIO MATRIX
. . . . . . . .
6 STEREO INPUTS 3 STEREO OUPUTS GAIN CONTROL 0dB/MUTE FOR EACH OUTPUT CASCADABLE (2 DIFFERENT ADDRESSES) SERIAL BUS CONTROLLED VERY LOW NOISE VERY LOW DISTORSION FULLY ESD PROTECTED
SHRINK 24 (Plastic Package) ORDER CODE : TEA6422
DESCRIPTION The TEA6422 switches 6 stereo audio inputs on 3 stereo outputs. All the switching possibilities are changed through the I2C BUS. PIN CONNECTIONS
SDIP24
GND CAPACITANCE VS L1 L2 L3 L4 L5 L6 LOU T1 ROUT1 LOU T2 1 2 3 4 5 6 7 8 9 10 11 12
SO28 (Plastic Micropackage) ORDER CODE : TEA6422D
SO28
24 23 22 21 20 19 18 17 16 15 14 13
SDA SCL ADDR R1 R2 R3 R4 R5 R6 ROUT3 LOUT3 ROUT2
GND CAPACITANCE VS L1 L2 L3 NC NC L4 L5 L6 LOUT1 ROUT1 LOUT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
SDA SCL ADDR R1 R2 R3 NC NC R4 R5 R6 ROUT3 LOUT3 ROUT2
6422-01.EPS / 6422-02.EPS
May 1996
1/9
TEA6422
BLOCK DIAGRAM
RIGHT INPUTS
T E A 6 4 2 2
GAIN = 0/2/4/6dB
RIGHT OUTPUTS
VS
S DA S UPP LY
C
BUS DECODER
SCL ADDR
GND
LEFT OUTPUTS
GAIN = 0/2/4/6dB
6422-03.EPS
LEFT INPUTS
ABSOLUTE MAXIMUM RATINGS
Symbol VCC Toper Tstg Supply Voltage Operating Temperature Storage Temperature Parameter Value 12 0, + 70 - 20, + 150 Unit
o o
C C
THERMAL DATA
Rth(j-a) Junction - ambient Thermal Resistance SDIP24 SO28 75 75
o C/W o
6422-02.TBL
Symbol
Parameter
Value
Unit C/W
2/9
6422-01.TBL
V
TEA6422
ELECTRICAL CHARACTERISTICS TA = 25oC, VS = 9V, RL = 10k, RG = 600, f = 1kHz (unless otherwise specified)
Symbol SUPPLY VS IS SVR MATRIX VIN RI CS Input DC Level Input Resistance Channel Separation VIN = 2VRMS, f = 1kHz 30 80 4.5 50 90 100 V k dB Supply Voltage Supply Current Ripple Rejection VIN = 500mVRMS, f = 1kHz 70 8 9 3 80 10.2 8 V mA dB Parameter Test Conditions Min. Typ. Max. Unit
OUTPUT BUFFER VOUT R OUT eNI S/N G d VCL RL Output DC Level Output Resistance Input Noise Signal to Noise Ratio Gain Distortion Clipping Level Output Load Resistance VIN = VOUT = 1VRMS d = 0.3% 2 2 BW = 20 - 20kHz, flat VIN = VOUT = 1VRMS -1 4.2 4.5 50 3 110 0 0.01 2.5 +1 0.05 4.8 100 V V dB dB VRMS k
6422-03.TBL
%
3/9
TEA6422
I2C BUS CHARACTERISTICS
Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low-to High Transition 4.7 4.0 250 0 4.0 4.7 4.0 4.7 340 s s ns ns s s s
6422-04.TBL 6422-04.EPS
Parameter
Test Conditions
Min.
Max.
Unit
Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance 1.5V to 3V 1.5V to 3V VI = 0 to VCC
- 0.3 3.0 - 10 0
+ 1.5 VCC + 0.5 + 10 100 1000 300 10
V V A kHz ns ns pF
Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance 1.5V to 3V 1.5V to 3V IOL = 3mA 3V to 1.5V VI = 0 to VCC
- 0.3 3.0 - 10
+ 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400
V V A pF ns ns V ns pF
s
Figure 1 : I2C Bus Timing
SDA t BUF t LOW tf
SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT
SDA t SU,STA t SU,STO
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TEA6422
POWER ON RESET After power-on reset all outputs are in mute mode
Symbol Reset Start of Reset End of Reset Parameter Conditions Incr. V CC Decr. V CC Incr. V CC Min. Typ. Max. 2.5 4.2 4.5 Unit V V V
6422-05.TBL
SOFTWARE SPECIFICATION 1. Chip address
Address 1001 1000 1001 1010 HEX 98 9A ADDR 0 1
2. Data bytes
Output select X 0 0 1 0 1 0 X X I2 I1 I0 Output 1 Output 2 Output 3
Input select X Q1 Q0 X X 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Mute
X = don't care - MSB is transmitted first Example : 0 10 XX 100 connects outputs 3 with input 5.
5/9
6422-06.TBL
TEA6422
Figure 2 : Distorsion Level versus Input Voltage
dis (%) 0.1 0.08 0.06 0.04 0.02 0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 VIN ( VRMS )
6422-05.EPS
Figure 3 : Clipping Level versus Supply Voltage
3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 7.5 8 8.5 9 9.5 10
6422-06.EPS
Vclipp ( VRMS ) dis = 0.3% f = 1kHz T amb = 25C
VS = 9V f = 1kHz T amb = 25C
VS (V) 10.5 11
Figure 4 : Supply Voltage Rejection versus frequency (VIN = 500mVRMS)
SVR (dB)
98 95 92 89
86
V S = 9V
83 80
6422-07.EPS
77 74 0.05
freq (kHz)
0.5
5
20
6/9
TEA6422
PIN CONFIGURATIONS (SDIP24 Package) Figure 5 : Audio IN
VCC
Figure 6 : Audio OUT
VCC
Pins 4-5-6-7-8-9 16-17-18-19-20-21 L (R) x in x = 1, 2, 3, 4, 5, 6
50k
Pins 10- 11-12 13-14-15
V C C /2
Figure 7 : ADDR
6422-08.EPS
Figure 8 : Bus Inputs (SDA, SCL)
VCC
V CC 50k
ESD PROT.
Pins 23 - 24
VREF
22
to CMOS
X4
to CMOS
ACKN
6422-10.EPS 6422-11.EPS
For SDA only
TYPICAL APPLICATION (SDIP24 Package)
1 24 23 22
SDA SCL
22F +9V
2 3
Bus Inputs SW
100nF C1 4 C2 Left Inputs C3 C4 C5 C11 C12 CH1 L Output R C13 C14 CH2 Output L
5 6 7 8 9 10 11 12
T E A 6 4 2 2
21 20 19 18 17 16 15 14 13
C6 C7 C8 C9 C10 C18 C17 C16 C15 R CH3 L Output R CH2 Output Right Inputs
C1 - C18 = 4.7F
7/9
6422-12.EPS
6422-09.EPS
Matrix Point
L (R) x out x = 1, 2, 3
TEA6422
PACKAGE MECHANICAL DATA 24 PINS - PLASTIC SHRINK
E E1
A1
A2
Stand-off B B1 e e1 e2
L c D E 24 13 F
.015 0,38
A
1
12 e3
SDIP24
e2
Dimensions A A1 A2 B B1 C D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86
Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240
Inches Typ.
Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270
3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62
0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30
2.54
3.30
0.10
0.130
8/9
SDIP24.TBL
10.92 1.52 3.81
0.430 0.060 0.150
PMSDIP24.EPS
Gage Plane
TEA6422
PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions A a1 b b1 C c1 D E e e3 F L S
Min. 0.1 0.35 0.23
Millimeters Typ.
Max. 2.65 0.3 0.49 0.32 45 (Typ.)
o
Min. 0.004 0.014 0.009
Inches Typ.
Max. 0.104 0.012 0.019 0.013
0.5 17.7 10 1.27 16.51 7.4 0.4 7.6 1.27 8 (Max.)
o
0.020 18.1 10.65 0.697 0.394 0.050 0.65
SO28.TBL
0.713 0.419
0.291 0.016
0.299 0.050
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
9/9
PM-SO28.EPS

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