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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78F4046
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78F4046 is a product of the PD784046 Subseries in the 78K/IV Series. The PD78F4046 has flash memory in place of the internal ROM of the PD784046. The incorporation of flash memory allows a program to be written or erased while mounted on the target board. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD784046 Subseries User's Manual Hardware: U11515E 78K/IV Series User's Manual Instruction: U10905E
FEATURES
* * * * * 78K/IV Series Pin compatible with PD784044, 784046 (except VPP pin) Flash memory: 64 KB Internal RAM: 2048 bytes Operable with the same supply voltage as that of the mask ROM version: VDD = 4.5 to 5.5 V
APPLICATIONS
* Water heaters, vending machines, etc. * FA fields such as robots, automated machine tools, etc.
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14 mm)
PD78F4046GC-3B9
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U11447EJ2V0DS00 (2nd edition) Date Published August 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1996, 2000
PD78F4046
78K/IV SERIES LINEUP
: Products in mass production : Products under development
Standard models
I2C bus supported
Multimaster I2C bus supported
PD784038Y PD784038
Expanded internal memory capacity, pin compatible with PD784026 Multimaster I2C bus supported PD784216Y/ PD784216AY PD784216/ PD784216A 100 pins, enhanced I/O, expanded internal memory capacity
PD784225Y PD784225
80 pins, ROM correction added
PD784026
Enhanced A/D, 16-bit timer, power management
Multimaster I2C bus supported PD784218Y/ PD784218AY PD784218/ PD784218A Expanded internal memory capacity, ROM correction added
PD784054
PD784046
On-chip 10-bit A/D ASSP models
PD784967 PD784956A
For DC inverter control
PD784938A PD784908 with enhanced functions, expanded internal memory capacity, ROM correction added
Multimaster I2C bus supplied
PD784908
On-chip IEBusTM controller
Enhanced functions of the PD784938A, enhanced I/O and internal memory capacity
PD784915
Software servo control, on-chip analog circuit for VCR, enhanced timer
PD784928Y PD784928 PD784915 with enhanced functions
PD784976A
On-chip VFD controller/driver
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Data Sheet U11447EJ2V0DS00
PD78F4046
OVERVIEW OF FUNCTIONS
Item Number of basic instructions (mnemonics) General-purpose registers Minimum instruction execution time Internal memory Memory space I/O ports Total Input I/O Pins with Pins with ancillary pull-up functionsNote resistors Real-time output port Timers Flash memory RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) 125 ns (@16 MHz operation with internal clock) 64 KB 2048 bytes 1 MB with program/data combined 65 17 48 29 Function
4 bits x 1 Timer 0: (16 bits) Timer 1: (16 bits) Timer counter x 1 Capture/compare register x 4 Timer counter x 1 Compare register x 2 Pulse output * Toggle output * Set/reset output Pulse output * Toggle output * Set/reset output Pulse output * Toggle output * PWM/PPG output Pulse output * Toggle output * PWM/PPG output Pulse output * Real-time output (4 bits x 1)
Timer/event counter 2: Timer counter x 1 (16 bits) Compare register x 2 Timer/event counter 3: Timer counter x 1 (16 bits) Compare register x 2 Timer 4: (16 bits) A/D converter Serial interface Watchdog timer Interrupts Sources Software Non-maskable Maskable Timer counter x 1 Compare register x 2
10-bit resolution x 16 channels UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator) 1 channel 27 (internal: 23, external: 8 (internal/external: 4)) + BRK instruction BRK instruction Internal: 1, external: 1 Internal: 22, external: 7 (internal/external: 4) * 4 programmable priority levels * 3 service modes: vectored interrupt/macro service/context switching
Bus sizing Standby Supply voltage Package
8-bit/16-bit external data bus width selectable HALT/STOP/IDLE modes VDD = 4.5 to 5.5 V 80-pin plastic QFP (14 x 14 mm)
Note
The pins with ancillary functions are included in the I/O pins.
Data Sheet U11447EJ2V0DS00
3
PD78F4046
CONTENTS
1. DIFFERENCES AMONG PD784046 SUBSERIES ........................................................................... 5 2. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 6 3. SYSTEM CONFIGURATION EXAMPLE (AC SERVO MOTOR CONTROL) .................................... 8 4. BLOCK DIAGRAM ...............................................................................................................................9 5. PIN FUNCTIONS ................................................................................................................................ 10
5.1 5.2 5.3 Port Pins .................................................................................................................................................... 10 Non-Port Pins ............................................................................................................................................ 12 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14
6. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ........................................................... 16 7. FLASH MEMORY PROGRAMMING ................................................................................................. 17
7.1 7.2 7.3 7.4 Selecting Communication Mode ............................................................................................................ 17 Function of Flash Memory Programming ............................................................................................. 18 Connection of Flashpro II and Flashpro III ........................................................................................... 18 Cautions When Writing to Flash Memory ............................................................................................. 19
8. ELECTRICAL SPECIFICATIONS ...................................................................................................... 21 9. PACKAGE DRAWING ........................................................................................................................32 10. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 33 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................34 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 37
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Data Sheet U11447EJ2V0DS00
PD78F4046
1. DIFFERENCES AMONG PD784046 SUBSERIES
The only difference between the PD784044 and PD784046 is the internal memory capacity. The PD78F4046 is a version of the PD784046 with the internal ROM replaced by flash memory. The differences are shown in Table 1-1. Table 1-1. Differences Among PD784046 Subseries
Part Number Item Internal ROM Internal RAM Function of pin 57
PD784044
32 KB (mask ROM) 1024 bytes MODE
PD784046
64 KB (mask ROM) 2048 bytes
PD78F4046
64 KB (flash memory)
MODE/VPP
Data Sheet U11447EJ2V0DS00
5
PD78F4046
2. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14 mm)
PD78F4046GC-3B9
P24/INTP3/TO03
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 AVREF AVDD VSS VDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P22/INTP1/TO01 BWD P21/INTP0/TO00 MODE/VPP P20/NMI VSS VDD P13/TO31 P12/TO30 P11/TO21 P10/TO20 P03/RTP3 P02/RTP2 P01/RTP1 P00/RTP0 P37/ASCK2/SCK2 P36/TxD2/SO2 P35/RxD2/SI2 P34/ASCK/SCK1 P33/TxD/SO1
P50/AD8
P51/AD9
P52/AD10
P53/AD11
P54/AD12
P55/AD13
P56/AD14
P57/AD15
P60/A16
P61/A17
P62/A18
P63/A19
P93/ASTB
P94/WAIT
P30/TO10
P31/TO11
Caution
Connect the MODE/VPP pin directly to VSS in normal operation mode.
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Data Sheet U11447EJ2V0DS00
P32/RxD/SI1
P90/RD
P91/LWR
P92/HWR
P23/INTP2/TO02
P27/INTP6/TI3
P26/INTP5/TI2
P25/INTP4
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
CLKOUT
RESET
AVSS
VDD
VSS
X2
X1
PD78F4046
P00 to P03: P10 to P13: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P63: P70 to P77: P80 to P87: P90 to P94: RTP0 to RTP3: NMI: INTP0 to INTP6: TO00 to TO03, TO10, TO11: TO20, TO21, TO30, TO31: TI2, TI3: RxD, RxD2: TxD, TxD2: ASCK, ASCK2: SI1, SI2,: SO1, SO2: SCK1, SCK2: Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Real-Time Port Nonmaskable Interrupt Interrupt from Peripherals Timer Output Timer Input Receive Data Transmit Data Asynchronous Serial Clock Serial Input Serial Output Serial Clock AD0 to AD15: A16 to A19: RD: LWR: HWR: ASTB: WAIT: BWD: MODE: CLKOUT: X1, X2: RESET: ANI0 to ANI15: AVREF: AVDD: AVSS: VDD: VPP: VSS: Address/Data Bus Address Bus Read Strobe Low Address Write Strobe High Address Write Strobe Address Strobe Wait Bus Width Definition Mode Clock Out Crystal Reset Analog Input Analog Reference Voltage Analog Power Supply Analog Ground Power Supply Programming Power Supply Ground
Data Sheet U11447EJ2V0DS00
7
PD78F4046
3. SYSTEM CONFIGURATION EXAMPLE (AC SERVO MOTOR CONTROL)
PD78F4046
Control panel Display Keypad I/O port Port INTP0 to INTP4 ANI8 to ANI15 Port TO10, TO11, TO20, TO21 Driver/switching circuit
AC motor
External tester
I/O interface circuit
ANI0 to ANI7 UART INTP5
Current/voltage sensor signal input circuit Limit switch
CPU-to-CPU communication
3-wire serial I/O AD0 to AD15 Encoder pulse counter Rotary encoder interface Rotary encoder
WDT
Flash memory 64 KB
RAM 2048 bytes
Macro service function
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Data Sheet U11447EJ2V0DS00
PD78F4046
4. BLOCK DIAGRAM
NMI INTP0 to INTP6
Programmable interrupt controller
UART/IOE1 Baud rate generator UART/IOE2 Baud rate generator
RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 BWD AD0 to AD15 A16 to A19 RD LWR, HWR ASTB WAIT P00 to P03 P10 to P13 P20 P21 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P63 P70 to P77 P80 to P87 P90 to P94 CLKOUT RESET MODE/VPP X1 X2 VDD VSS
INTP0 to INTP3 TO00 to TO03
Timer 0 (16 bits)
TO10, TO11
Timer 1 (16 bits) BUS I/F
INTP5/TI2 TO20, TO21
Timer/event counter 2 (16 bits) Timer/event counter 3 (16 bits)
78K/IV CPU core
Flash memory Port 0
INTP6/TI3 TO30, TO31
Port 1 Port 2
Timer 4 (16 bits) RAM RTP0 to RTP3 Real-time output port
Port 3 Port 4 Port 5 Port 6
ANI0 to ANI15 AVDD AVSS AVREF INTP4 A/D converter
Port 7 Port 8 Port 9
Watchdog timer
System control
Data Sheet U11447EJ2V0DS00
9
PD78F4046
5. PIN FUNCTIONS 5.1 Port Pins (1/2)
Pin Name P00 to P03 I/O I/O Alternate Function RTP0 to RTP3 Function Port 0 (P0): * 4-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software. Port 1 (P1): * 4-bit I/O port * Input/output can be specified in 1-bit units.
P10 P11 P12 P13 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
I/O
TO20 TO21 TO30 TO31
Input I/O
NMI INTP0/TO00 INTP1/TO01 INTP2/TO02 INTP3/TO03 INTP4 INTP5/TI2 INTP6/TI3
Port 2 (P2): * 8-bit I/O port
Input only Input/output can be specified in 1-bit units.
I/O
TO10 TO11 RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
Port 3 (P3): * 8-bit I/O port * Input/output can be specified in 1-bit units.
I/O
AD0 to AD7
Port 4 (P4): * 8-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software. Port 5 (P5): * 8-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software. Port 6 (P6): * 4-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software.
P50 to P57
I/O
AD8 to AD15
P60 to P63
I/O
A16 to A19
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Data Sheet U11447EJ2V0DS00
PD78F4046
5.1 Port Pins (2/2)
Pin Name P70 to P77 P80 to P87 P90 P91 P92 P93 P94 I/O Input Input I/O Alternate Function ANI0 to ANI7 ANI8 to ANI15 RD LWR HWR ASTB WAIT Port 7 (P7): * 8-bit input-only port Port 8 (P8): * 8-bit input-only port Port 9 (P9): * 5-bit I/O port * Input/output can be specified in 1-bit units. * When used as an input port, an on-chip pull-up resistor can be specified by means of software. Function
Data Sheet U11447EJ2V0DS00
11
PD78F4046
5.2 Non-Port Pins (1/2)
Pin Name RTP0 to RTP3 NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 TO00 TO01 TO02 TO03 TO10 TO11 TO20 TO21 TO30 TO31 TI2 TI3 RxD RxD2 TxD TxD2 ASCK ASCK2 SI1 SI2 SO1 SO2 SCK1 SCK2 AD0 to AD7 AD8 to AD15 Note I/O Output Input Output Input Output I/O Output Input Alternate Function P00 to P03 P20 P21/TO00 P22/TO01 P23/TO02 P24/TO03 P25 P26/TI2 P27/TI3 P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P30 P31 P10 P11 P12 P13 P26/INTP5 P27/INTP6 P32/SI1 P35/SI2 P33/SO1 P36/SO2 P34/SCK1 P37/SCK2 P32/RxD P35/RxD2 P33/TxD P36/TxD2 P34/ASCK P37/ASCK2 P40 to P47 P50 to P57 External count clock input to timer/event counter 2 External count clock input to timer/event counter 3 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Lower multiplexed address/data bus for expanding memory externally * When 8-bit bus is specified Higher address bus for expanding memory externally * When external 16-bit bus is specified Higher multiplexed address/data bus for expanding memory externally Higher address bus for expanding memory externally Read strobe to external memory Timer output from timer Real-time output Non-maskable interrupt request input External interrupt request input Capture trigger signal of CC00 Capture trigger signal of CC01 Capture trigger signal of CC02 Capture trigger signal of CC03 Conversion start trigger input of A/D converter - Function
A16 to A19 Note RD
Output
P60 to P63 P90
Note
The number of pins used as address bus pins differs depending on the external address space.
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Data Sheet U11447EJ2V0DS00
PD78F4046
5.2 Non-Port Pins (2/2)
Pin Name LWR I/O Output Alternate Function P91 Function * When external 8-bit bus is specified Write strobe to external memory * When external 16-bit bus is specified Write strobe to external memory located at lower address Write strobe to external memory located at higher address when external 16-bit bus is specified Timing signal output that externally latches address information output from AD0 through AD15 pins to access external memory Wait insertion - VPP Output Input - Input - - - - P70 to P77 P80 to P87 - - - - - Input - MODE - Reference voltage application for A/D converter Positive power supply for A/D converter GND for A/D converter Positive power supply Flash memory programming mode setting Applying high-voltage for program write/verify. GND Bus width setting Connect directly to VSS in normal operation mode (for specification of IC test mode). Clock output Connecting crystal resonator for system clock oscillation (clock can be input to X1). Chip reset Analog voltage input for A/D converter
HWR ASTB WAIT BWD MODE CLKOUT X1 X2 RESET ANI0 to ANI7 ANI8 to ANI15 AVREF AVDD AVSS VDD VPP VSS Output Input
P92 P93 P94
Data Sheet U11447EJ2V0DS00
13
PD78F4046
5.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 5-1. For the I/O circuit configuration of each type, refer to Figure 5-1. Table 5-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name P00/RTP0 to P03/RTP3 P10/TO20 P11/TO21 P12/TO30 P13/TO31 P20/NMI P21/INTP0/TO00 P22/INTP1/TO01 P23/INTP2/TO02 P24/INTP3/TO03 P25/INTP4 P26/INTP5/TI2 P27/INTP6/TI3 P30/TO10 P31/TO11 P32/RxD/SI1 P33/TxD/SO1 P34/ASCK/SCK1 P35/RxD2/SI2 P36/TxD2/SO2 P37/ASCK2/SCK2 P40/AD0 to P47/AD7 P50/AD8 to P57/AD15 P60/A16 to P63/A19 P70/ANI0 to P77/ANI7 P80/ANI8 to P87/ANI15 P90/RD P91/LWR P92/HWR P93/ASTB P94/WAIT MODE RESET CLKOUT AVREF AVSS AVDD Connect to VDD. 1 2 3 - Output - Leave open. Connect to VSS. Input - 5-A I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. 9 Input Connect to VSS. 8 5-A 8 5 5 2 8 Input I/O Connect to VSS. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. I/O Circuit Type 5-A 5 I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
Remark Since type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).
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Data Sheet U11447EJ2V0DS00
PD78F4046
Figure 5-1. Pin I/O Circuits
Type 1
Type 5-A
VDD
VDD P-ch IN
Pullup enable Data
P-ch VDD P-ch IN/OUT
N-ch
Output disable Input enable
N-ch
Type 2
Type 8
VDD Data IN Output disable N-ch P-ch IN/OUT
Schmitt-triggered input with hysteresis characteristics Type 3 Type 9
VDD IN P-ch OUT N-ch
P-ch N-ch
Comparator
+ -
VREF (Threshold voltage)
Input enable
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Input enable
Data Sheet U11447EJ2V0DS00
15
PD78F4046
6. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting this register, the internal memory of the PD78F4046 can be mapped identically to that of a mask ROM version with a different internal memory (ROM and RAM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to DEH. Figure 6-1. Internal Memory Size Switching Register (IMS) Format
Address: 0FFFCH 7 IMS 1 6 1 After reset: DEH 5 ROM1 4 ROM0 3 1 R/W 2 1 1 RAM1 0 RAM0
ROM1 0 0
ROM0 0 1 32 KB 64 KB
Internal ROM Capacity Selection
Other than above
Setting prohibited
RAM1 0 1
RAM0 1 0 768 bytes 1.5 KB
Peripheral RAM Capacity Selection
Other than above
Setting prohibited
Table 6-1 shows the IMS setting values to make the memory mapping the same as that of the mask ROM versions. Table 6-1. Setting Values of Internal Memory Size Switching Register (IMS)
Target Mask ROM Version IMS Setting Value CDH Note DEH
PD784044, 784054 PD784046
Note
When IMS is set to CDH, the peripheral RAM capacity of the
PD78F4046 is 768 bytes, but that of the PD784044 or 784054 is
512 bytes. Consequently, when making a mask ROM version, be sure not to use 0FA00H through 0FAFFH in the peripheral RAM area of PD78F4046 (upon the execution of the LOCATION 0H instruction).
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Data Sheet U11447EJ2V0DS00
PD78F4046
7. FLASH MEMORY PROGRAMMING
The flash memory can be written with the PD78F4046 mounted on the target board (on-board write). Writing is performed with the dedicated flash programmer Flashpro II (part number: FL-PR2) and Flashpro III (part number: FL-PR3, PG-FP3)) connected to the host machine and the target system. Remark Flashpro II and III are products of Naito Densei Machida Mfg. Co., Ltd..
7.1 Selecting Communication Mode
Writing to flash memory is performed using the Flashpro II and III via a serial communication mode. Select a serial communication mode from those listed in Table 7-1. The selection of the communication mode is made by using the format shown in Figure 7-1. Each communication mode is selected by the number of VPP pulses shown in Table 7-1. Table 7-1. List of Communication Modes
Communication Mode 3-wire serial I/O Number of Channels 2 Pins Used P34/ASCK/SCK1 P33/TxD/SO1 P32/RxD/SI1 P37/ASCK2/SCK2 P36/TxD2/SO2 P35/RxD2/SI2 UART 2 P33/TxD/SO1 P32/RxD/SI1 P36/TxD2/SO2 P35/RxD2/SI2 9 8 1 0 Number of VPP Pulses
Figure 7-1. Format of Communication Mode Selection
10 V MODE/VPP VDD VSS VDD VSS
RESET
Data Sheet U11447EJ2V0DS00
17
PD78F4046
7.2 Function of Flash Memory Programming
Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 7-2 shows the major functions of flash memory programming. Table 7-2. Major Functions of Flash Memory Programming
Function Batch erase Block erase Batch blank check Block blank check Data write Erases the entire memory contents. Erases the contents of the specified memory block, with one memory block consisting of 16 KB. Checks the erasure status of the entire memory. Checks the erasure status of the specified block. Writes to the flash memory based on the write start address and the amount of data to be written (number of bytes). Compares the entire memory contents with the input data. Compares the contents of the specified memory block with the input data. Description
Batch verify Block verify
7.3 Connection of Flashpro II and Flashpro III
The connection of the dedicated flash programmer and the PD78F4046 differs according to the communication mode (3-wire serial I/O or UART). The connection for each communication mode is shown in Figures 7-2 and 7-3. Figure 7-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O Mode
VPP VDD RESET Flashpro II, Flashpro III SCK1 or SCK2 SI1 or SI2 SO1 or SO2 VSS
PD78F4046
Figure 7-3. Connection of Flashpro II and Flashpro III in UART Mode
VPP VDD RESET Flashpro II, Flashpro III RxD or RxD2 TxD or TxD2 VSS
PD78F4046
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Data Sheet U11447EJ2V0DS00
PD78F4046
7.4 Cautions When Writing to Flash Memory
For writing data to the flash memory of the PD78F4046, use the prewrite and ECC functions. Moreover, set the flash programmer as follows when writing to flash memory using these functions. Either 1-bit or 8-bit memory manipulation instructions can be used to make these settings. (1) Using prewrite function To improve flash memory rewrite characteristics, prewriting is necessary before erasing. Prewriting involves writing 00H to all the data. This is performed to delete the bits that are already 1 in the data (erasure state), and to prevent further erasure stress. (2) Using ECC function When writing to the PD78F4046 and shipping it as a product, ECC data needs to be written in the ECC data area of flash memory. By writing ECC data and setting the ECC function, data writing can be performed correctly. <1> Creating ECC data Convert the EX file to an ECC-attached HEX file using the ECC generator included in the assembly package (Ver. 1.20 or later for PC). Download this ECC-attached HEX file to the flash programmer, and then write. [ECC data creating method] * Prepare the HEX file created by the object converter of the assembly package. * Convert it to the program data + HEX file using the ECC generator (ECCGEN.EXE) included in the assembly package. Example Convert the file "file.hex" to "file_ec.hex". ec file.hex-ofile_ec.hex -a0ffffh, 10000h, 14000h, 14004h <2> Flash programmer (Flashpro II, Flashpro III) setting and writing Prewriting and ECC writing are performed by Flashpro II and Flashpro III. The setting method when using an earlier version than Flashpro II Ver. 2.50 is described below. Remark If using Flashpro II Ver. 2.50 or later or Flashpro III (PG-FP3 (Ver. 3.040 or later, products of NEC Corporation)), setting is not necessary. Setting is performed automatically by reading parameter files.
Data Sheet U11447EJ2V0DS00
19
PD78F4046
[When earlier version than Flashpro II Ver. 2.50 is used] a. Connect the PC and FL-PR2, then start up the control software "flashpro.exex". b. Press the CTRL + GRPH (ART) + P keys at the same time. c. Check the check box of Pre-Write set. d. Press the OK button. e. Select Setting. f. Select Option. g. Check the ECC code area in the menu window. h. Input 14004 to ECC END ADDRESS i. Press the OK button. j. Press the TYPE button. k. Input 14004 to END ADDRESS l. Press the OK button ECC write setting Prewrite setting
[Writing method] a. Download the ECC-attached HEX file to the flash programmer. b. Set to chip mode and write using the E.P.V button. Do not use the Program command, since this will disable writing to ECC.
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Data Sheet U11447EJ2V0DS00
PD78F4046
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage VI1 VI2 Output voltage Output current, low VO IOL All output pins Total of all output pins Output current, high IOH All output pins Total of all output pins Analog input voltage VIAN Note 2 AVDD > VDD VDD AVDD A/D converter reference input voltage Operating ambient temperature Storage temperature TA Tstg AVREF AVDD > VDD VDD AVDD Note 1 TEST/VPP pin in the programming mode Conditions Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 7.0 -0.5 to +11.0 -0.5 to VDD + 0.5 15 150 -10 -100 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -10 to +70 -40 to +125 C C V Unit V V V V V V mA mA mA mA V
Notes 1. Pins other than the pins specified in Note 2. 2. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. Recommended Operating Conditions
Oscillation Frequency 8 MHz fXX 32 MHz TA -10 to +70C VDD 4.5 to 5.5 V
Capacitance (TA = 25C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz Unmeasured pins returned to 0 V. Conditions MIN. TYP. MAX. 10 10 10 Unit pF pF pF
Data Sheet U11447EJ2V0DS00
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PD78F4046
Flash Memory Specifications (TA = +10 to +40C (rewriting), TA = -10 to +70C (other than rewriting))
Parameter VDD supply voltage VPP supply voltage Number of rewrites Note Symbol VDD VPP VPP high-voltage detection Conditions MIN. 4.5 9.7 10 10.0 TYP. MAX. 5.5 10.3 Unit V V Times
Note
If the number of flash memory rewrites exceeds 10, operation is not guaranteed.
Oscillator Characteristics (TA = -10 to +70C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator Recommended Circuit Parameter Oscillation frequency (fXX) MIN. 8 MAX. 32 Unit MHz
VSS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
8
32
MHz
X1
X2 OpenNote HCMOS inverter
X1 input high-/low-level width 20 105 ns X1 input rise/fall time 0 5 ns
Note
When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of pin X1 to pin X2 when the EXTC bit = 1.
Caution
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Data Sheet U11447EJ2V0DS00
PD78F4046
DC Characteristics (TA = -10 to +70C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Input voltage, low Input voltage, high Symbol VIL VIH1 VIH2 Output voltage, low Output voltage, high Input leakage current Analog pin input leakage current Output leakage current VDD supply current VOL VOH ILI ILIAN ILO IDD1 IDD2 IDD3 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 IOL = 2.0 mA IOH = -400 A Note 3 Note 4 0 V VO VDD Operating mode (fXX = 32 MHz) HALT mode (fXX = 32 MHz) IDLE mode (fXX = 32 MHz) STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5 V 10% Pull-up resistor RL 15 2.5 2 15 40 15 50 80 50 30 10 0 V VI VDD 0 V VI AVDD VDD - 1.0 10 1 10 80 60 20 Conditions MIN. 0 2.2 0.8VDD TYP. MAX. 0.8 VDD VDD 0.45 V V Unit V V
A A A
mA mA mA V
A A
k
Notes 1. Pins other than the pins specified in Note 2 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 used as analog inputs) 4. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 (pins used as analog inputs, and only during a non-sampling operation)
Data Sheet U11447EJ2V0DS00
23
PD78F4046
AC Characteristics (TA = -10 to +70C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation
Parameter System clock cycle time Address setup time (to ASTB) Address hold time (from ASTB) ASTB high-level width RD delay time from address Address float time from RD Data input time from address Data input time from RD Delay time from ASTB to RD Data hold time (from RD) Address active time from RD RD low-level width Delay time from address to LWR, HWR Data output time from LWR, HWR Delay time from ASTB to LWR, HWR Data setup time (to LWR, HWR) Data hold time (from LWR, HWR) Delay time from LWR, HWR to ASTB LWR, HWR low-level width WAIT input time from address WAIT input time from ASTB WAIT hold time from ASTB Delay time from ASTB to WAIT WAIT input time from RD WAIT hold time from RD Delay time from RD to WAIT WAIT input time from LWR, HWR WAIT hold time from LWR, HWR Delay time from LWR, HWR to WAIT Symbol tCYK tSAST tHSTA tWSTH tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tDAW tDWOD tDSTW tSODW tHWOD tDWST tWWL tDAWT tDSTWT tHSTWT tDSTWTH tDRWT tHRWT tDRWTH tDWWT tHWWT tDWWTH 0.5T - 16 (1.5 + n) T - 25 0.5T - 14 1.5T - 15 (1.5 + n) T - 36 (2 + a) T - 50 1.5T - 40 (1.5 + n) T + 5 (2.5 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 T - 40 (1 + n) T + 5 (1 + n) T - 40 67.5 85 Note 67.5 85 Note 22.5 98.8 116.2 Note 22.5 15.3 68.7 17.2 78.8 57.7 75 53.7 0.5T - 14 (1.5 + n) T - 30 (1 + a) T - 15 (2.5 + a + n) T - 56 (1.5 + n) T - 48 0.5T - 16 15.3 0 17.2 63.7 47.5 15 (0.5 + a) T - 20 0.5T - 20 (0.5 + a) T - 17 (1 + a) T - 15 Expression MIN. 62.5 11.2 11.2 14.2 47.5 0 100.2 45.7 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise 0. 3. n indicates the number of the wait cycles as specified by the external wait pin (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n 0. n 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 62.5 ns.
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Data Sheet U11447EJ2V0DS00
PD78F4046
Serial Operation (TA = -10 to +70C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Conditions SCK1, SCK2 output BRG SCK1, SCK2 input Serial clock low-level width tWSKL External clock MIN. TSFT 500 0.5TSFT-40 210 0.5TSFT-40 210 80 80 R = 1 k, C = 100 pF 0 150 MAX. Unit ns ns ns ns ns ns ns ns ns
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
Serial clock high-level width
tWSKH
SCK1, SCK2 output BRG SCK1, SCK2 input External clock
SI1, SI2 setup time (to SCK1, SCK2) SI1, SI2 hold time (from SCK1, SCK2) Delay time from SCK1, SCK2 to SO1, SO2 output
tSSSK tHSSK tDSBSK
Remarks 1. TSFT is a value set by software. The minimum value is tCYK x 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = -10 to +70C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter NMI high-/low-level width Symbol tWNIH, tWNIL Conditions MIN. 10 4 4 10 MAX. Unit
s
tCYSMP tCYSMP
INTP0 to INTP6 high-/low-level width tWITH, tWITL TI2, TI3 high-/low-level width RESET high-/low-level width tWTIH, tWTIL tWRSH, tWRSL
s
Remarks 1. tCYSMP is a sampling clock set by software in the noise protection control register (NPC). When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK x 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0 to 6) AC Timing Test Points
VDD 0.8VDD or 2.2 V 0.8 V 0V Test points 0.8VDD or 2.2 V 0.8 V
Data Sheet U11447EJ2V0DS00
25
PD78F4046
AD Converter Characteristics (TA = -10 to +70C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD)
Parameter Resolution Overall error Note 1 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Quantization error Conversion time tCONV 80 ns tCYK 250 ns 62.5 ns tCYK < 80 ns Sampling time tSAMP 80 ns tCYK 250 ns 62.5 ns tCYK < 80 ns Zero-scale error Note 1 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Full-scale errorNote 1 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Integral linearity errorNote 1 4.5 V AVREF AVDD 3.4 V AVREF < 4.5 V Analog input voltage A/D converter reference input voltage AVREF current AVDD supply current A/D converter data retention current VIAN AVREF AIREF AIDD AIDDDR STOP mode AVDDDR = 2.5 V AVDDDR = 5 V 10% -0.3 3.4 1.0 2.0 2 10 169 208 20 24 1.5 1.5 1.5 1.5 1.5 1.5 3.5 4.5 3.5 4.5 2.5 4.5 AVREF + 0.3 AVDD 3.0 6.0 10 50 Symbol Conditions MIN. 10 0.5 0.7 1/2 TYP. MAX. Unit bit %FSRNote 2 %FSRNote 2 LSB tCYK tCYK tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA
A A
Notes 1. 2.
Excludes quantization error. Indicated as a ratio (%FSR) to the full-scale value.
Remark tCYK = 1/fCLK (fCLK is the internal system clock frequency)
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Data Sheet U11447EJ2V0DS00
PD78F4046
Read Operation (8 bits)
tCYK (CLK)
AD8 to AD15 (Output) tSAST AD0 to AD7 (I/O) Hi-Z tDAID
Higher address
Higher address
Lower address (output) tWSTH
Hi-Z
Data (input)
Hi-Z
Lower address (output)
Hi-Z
tHRID
ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDAR tWRL tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tDRA
Data Sheet U11447EJ2V0DS00
27
PD78F4046
Write Operation (8 bits)
tCYK (CLK)
AD8 to AD15 (Output) tSAST AD0 to AD7 (Output) Lower address (output) tWSTH ASTB (Output) tHSTA LWR (Output) tDSTW
Higher address
Higher address
Undefined
Data (output) tHWOD
Lower address (output)
tDWST
tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tWWL
tSODW
tHWWT tDWWTH
tDAWT WAIT (Input)
28
Data Sheet U11447EJ2V0DS00
PD78F4046
Read Operation (16 bits)
tCYK (CLK)
tSAST AD8 to AD15 AD0 to AD7 (I/O) Hi-Z
tDAID Hi-Z Data (input) Hi-Z Address (output) Hi-Z
Address (output) tWSTH
tHRID
ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDAR tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tWRL tDRA
Data Sheet U11447EJ2V0DS00
29
PD78F4046
Write Operation (16 bits)
tCYK (CLK)
AD8 to AD15 AD0 to AD7 (Output)
tSAST Address (output) tWSTH Undefined Data (output) tHWOD Address (output)
ASTB (Output) tHSTA HWR, LWR (Output) tDSTW tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tHWWT tDWWTH tWWL tSODW tDWST
tDAWT WAIT (Input)
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Data Sheet U11447EJ2V0DS00
PD78F4046
Serial Operation
tCYSK tWSKL SCK1, SCK2 tDSBSK SO1, SO2 tWSKH
SI1, SI2 tSSSK tHSSK
Interrupt Input Timing
tWNIH
tWNIL
0.8VDD NMI 0.8 V
tWITH
tWITL
0.8VDD INTP0 to INTP6 0.8 V
Reset Input Timing
tWRSH tWRSL
0.8VDD RESET 0.8 V
Timer Input Timing
tWTIH tWTIL
0.8VDD TI2, TI3 0.8 V
Data Sheet U11447EJ2V0DS00
31
PD78F4046
9. PACKAGE DRAWING
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S CD Q R
80 1
21 20
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. S80GC-65-3B9-6
32
Data Sheet U11447EJ2V0DS00
PD78F4046
10. RECOMMENDED SOLDERING CONDITIONS
The PD78F4046 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC representative. Table 10-1. Surface Mounting Type Soldering Conditions
PD78F4046GC-3B9: 80-pin plastic QFP (14 x 14 mm)
Recommended Condition Symbol IR35-207-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 days Note (after 7 days, prebake at 125C for 20 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 days Note (after 7 days, prebake at 125C for 20 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 days Note (after 7 days, prebake at 125C for 20 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-207-2
Wave soldering
WS60-207-1
Partial heating
-
Note
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Do not use different soldering methods together (except for partial heating).
Caution
Data Sheet U11447EJ2V0DS00
33
PD78F4046
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78F4046. Refer to (5) Cautions on using development tools. (1) Language processing software
RA78K4 CC78K4 DF784046 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file for PD784046 Subseries C compiler library source file common to 78K/IV Series
(2) Flash memory writing tools
Flashpro II (Model FL-PR2), Flashpro III (Model FL-PR3, PG-FP3) FA-80GC Adapter for flash memory programming Dedicated flash programmer for microcontrollers incorporating flash memory
(3) Debugging tools * When IE-78K4-NS in-circuit emulator is used
In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter necessary when a PC-9800 series PC (except notebook PC) is used as the host machine (C bus supported) PC card and interface cable necessary when a PC-9800 series notebook PC is used as the host machine (PCMCIA socket supported) Interface adapter necessary when an IBM PC/ATTM -compatible is used as the host machine (ISA bus supported) Emulation board for emulating PD784046 Subseries Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file for the PD784046 Subseries
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF IE-70000-PC-IF-C IE-784046-NS-EM1 NP-80GC EV-9200GC-80 ID78K4-NS SM78K4 DF784046
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Data Sheet U11447EJ2V0DS00
PD78F4046
* When using the IE-784000-R in-circuit emulator
IE-784000-R IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-784000-R-EM IE-784046-NS-EM1 IE-784046-R-EM1 IE-78K4-R-EX2 EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784046 In-circuit emulator common to 78K/IV Series Interface adapter necessary when a PC-9800 series PC (except notebook PC) is used as the host machine (C bus supported) Interface adapter necessary when an IBM PC/AT-compatible is used as the host machine (ISA bus supported) Interface adapter necessary when PC that incorporates PCI bus is used as host machine Interface adapter and cable necessary when an EWS is used as the host machine Emulation board common to 78K/IV Series Emulation board for emulating PD784046 Subseries Emulation probe conversion board necessary when the IE-784046-NS-EM1 is used in the IE-784000-R. Not necessary when the IE-784046-R-EM1 is used. Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket to be mounted on the board of the target system made for the 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file for PD784046 Subseries
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series
Data Sheet U11447EJ2V0DS00
35
PD78F4046
(5) Cautions on using development tools * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784046. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784046. * FL-PR2, FL-PR3, FA-80GC, and NP-80GC are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: +8144-822-3813). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] PC PC-9800 series IBM PC/AT-compatible [Japanese/English Windows] Note Note Note
Note
EWS HP9000 series 700 TM [HP-UXTM ] SPARCstation TM [SunOSTM, Solaris TM] NEWS TM (RISC) [NEWS-OSTM ] - -
[Windows TM]
Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note
DOS-based software
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Data Sheet U11447EJ2V0DS00
PD78F4046
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Japanese Document No. English U10951E This manual U11515E - U10905E - - U10095E
PD784044, 784046 Data Sheet PD78F4046 Data Sheet PD784046 Subseries User's Manual - Hardware PD784046 Subseries Special Function Register Table
78K/IV Series User's Manual - Instruction 78K/IV Series Instruction List 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
U10951J U11447J U11515J U10986J U10905J U10594J U10595J U10095J
Documents Related to Development Tools (User's Manuals)
Document Japanese RA78K4 Assembler Package Operation Language RA78K4 Structured Assembler Preprocessor CC78K4 C Compiler Operation Language IE-78K4-NS IE-784000-R IE-784046-NS-EM1 IE-784046-R-EM1 EP-78230 SM78K4 System Simulator Windows Based SM78K Series System Simulator ID78K4-NS Integrated Debugger PC Based ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based Reference U11334J U11162J U11743J U11572J U11571J U13356J U12903J U13744J U11677J EEU-985 U10093J Document No. English U11334E U11162E U11743E U11572E U11571E U13356E U12903E U13744E U11677E EEU-1515 U10093E U10092E U12796E U10440E U11960E
External Part User Open U10092J Interface Specifications Reference Reference Reference U12796J U10440J U11960J
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U11447EJ2V0DS00
37
PD78F4046
Documents Related to Embedded Software (User's Manuals)
Document Japanese 78K/IV Series Real-Time OS Fundamentals Installation Debugger 78K/IV Series OS MX78K4 Fundamental U10603J U10604J U10364J U11779J Document No. English U10603E U10604E - -
Other Documents
Document Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Parties X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E - Document No. English
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
38
Data Sheet U11447EJ2V0DS00
PD78F4046
[MEMO]
Data Sheet U11447EJ2V0DS00
39
PD78F4046
[MEMO]
40
Data Sheet U11447EJ2V0DS00
PD78F4046
[MEMO]
Data Sheet U11447EJ2V0DS00
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PD78F4046
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Data Sheet U11447EJ2V0DS00
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U11447EJ2V0DS00
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PD78F4046
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
* The information in this document is current as of July, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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