View UPD78P4038_96351.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD78P4038
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The PD78P4038, 78K/IV Series' product, is a one-time PROM or EPROM version of the PD784035, PD784036, PD784037, and PD784038 with internal masked ROM. Since user programs can be written to PROM, this microcontroller is best suited for evaluation in system development, manufacture of small quantities of multiple products, and fast start-up of applications. For specific functions and other detailed information, consult the following user's manual. This manual is required reading for design work. PD784038, 784038Y Subseries User's Manual, Hardware : U11316E 78K/IV Series User's Manual, Instruction : U10905E
FEATURES
* Compatible with the PD78P238, PD78P4026, and PD78P4038Y * Internal PROM: 128 Kbytes * PD78P4038KK-T : EPROM (best suited for system evaluation) * PD78P4038GC-3B9 : One-time PROM (best suited for manufacture of small quantities)
PD78P4038GC-8BT : One-time PROM (best suited for manufacture of small quantities) PD78P4038GK-BE9 : One-time PROM (best suited for manufacture of small quantities) * Internal RAM : 4,352 bytes * Power supply voltage : VDD = 2.7 to 5.5 V * QTOPTM microcomputer (In the planning phase)
Remark The QTOP microcomputer is a microcomputer with a built-in one-time PROM that is totally supported by NEC. The support includes writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 x 14 x 2.7 mm) 80-pin plastic QFP (14 x 14 x 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN (14 x 14 mm) Internal ROM One-time PROM One-time PROM (QTOP microcomputer) One-time PROM One-time PROM One-time PROM (QTOP microcomputer) EPROM
PD78P4038GC-3B9 PD78P4038GC-8BT PD78P4038GK-BE9 PD78P4038KK-T
PD78P4038GC-xxx-3B9 80-pin plastic QFP (14 x 14 x 2.7 mm)
PD78P4038GK-xxx-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
In this reference, all ROM components that are common to one-time PROM and EPROM are referred to as PROM.
The information in this document is subject to change without notice. Document No. U10848EJ2V0DS00 (2nd edition) Date Published July 1998 J CP(K) Printed in Japan The mark shows major revised points.
(c)
1995
PD78P4038
QUALITY GRADE
Part number Package 80-pin plastic QFP (14 x 14 x 2.7 mm) 80-pin plastic QFP (14 x 14 x 2.7 mm) 80-pin plastic QFP (14 x 14 x 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN (14 x 14 mm) Quality grade Standard (for general electronic equipment) Standard (for general electronic equipment) Standard (for general electronic equipment) Standard (for general electronic equipment) Standard (for general electronic equipment) Not applied (for function evaluation)
PD78P4038GC-3B9 PD78P4038GC-xxx-3B9 PD78P4038GC-8BT PD78P4038GK-BE9 PD78P4038GK-xxx-BE9 PD78P4038KK-T
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Caution The EPROM versions of the PD78P4038 are not intended for use in mass-produced products; they do not have reliability high enough for such purposes. Their use should be restricted to functional evaluation in experiment or trial manufacture. Remark xxx indicates ROM code suffix.
2
PD78P4038
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
: Under mass production : Under development
I2C bus supported
Multimaster I2C bus supported
PD784038Y
Standard models
PD784225Y PD784225
80 pins, added ROM correction Multimaster I2C bus supported
PD784038
Enhanced internal memory capacity, pin compatible with the PD784026 Multimaster I2C bus supported
PD784026
Enhanced A/D, 16-bit timer, and power management
PD784216Y PD784216
100 pins, enhanced I/O and internal memory capacity
PD784218Y PD784218
Enhanced internal memory capacity, added ROM correction
PD784054 PD784046
ASSP models Equipped with 10-bit A/D
PD784955
For DC inverter control
PD784937 PD784908
Equipped with controller IEBusTM Enhanced function of the PD784908, enhanced internal memory capacity, added ROM correction
Multimaster I2C bus supported
PD784928Y PD784928 PD784915
For software servo control, equipped with analog circuit for VCR, enhanced timer Enhanced function of the PD784915
3
PD78P4038
FUNCTIONS
(1/2)
Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O ports Total Input Input/output Additional function pinsNote Pins with pullup resistor LED direct drive outputs Transistor direct drive Real-time output ports Timer/counter PROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) 125 ns/250 ns/500 ns/1,000 ns (at 32 MHz) Functions
128 Kbytes (Can be changed to 48 K, 64 K, or 96 Kbytes by software) 4,352 bytes (Can be changed to 2,048 or 3,584 bytes by software) Program and data: 1 Mbyte 64 8 56 54
24
8 4 bits x 2, or 8 bits x 1 Timer/counter 0: Timer register x 1 (16 bits) Capture register x 1 Compare register x 2 Timer/counter 1: Timer register x 1 (8/16 bits) Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer/counter 2: Timer register x 1 (8/16 bits) Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer 3 (8/16 bits) : Timer register x 1 Compare register x 1 Pulse output capability * Toggle output * PWM/PPG output * One-shot pulse output Pulse output capability * Real-time output (4 bits x 2)
Pulse output capability * Toggle output * PWM/PPG output
PWM outputs Serial interface
12-bit resolution x 2 channels UART/IOE (3-wire serial I/O): 2 channels (incorporating baud rate generator) CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel 8-bit resolution x 8 channels 8-bit resolution x 2 channels
A/D converter D/A converter
Note Additional function pins are included in the I/O pins.
4
PD78P4038
(2/2)
Item Clock output Watchdog timer Standby Interrupt Functions Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port) 1 channel HALT/STOP/IDLE mode Hardware source 23 (16 internal, 7 external (sampling clock variable input: 1)) Software source Nonmaskable Maskable BRK instruction, BRKCS instruction, operand error 1 internal, 1 external 15 internal, 6 external * 4-level programmable priority * 3 operation statuses: vectored interrupt, macro service, context switching Supply voltage Package VDD = 2.7 to 5.5 V 80-pin 80-pin 80-pin 80-pin plastic QFP (14 x 14 x 2.7 mm) plastic QFP (14 x 14 x 1.4 mm) plastic TQFP (fine pitch) (12 x 12 mm) ceramic WQFN (14 x 14 mm)
5
PD78P4038
CONTENTS
1. 2. 3. 4.
DIFFERENCES BETWEEN PD78P4038 AND MASKED ROM PRODUCTS ....................... PIN CONFIGURATION (TOP VIEW) ......................................................................................... BLOCK DIAGRAM ..................................................................................................................... LIST OF PIN FUNCTIONS .........................................................................................................
4.1 4.2 Pins for Normal Operating Mode ................................................................................................... Pins for PROM Programming Mode (VPP +5 V or +12.5 V, RESET = L) ................................. 4.2.1 4.2.2 4.3 Pin functions ....................................................................................................................... Pin functions .......................................................................................................................
7 8 11 12
12 15 15 16 17
I/O Circuits for Pins and Handling of Unused Pins ....................................................................
5. 6.
INTERNAL MEMORY SWITCHING REGISTER (IMS) ............................................................ PROM PROGRAMMING ............................................................................................................
6.1 6.2 6.3 Operation Mode ................................................................................................................................ PROM Write Sequence .................................................................................................................... PROM Read Sequence ....................................................................................................................
20 21
21 23 27
7. 8. 9.
ERASURE CHARACTERISTICS (PD78P4038KK-T ONLY) ................................................. PROTECTIVE FILM COVERING THE ERASURE WINDOW (PD78P4038KK-T ONLY) .... QUALITY .....................................................................................................................................
28 28 28 28 29 55 59 61
10. SCREENING ONE-TIME PROM PRODUCTS .......................................................................... 11. ELECTRICAL CHARACTERISTICS ......................................................................................... 12. PACKAGE DRAWINGS ............................................................................................................. 13. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A DEVELOPMENT TOOLS ......................................................................................... APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW) ........................................................................................................ APPENDIX C RELATED DOCUMENTS .........................................................................................
64 67
6
PD78P4038
1. DIFFERENCES BETWEEN PD78P4038 AND MASKED ROM PRODUCTS
The PD78P4038 is produced by replacing the masked ROM in the PD784035, PD784036, PD784037, or
PD784038 with PROM to which data can be written. The functions of the PD78P4038 are the same as those of
the PD784035, PD784036, PD784037, or PD784038 except for the PROM specification such as writing and verification, except that the PROM size can be changed to 48 K, 64 K, or 96 Kbytes, and except that the internal RAM size can be changed to 2,048 or 3,584 bytes. Table 1-1 shows the differences between these products. Table 1-1. Differences between the PD78P4038 and Masked ROM Products
Product Name Item Internal program memory * 128-Kbyte PROM * Can be changed to 48 K, 64 K, or 96 Kbytes by IMS * 48-Kbyte masked ROM * 64-Kbyte masked ROM * 96-Kbyte masked ROM * 128-Kbyte masked ROM
PD78P4038
PD784035
PD784036
PD784037
PD784038
Internal RAM
* 4,352-byte * 2,048-byte internal RAM internal RAM * Can be changed to 2,048 or 3,584 bytes by IMS * 80-pin plastic QFP (14 x 14 x 2.7 mm) * 80-pin plastic QFP (14 x 14 x 1.4 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN (14 x 14 mm)
* 3,584-byte internal RAM
* 4,352-byte internal RAM
Package
7
PD78P4038
2. PIN CONFIGURATION (TOP VIEW)
(1) Normal operating mode
* 80-pin plastic QFP (14 x 14 x 2.7 mm)
PD78P4038GC-3B9, PD78P4038GC-xxx-3B9
* 80-pin plastic QFP (14 x 14 x 1.4 mm)
PD78P4038GC-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD78P4038GK-BE9, PD78P4038GK-xxx-BE9
* 80-pin ceramic WQFN (14 x 14 mm)
PD78P4038KK-T
P25/INTP4/ASCK/SCK1
P31/TxD/SO1
P23/INTP2/CI
P30/RxD/SI1
P22/INTP1
P24/INTP3
P26/INTP5
P21/INTP0
P77/ANI7
P76/ANI6
P32/SCK0/SCL P33/SO0/SDA P34/ TO0 P35/ TO1 P36/ TO2 P37/ TO3 RESET VDD1 X2 X1 VSS1 P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P75/ANI5
P20/NMI
P27/SI0
AVREF3
AVREF2
AVREF1
ANO1
ANO0
AVDD
AVSS
P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P17 P16 P15 P14/TXD2/SO2 P13/RXD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS0 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2
P66/WAIT/HLDRQ
P65/WR
P64/RD
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Note Connect the TEST pin to VSS0 directly.
8
P43/AD3
PD78P4038
A8-A19 AD0-AD7 ANI0-ANI7 : Address bus : Address/data bus : Analog input P60-P67 P70-P77 RD REFRQ RESET RxD, RxD2 SCK0-SCK2 SCL SDA SI0-SI2 SO0-SO2 TEST TO0-TO3 TxD, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT WR X1, X2 : Port 6 : Port 7 : Read strobe : Refresh request : Reset : Receive data : Serial clock : Serial clock : Serial data : Serial input : Serial output : Test : Timer output : Transmit data : Power supply : Ground : Wait : Write strobe : Crystal
PWM0, PWM1 : Pulse width modulation output
ANO0, ANO1 : Analog output ASCK, ASCK2 : Asynchronous serial clock ASTB AVDD AVSS CI CLKOUT HLDAK HLDRQ NMI P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 : Address strobe : Analog power supply : Analog ground : Clock input : Clock output : Hold acknowledge : Hold request : Non-maskable interrupt : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5
AVREF1-AVREF3 : Reference voltage
INTP0-INTP5 : Interrupt from peripherals
9
PD78P4038
(2) PROM programming mode
* 80-pin plastic QFP (14 x 14 x 2.7 mm)
PD78P4038GC-3B9, PD78P4038GC-xxx-3B9
* 80-pin plastic QFP (14 x 14 x 1.4 mm)
PD78P4038GC-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD78P4038GK-BE9, PD78P4038GK-xxx-BE9
* 80-pin ceramic WQFN (14 x 14 mm)
PD78P4038KK-T
Open Open VDD Open VSS VSS VSS
(L)
Open
RESET VDD Open (L) VSS D0 D1 D2 D3 D4 D5 D6 D7 (L)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A9
Open
VDD (L)
Open
VPP VSS Open A0 A1 A2
A15
A14
A13
A12
A11
A10
A16
A8
A7
A6
A5
A4
PGM
CE
OE
Caution L VSS
: Connect these pins separately to the VSS pins through 10-k pull-down resistors. : To be connected to the ground.
Open : Nothing should be connected on these pins. RESET: Set a low-level input. A0-A16 CE D0-D7 OE PGM : Address bus : Chip enable : Data bus : Output enable : Program RESET : Reset VDD VPP VSS : Power supply : Programming power supply : Ground
10
(L)
A3
PD78P4038
3. BLOCK DIAGRAM
NMI INTP0-INTP5 INTP3 TO0 TO1 UART/IOE2 Baud-rate generator UART/IOE1 Timer/counter 0 (16 bits) Baud-rate generator Clocked serial interface Clock output Timer/counter 2 (16 bits) 78 K/IV CPU core (RAM 512 bytes) PROM (128 Kbytes) RXD/SI1 TXD/SO1 ASCK/SCK1 RXD2/SI2 TXD2/SO2 ASCK2/SCK2 SCK0/SCL SO0/SDA SI0 ASTB/CLKOUT AD0-AD7 A8-A15 A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK D0-D7Note A0-A16Note CENote OENote PGMNote RAM (3,840 bytes) Port 0 Port 1 Port 2 D/A converter Port 3 Port 4 Port 5 ANI0-ANI7 AVDD AVREF1 AVSS INTP5 Watchdog timer System control A/D converter Port 6 Port 7 P60-P67 P70-P77
RESET TEST X1 X2 Note VPP VDD0, VDD1 VSS0, VSS1
Programmable interrupt controller
INTP0
Timer/counter 1 (16 bits)
INTP1 INTP2/CI TO2 TO3
Timer 3 (16 bits)
Bus interface
P00-P03 P04-P07 PWM0
Real-time output port
P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57
PWM PWM1
ANO0 ANO1 AVREF2 AVREF3
Note In the PROM programming mode.
11
PD78P4038
4. LIST OF PIN FUNCTIONS
4.1 Pins for Normal Operating Mode
(1) Port pins (1/2)
Pin P00-P07 I/O I/O Alternate-Function - Function Port 0 (P0): * 8-bit I/O port. * Functions as a real-time output port (4 bits x 2). * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. * Can drive a transistor. Port 1 (P1): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. * Can drive LED.
P10 P11 P12 P13 P14 P15-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34-P37 P40-P47
I/O
PWM0 PWM1 ASCK2/SCK2 RXD2/SI2 TXD2/SO2 -
Input
Port 2 (P2): * 8-bit input-only port. INTP0 * P20 does not function as a general-purpose port (nonmaskable INTP1 interrupt). However, the input level can be checked by an interrupt service routine. INTP2/CI * The use of the pull-up resistors can be specified by software for pins INTP3 P22 to P27 (in units of 6 bits). INTP4/ASCK/SCK1 * The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by INTP5 CSIM1. NMI SI0
I/O
RXD/SI1 TXD/SO1 SCK0/SCL SO0/SDA TO0-TO3
Port 3 (P3): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together.
I/O
AD0-AD7
Port 4 (P4): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. * Can drive LED.
12
PD78P4038
(1) Port pins (2/2)
Pin P50-P57 I/O I/O Alternate-Function A8-A15 Function Port 5 (P5): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. * Can drive LED. Port 6 (P6): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together.
P60-P63 P64 P65 P66 P67 P70-P77
I/O
A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK
I/O
ANI0-ANI7
Port 7 (P7): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit.
13
PD78P4038
(2) Non-port pins (1/2)
Pin TO0-TO3 CI RXD RXD2 TXD TXD2 ASCK ASCK2 SDA SI0 SI1 SI2 SO0 SO1 SO2 SCK0 SCK1 SCK2 SCL NMI INTP0 Input I/O Output I/O Input Input Output I/O Output Input Input Alternate-Function P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P27 P30/RXD P13/RXD2 P33/SDA P31/TXD P14/TXD2 P32/SCL P25/INTP4/ASCK P12/ASCK2 P32/SCK0 P20 P21 Timer output Input of a count clock for timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data I/O (2-wire serial I/O) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock I/O (3-wire serial I/O0) Serial clock I/O (3-wire serial I/O1) Serial clock I/O (3-wire serial I/O2) Serial clock I/O (2-wire serial I/O) External interrupt request - * Input of a count clock for timer/counter 1 * Capture/trigger signal for CR11 or CR12 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR22 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR21 * Input of a count clock for timer/counter 0 * Capture/trigger signal for CR02 - Input of a conversion start trigger for A/D converter Time multiplexing address/data bus (for connecting external memory) High-order address bus (for connecting external memory) High-order address bus during address expansion (for connecting external memory) Strobe signal output for reading the contents of external memory Strobe signal output for writing on external memory Wait signal insertion Refresh pulse output to external pseudo static memory Input of bus hold request Output of bus hold response Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) Clock output Function
INTP1
P22
INTP2
P23/CI
INTP3
P24
INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB I/O Output Output Output Output Input Output Input Output Output
P25/ASCK/SCK1 P26 P40-P47 P50-P57 P60-P63 P64 P65 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT
CLKOUT
Output
ASTB
14
PD78P4038
(2) Non-port pins (2/2)
Pin RESET X1 X2 ANI0-ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD0Note 1 VDD1Note 1 VSS0Note 2 VSS1Note 2 TEST I/O Input Input - Input Output - P70-P77 - - Alternate-Function - - Chip reset Crystal input for system clock oscillation (A clock pulse can also be input to the X1 pin.) Analog voltage inputs for the A/D converter Analog voltage inputs for the D/A converter Application of A/D converter reference voltage Application of D/A converter reference voltage Positive power supply for the A/D converter Ground for the A/D converter Positive power supply of the port part Positive power supply except for the port part Ground of the port part Ground except for the port part Directly connect to VSS0. (The TEST pin is for the IC test.) Function
Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin. 2. The potential of the VSS0 pin must be equal to that of the VSS1 pin. 4.2 Pins for PROM Programming Mode (VPP +5 V or +12.5 V, RESET = L)
4.2.1 Pin functions
Pin Name VPP I/O - Function PROM programming mode selection High voltage input during program write or verification PROM programming mode selection Address bus I/O Input Data bus PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input during PROM programming mode - - Positive power supply GND
RESET A0-A16 D0-D7 CE OE PGM VDD VSS
Input
15
PD78P4038
4.2.2 Pin functions
(1) VPP (Programming power supply): Input Input pin for setting the PD78P4038 to the PROM programming mode. When the input voltage on this pin is +5 V or more and when RESET input goes low, the PD78P4038 enters the PROM programming mode. When CE is made low for VPP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal PROM cell selected by A0 to A16. (2) RESET (Reset): Input Input pin for setting the PD78P4038 to the PROM programming mode. When input on this pin is low, and when the input voltage on the VPP pin goes +5 V or more, the PD78P4038 enters the PROM programming mode. (3) A0 to A16 (Address bus): Input Address bus that selects an internal PROM address (0000H to 1FFFFH) (4) D0 to D7 (Data bus): I/O Data bus through which a program is written on or read from internal PROM (5) CE (Chip enable): Input This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or read. (6) OE (Output enable): Input This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a onebyte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7. (7) PGM (Program): Input The input pin for the operation mode control signal of the internal PROM. Upon activation, writing to the internal PROM is enabled. Upon inactivation, reading from the internal PROM is enabled. (8) VDD Positive power supply pin (9) VSS Ground potential pin
16
PD78P4038
4.3 I/O Circuits for Pins and Handling of Unused Pins
Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins. Figure 4-1 shows the configuration of these various types of I/O circuits. Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Pin P00-P07 P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RXD2/SI2 P14/TXD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-C I/O Input state: To be connected to VDD0 Output state: To be left open To be connected to VDD0 2-C To be connected to VDD0 2 Input To be connected to VDD0 or VSS0 8-C 5-H I/O Circuit Type 5-H I/O I/O Recommended Connection Method for Unused Pins Input state: To be connected to VDD0 Output state: To be left open
P26/INTP5 P27/SI0 P30/RXD/SI1 P31/TXD/SO1 P32/SCK0/SCL P33/SO0/SDA P34/TO0-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7
2-C
Input
5-H
I/O
Input state: To be connected to VDD0 Output state: To be left open
10-B
5-H
20-A
I/O
Input state:
To be connected to VDD0 or VSS0
Output state: To be left open ANO0, ANO1 ASTB/CLKOUT 12 4-B Output To be left open
17
PD78P4038
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
Pin RESET TEST AVREF1-AVREF3 AVSS AVDD To be connected to VDD0 I/O Circuit Type 2 1-A - I/O Input Recommended Connection Method for Unused Pins - To be connected to VSS0 directly To be connected to VSS0
Caution When the I/O mode of an I/O alternate-function pin is unpredictable, connect the pin to VDD0 through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K Series, those numbers are not always serial in each product. (Some circuits are not included.)
18
PD78P4038
Figure 4-1. I/O Circuits for Pins
Type 1-A Type 2-C
VDD0 Pull-up enable
VDD0 P IN
P
N VSS0 Type 2
IN
Schmitt trigger input with hysteresis characteristics
IN
Type 5-H
Schmitt trigger input with hysteresis characteristics
VDD0 Pull-up enable Data VDD0 P IN/OUT Output disable VSS0 N P
Type 4-B Data
VDD0 P OUT
Output disable
N VSS0
Push-pull output which can output high impedance (both the positive and negative channels are off.) Type 8-C
VDD0 Pull-up enable Data VDD0 P IN/OUT Output disable N VSS0 P
Input enable Type 12
Analog output voltage
P OUT N
Type 10-B
Type 20-A
VDD0
Data
VDD0 P IN/OUT
Pull-up enable
P
Output disable VSS0
Data Open drain Output disable
VDD0 P IN/OUT N VSS0
N
Comparator + - AVSS AVREF (Threshold voltage) Input enable P N
19
PD78P4038
5. INTERNAL MEMORY SWITCHING REGISTER (IMS)
This register enables the software to avoid using part of the internal memory. IMS can be set to establish the same memory mapping as used in ROM products that have different internal memory (ROM and RAM) configurations. IMS is set with 8-bit memory operation instructions. RESET input sets IMS to FFH. Figure 5-1. Internal Memory Switching Register (IMS)
7 IMS IMS7 6 IMS6 5 IMS5 4 IMS4 3 IMS3 2 IMS2 1 IMS1 0 IMS0 Address 0FFFCH After Reset FFH R/W W
IMS0-7 FFH EEH DCH CCH
Memory Size Same as the PD784038 Same as the PD784037 Same as the PD784036 Same as the PD784035
IMS is not contained in a mask ROM product (PD784035, PD784036, PD784037, or PD784038). But the action is not affected if the write command to IMS is executed to the mask ROM product.
20
PD78P4038
6. PROM PROGRAMMING
The PD78P4038 has an on-chip 128-KB PROM device for use as program memory. When programming, set the VPP and RESET pins for PROM programming mode. See (2) in Chapter 2 with regard to handling of other, unused pins. 6.1 Operation Mode
PROM programming mode is selected when +5 V or +12.5 V is added to the VPP pin or low-level input is added to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown in Table 6-1 below. In addition, the PROM contents can be read by setting read mode. Table 6-1. PROM Programming Operation Mode
Pin Operation Mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disable Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High impedance High impedance Data input High impedance Data input Data output High impedance RESET VPP VDD CE OE PGM D0-D7
Remark x = L or H
21
PD78P4038
(1) Read mode Set CE to L and OE to L to set read mode. (2) Output disable mode Set OE to H to set high impedance for data output and output disable mode. Consequently, if several PD78P4038 devices are connected to a data bus, the OE pins can be controlled to select data output from any of the devices. (3) Standby mode Set CE to H to set standby mode. In this mode, data output is set to high impedance regardless of the OE setting. (4) Page data latch mode At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode. In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit. (5) Page write mode After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1-ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting both CE and OE to L causes program verification to be executed. If programming is not completed after one program pulse, the write and verify operations may be repeated X times (where X 10). (6) Byte write mode Adding a 0.1-ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes byte write to be executed. Later, setting OE to L causes program verification to be executed. If programming is not completed after one program pulse, the write and verify operations may be repeated X times (where X 10). (7) Program verify mode Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each write operation. (8) Program inhibit mode Program inhibit mode is used to write to a single device when several PD78P4038 devices are connected in parallel to OE , VPP, and D0 to D7 pins. Use the page write mode or byte write mode described above for each write operation. Write operations cannot be done for devices in which the PGM pin has been set to H.
22
PD78P4038
6.2 PROM Write Sequence Figure 6-1. Page Program Mode Flowchart
Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X=X+1 0.1 ms program pulse No X = 10? Yes
Address = Address + 1
Verify 4 bytes Pass No Address = N? Yes VDD = 4.5-5.5 V, VPP = VDD
Fail
Pass
Verify all bytes All pass Write end
Fail
Defective
Remark G = Start address N = Program end address
23
PD78P4038
Figure 6-2. Page Program Mode Timing
Page data latch Page program Program verify
A2-A16
A0, A1
D0-D7 Data input VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Data output
24
PD78P4038
Figure 6-3. Byte Program Mode Flowchart
Start Address = G VDD = +6.5 V, VPP = +12.5 V X= 0 X= X + 1 0.1-ms program pulse Fail No X = 10? Address = Address + 1 Yes
Verify Pass No Address = N? Yes VDD = 4.5-5.5 V, VPP = VDD Pass
Verify all bytes All pass Write end
Fail
Defective
Remark G = Start address N = Program end address
25
PD78P4038
Figure 6-4. Byte Program Mode Timing
Program Program verify
A0-A16
D0-D7
Data input
Data output
VPP VPP VDD
VDD+1.5 VDD VDD
VIH CE VIL VIH PGM VIL VIH OE VIL
Cautions 1. Add VDD before VPP, and turn off the VDD after VPP. 2. Do not allow VPP to exceed +13.5 V including overshoot. 3. Reliability problems may result if the device is inserted or pulled out while +12.5 V is applied at VPP.
26
PD78P4038
6.3 PROM Read Sequence
Follow this sequence to read the PROM contents to an external data bus (D0 to D7). (1) Set the RESET pin to low level and add +5 V to the VPP pin. See (2) in Chapter 2 with regard to handling of other, unused pins. (2) Add +5 V to the VDD and VPP pins. (3) Input the data address to be read to pins A0 to A16. (4) Set read mode. (5) Output the data to pins D0 to D7. Figure 6-5 shows the timing of steps (2) to (5) above. Figure 6-5. PROM Read Timing
A0-A16
Address input
CE (input)
OE (input)
D0-D7
Hi-Z
Data output
Hi-Z
27
PD78P4038
7. ERASURE CHARACTERISTICS (PD78P4038KK-T ONLY)
Data written in the PD78P4038KK-T program memory can be erased (FFH); therefore users can write other data in the memory. To erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. Normally, ultraviolet light with a wavelength of 254 nm is employed. The amount of light required to completely erase the data is as follows: * Intensity of ultraviolet light x erasing time: 57.6 W*s/cm2 min. * Erasing time: About 80 minutes (When using a 12,000 W/cm2 ultraviolet lamp. It may, however, take more time due to lamp deterioration, dirt on the erasure window, or the like.) The ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. In addition, if a filter is attached to the ultraviolet lamp, remove the filter before erasure.
8. PROTECTIVE FILM COVERING THE ERASURE WINDOW (PD78P4038KK-T ONLY)
To prevent EPROM from being erased inadvertently by light other than that from the lamp used for erasing EPROM, or to prevent the internal circuits other than EPROM from malfunctioning by light, stick a protective film on the erasure window except when EPROM is to be erased.
9. QUALITY
The PD78P4038KK-T is not intended for use in mass-produced products; they do not have reliability high enough for such purposes. Their use should be restricted to functional evaluation in experiment or trial manufacture.
10. SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (PD78P4038GC-3B9, PD78P4038GC-8BT, and PD78P4038GK-BE9) due to their structure before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them and storing them at 125C for 24 hours.
28
PD78P4038
11. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage VI1 VI2 TEST/VPP pin and P21/INTP0/A9 pin in PROM programming mode Conditions Rating -0.5 to +7.0 AVSS to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to +13.5 Unit V V V V V
Output voltage Output low current
VO IOL At one pin Total of all output pins
-0.5 to VDD + 0.5 15 100 -10 -100 -0.5 to VDD + 0.3
V mA mA mA mA V
Output high current
IOH
At one pin Total of all output pins
A/D converter reference input voltage D/A converter reference input voltage Operating ambient temperature Storage temperature
AVREF1
AVREF2 AVREF3 TA Tstg
-0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150
V V C C
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values.
29
PD78P4038
OPERATING CONDITIONS * Operating ambient temperature (TA) * Power supply voltage and clock cycle time : -40 to +85C : See Figure 11-1. * Rise time and fall time (tr, tf) (at pins which are not specified) : 0 to 200 s
Figure 11-1. Power Supply Voltage and Clock Cycle Time
10,000 4,000
Clock cycle time tCYK [ns]
1,000 Guaranteed operating range 125 100 62.5
10
0
1
2 3 4 5 Power supply voltage [V]
6
7
CAPACITANCE (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions f = 1 MHz 0 V on pins other than measured pins MIN. TYP. MAX. 10 10 10 Unit pF pF pF
30
PD78P4038
OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = +4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal Recommended Circuit Parameter Oscillator frequency (fXX) MIN. 4 MAX. 32 Unit MHz
VSS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
32
MHz
X1
X2
X1 input rise and fall times (tXR, tXF) X1 input high-level and lowlevel widths (tWXH, tWXL)
0
10
ns
10
125
ns
HCMOS inverter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: * Minimize the wiring. * Never cause the wires to cross other signal lines. * Never cause the wires to run near a line carrying a large varying current. * Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator.
31
PD78P4038
OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = +2.7 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal Recommended Circuit Parameter Oscillator frequency (fXX) MIN. 4 MAX. 16 Unit MHz
VSS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
16
MHz
X1
X2
X1 input rise and fall times (tXR, tXF) X1 input high-level and lowlevel widths (tWXH, tWXL)
0
10
ns
10
125
ns
HCMOS inverter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: * Minimize the wiring. * Never cause the wires to cross other signal lines. * Never cause the wires to run near a line carrying a large varying current. * Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator.
32
PD78P4038
DC CHARACTERISTICS (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter Input low voltage Symbol VIL1 Conditions For pins other than those described in Notes 1, 2, 3, and 4 For pins described in Notes 1, 2, 3, and 4 VDD = +5.0 V 10% For pins described in Notes 2, 3, and 4 For pins other than those described in Note 1 For pins described in Note 1 VDD = +5.0 V 10% For pins described in Notes 2, 3, and 4 IOL = 2 mA VDD = +5.0 V 10% IOL = 8 mA For pins described in Notes 2 and 5 IOH = -2 mA VDD = +5.0 V 10% IOH = -5 mA For pins described in Note 4 EXTC = 0 0 V VI VIL2 EXTC = 0 VIH2 VI VDD VDD - 1.0 VDD - 1.4 MIN. -0.3 TYP. MAX. 0.3VDD Unit V
VIL2
-0.3
0.2VDD
V
VIL3
-0.3
+0.8
V
Input high voltage
VIH1
0.7VDD
VDD + 0.3
V
VIH2 VIH3
0.8VDD 2.2
VDD + 0.3 VDD + 0.3
V V
Output low voltage
VOL1 VOL2
0.4 1.0
V V
Output high voltage
VOH1 VOH2
V V
X1 input low current
IIL
-30
A A
X1 input high current
IIH
+30
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA, TEST 2. P40/AD0 to P47/AD7, P50/A8 to P57/A15 3. P60/A16 to P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK 4. P00 to P07 5. P10 to P17
33
PD78P4038
DC CHARACTERISTICS (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter Input leakage current Symbol IL| Conditions 0 V VI VDD For pins other than X1 when EXTC = 0 0 V VO VDD Operation mode fXX = 32 MHz VDD = +5.0 V 10% fXX = 16 MHz VDD = +2.7 to 3.3 V IDD2 HALT mode fXX = 32 MHz VDD = +5.0 V 10% fXX = 16 MHz VDD = +2.7 to 3.3 V IDD3 IDLE mode (EXTC = 0) fXX = 32 MHz VDD = +5.0 V 10% fXX = 16 MHz VDD = +2.7 to 3.3 V Pull-up resistor RL VI = 0 V 15 25 MIN. TYP. MAX. 10 10 45 Unit
A A
mA
Output leakage current VDD supply current
ILO IDD1
12
25
mA
13
26
mA
8
12
mA
12
mA
8
mA
80
k
34
PD78P4038
AC CHARACTERISTICS (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2)
Parameter Address setup time Symbol tSAST Conditions VDD = +5.0 V 10% MIN. (0.5 + a) T - 15 (0.5 + a) T - 31 ASTB high-level width tWSTH VDD = +5.0 V 10% (0.5 + a) T - 17 (0.5 + a) T - 40 Address hold time (to ASTB) tHSTLA VDD = +5.0 V 10% 0.5T - 24 0.5T - 34 Address hold time (to RD) Delay from address to RD tHRA tDAR VDD = +5.0 V 10% 0.5T - 14 (1 + a) T - 9 (1 + a) T - 15 Address float time (to RD) Delay from address to data input tFRA tDAID VDD = +5.0 V 10% 0 (2.5 + a + n) T - 37 (2.5 + a + n) T - 52 Delay from ASTB to data input tDSTID VDD = +5.0 V 10% (2 + n) T - 40 (2 + n) T - 60 Delay from RD to data input tDRID VDD = +5.0 V 10% (1.5 + n) T - 50 (1.5 + n) T - 70 Delay from ASTB to RD Data hold time (to RD) Delay from RD to address active tDSTR tHRID tDRA After program is read After data is read Delay from RD to ASTB RD low-level width tDRST tWRL VDD = +5.0 V 10% VDD = +5.0 V 10% 0.5T - 9 0 0.5T - 8 0.5T - 12 VDD = +5.0 V 10% 1.5T - 8 1.5T - 12 0.5T - 17 (1.5 + n) T - 30 (1.5 + n) T - 40 Address hold time (to WR) Delay from address to WR tHWA tDAW VDD = +5.0 V 10% 0.5T - 14 (1 + a) T - 5 (1 + a) T - 15 Delay from ASTB to data output tDSTOD VDD = +5.0 V 10% 0.5T + 19 0.5T + 35 Delay from WR to data output Delay from ASTB to WR tDWOD tDSTW 0.5T - 9 0.5T - 11 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks T: TCYK (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
35
PD78P4038
(1) Read/write operation (2/2)
Parameter Data setup time (to WR) Symbol tSODW Conditions VDD = +5.0 V 10% MIN. (1.5 + n) T - 30 (1.5 + n) T - 40 Data hold time (to WR)Note tHWOD VDD = +5.0 V 10% 0.5T - 5 0.5T - 25 Delay from WR to ASTB WR low-level width tDWST tWWL VDD = +5.0 V 10% 0.5T - 12 (1.5 + n) T - 30 (1.5 + n) T - 40 MAX. Unit ns ns ns ns ns ns ns
Note The hold time includes the time during which VOH1 and VOL1 are held under the load conditions of CL = 50 pF and RL = 4.7 k. Remarks T: TCYK (system clock cycle time) n: Number of wait states (n 0) (2) Bus hold timing
Parameter Delay from HLDRQ to float Symbol tFHQC Conditions MIN. MAX. (6 + a + n) T + 50 (7 + a + n) T + 30 (7 + a + n) T + 40 Delay from float to HLDAK Delay from HLDRQ to HLDAK tDCFHA tDHQLHAL VDD = +5.0 V 10% 1T + 30 2T + 40 2T + 60 Delay from HLDAK to active tDHAC VDD = +5.0 V 10% 1T - 20 1T - 30 Unit ns ns ns ns ns ns ns ns
Delay from HLDRQ to HLDAK tDHQHHAH VDD = +5.0 V 10%
Remarks T: TCYK (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0)
36
PD78P4038
(3) External wait timing
Parameter Delay from address to WAIT input Symbol tDAWT Conditions VDD = +5.0 V 10% MIN. MAX. (2 + a) T - 40 (2 + a) T - 60 Delay from ASTB to WAIT input tDSTWT VDD = +5.0 V 10% 1.5T - 40 1.5T - 60 Hold time from ASTB to WAIT tHSTWTH VDD = +5.0 V 10% (0.5 + n) T + 5 (0.5 + n) T +10 Delay from ASTB to WAIT tDSTWTH VDD = +5.0 V 10% (1.5 + n) T - 40 (1.5 + n) T - 60 Delay from RD to WAIT input tDRWTL VDD = +5.0 V 10% T - 50 T - 70 Hold time from RD to WAIT tHRWT VDD = +5.0 V 10% nT + 5 nT + 10 Delay from RD to WAIT tDRWTH VDD = +5.0 V 10% (1 + n) T - 40 (1 + n) T - 60 Delay from WAIT to data input tDWTID VDD = +5.0 V 10% 0.5T - 5 0.5T - 10 Delay from WAIT to WR Delay from WAIT to RD Delay from WR to WAIT input tDWTW tDWTR tDWWTL VDD = +5.0 V 10% 0.5T 0.5T T - 50 T - 75 Hold time from WR to WAIT tHWWT VDD = +5.0 V 10% nT + 5 nT + 10 Delay from WR to WAIT tDWWTH VDD = +5.0 V 10% (1 + n) T - 40 (1 + n) T - 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks T: TCYK (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n 0) (4) Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tRC tWRFQL VDD = +5.0 V 10% Conditions MIN. 3T 1.5T - 25 1.5T - 30 Delay from ASTB to REFRQ Delay from RD to REFRQ Delay from WR to REFRQ Delay from REFRQ to ASTB REFRQ high-level pulse width tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH VDD = +5.0 V 10% 0.5T - 9 1.5T - 9 1.5T - 9 0.5T - 15 1.5T - 25 1.5T - 30 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark T: TCYK (system clock cycle time)
37
PD78P4038
SERIAL OPERATION (TA = -40 to +85C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V) (1) CSI
Parameter Serial clock cycle time (SCK0) Symbol tCYSK0 Input Conditions External clock When SCK0 and SO0 are CMOS I/O MIN. 10/fXX + 380 MAX. Unit ns
Output Serial clock low-level width (SCK0) tWSKL0 Input External clock When SCK0 and SO0 are CMOS I/O
T 5/fXX + 150
s
ns
Output Serial clock high-level width (SCK0) tWSKH0 Input External clock When SCK0 and SO0 are CMOS I/O
0.5T - 40 5/fXX + 150
s
ns
Output SI0 setup time (to SCK0) SI0 hold time (to SCK0) SO0 output delay time (to SCK0) tSSSK0 tHSSK0 tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) Open-drain output (2-wire serial I/O mode), RL = 1 k
0.5T - 40 40 5/fXX + 40 0 5/fXX + 150
s
ns ns ns
tDSBSK2
0
5/fXX + 400
ns
Remarks 1. The values in this table are those when CL is 100 pF. 2. T : Serial clock cycle set by software. The minimum value is 16/fXX. 3. fXX : Oscillator frequency
38
PD78P4038
(2) IOE1, IOE2
Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions VDD = +5.0 V 10% MIN. 250 500 Output Serial clock low-level width (SCK1, SCK2) tWSKL1 Input Internal, divided by 16 VDD = +5.0 V 10% T 85 210 Output Serial clock high-level width (SCK1, SCK2) tWSKH1 Input Internal, divided by 16 VDD = +5.0 V 10% 0.5T - 40 85 210 Output Setup time for SI1 and SI2 (to SCK1, SCK2) Hold time for SI1 and SI2 (to SCK1, SCK2) Output delay time for SO1 and SO2 (to SCK1, SCK2) Output hold time for SO1 and SO2 (to SCK1, SCK2) tSSSK1 Internal, divided by 16 0.5T - 40 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns
tHSSK1
40
ns
tDSOSK
0
50
ns
tHSOSK
When data is transferred
0.5tCYSK1 - 40
ns
Remarks 1. The values in this table are those when CL is 100 pF. 2. T: Serial clock cycle set by software. The minimum value is 16/fXX. (3) UART, UART2
Parameter ASCK clock input cycle time Symbol tCYASK Conditions VDD = +5.0 V 10% MIN. 125 250 ASCK clock low-level width tWASKL VDD = +5.0 V 10% 52.5 85 ASCK clock high-level width tWASKH VDD = +5.0 V 10% 52.5 85 MAX. Unit ns ns ns ns ns ns
39
PD78P4038
CLOCK OUTPUT OPERATION
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL VDD = +5.0 V 10% Conditions MIN. nT 0.5tCYCL - 10 0.5tCYCL - 20 CLKOUT high-level width tCLH VDD = +5.0 V 10% 0.5tCYCL - 10 0.5tCYCL - 20 CLKOUT rise time tCLR VDD = +5.0 V 10% 10 20 CLKOUT fall time tCLF VDD = +5.0 V 10% 10 20 MAX. Unit ns ns ns ns ns ns ns ns ns
Remarks n:
Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)
T: TCYK (system clock cycle time) OTHER OPERATIONS
Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width Low-level width for INTP1INTP3 and CI High-level width for INTP1INTP3 and CI Low-level width for INTP4 and INTP5 High-level width for INTP4 and INTP5 RESET low-level width RESET high-level width Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L Conditions MIN. 10 10 4tCYSMP 4tCYSMP 4tCYCPU MAX. Unit
s s
ns ns ns
tWIT1H
4tCYCPU
ns
tWIT2L
10
s s s s
tWIT2H
10
tWRSL tWRSH
10 10
Remarks tCYSMP: Sampling clock set by software tCYCPU: CPU operation clock set by software in the CPU
40
PD78P4038
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total errorNote VDD = AVDD = +5.0 V 10% VDD = AVDD = +2.7 to 4.5 V TA = -10 to +85C Linearity calibrationNote Quantization error Conversion time tCONV FR = 1 FR = 0 Sampling time tSAMP FR = 1 FR = 0 Analog input voltage Analog input impedance AVREF1 current AVDD supply current VIAN RAN AIREF1 AIDD1 AIDD2 fXX = 32 MHz, CS = 1 STOP mode, CS = 0 120 180 24 36 -0.3 1,000 0.5 2.0 1.0 1.5 5.0 20 AVREF1 + 0.3 Symbol Conditions MIN. 8 1.0 1.0 TYP. MAX. Unit bit % %
0.8 1/2
% LSB tCYK tCYK tCYK tCYK V M mA mA
A
Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value. Remark tCYK: System clock cycle time
41
PD78P4038
D/A CONVERTER CHARACTERISTICS (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Load conditions: VDD = AVDD = AVREF2 4 M, 30 pF = +2.7 to 5.5 V AVREF3 = 0 V VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD Load conditions: VDD = AVDD = AVREF2 2 M, 30 pF = +2.7 to 5.5 V AVREF3 = 0 V VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD Settling time Output resistance Analog reference voltage RO AVREF2 AVREF3 Resistance of AVREF2 and AVREF3 Reference power supply input current RAIREF DACS0, 1 = 55 H Load conditions: 2 M, 30 pF DACS0, 1 = 55 H 0.75VDD 0 4 8 10 VDD 0.25VDD Symbol Conditions MIN. 8 0.6 TYP. MAX. Unit bit %
0.8
%
0.8
%
1.0
%
10
s
k V V k
AIREF2 AIREF3
0 -5
5 0
mA mA
42
PD78P4038
DATA RETENTION CHARACTERISTICS (TA = -40 to +85C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = +2.7 to 5.5 V VDDDR = +2.5 V VDD rise time VDD fall time VDD hold time (to STOP mode setting) STOP clear signal input time Oscillation settling time tRVD tFVD tHVD 200 200 0 Conditions MIN. 2.5 30 10 TYP. MAX. 5.5 50 40 Unit V
A A s s
ms
tDREL tWAIT Crystal Ceramic resonator
0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR
ms ms ms V V
Input low voltage Input high voltage
VIL VIH
Specific pinsNote
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins AC TIMING TEST POINTS
VDD - 1 V 0.8VDD or 2.2 V Test points 0.45 V 0.8 V 0.8 V 0.8VDD or 2.2 V
43
PD78P4038
TIMING WAVEFORM (1) Read operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTID tDRST
tDAID AD0-AD7 tDSTR tDAR RD tWRL tFRA tDRID
tHRA
tHRID tDRA
(2) Write operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTOD tDWST
tHWA AD0-AD7 tDSTW tDAW WR tWWL tDWOD tSODW tHWOD
44
PD78P4038
HOLD TIMING
ADTB, A8-A19, AD0-AD7, RD, WR tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
(2) Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW
45
PD78P4038
REFRESH TIMING WAVEFORM (1) Random read/write cycle
tRC ASTB
WR tRC RD tRC tRC tRC
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
(3) Refresh after a read
ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL
(4) Refresh after a write
ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL
46
PD78P4038
SERIAL OPERATION (1) CSI
tWSKL0 SCK tCYSK0 SI tDSBSK1 SO Output data tSSSK0 tHSSK0 Input data tWSKH0
(2) IOE1, IOE2
tWSKL1 SCK tCYSK1 SI tDSOSK SO tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
(3) UART, UART2
tWASKH tWASKL
ASCK, ASCK2 tCYASK
47
PD78P4038
CLOCK OUTPUT TIMING
tCLH
tCLL
CLKOUT tCLR tCYCL tCLF
INTERRUPT INPUT TIMING
tWNIH tWNIL
NMI
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
CI, INTP1-INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
48
PD78P4038
EXTERNAL CLOCK TIMING
tWXH tWXH
X1 tXR tCYX tXF
DATA RETENTION CHARACTERISTICS
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Clearing by falling edge)
NMI (Clearing by rising edge)
49
PD78P4038
DC PROGRAMMING CHARACTERISTICS (TA = 25 5C, VSS = 0 V)
Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current VDDP supply voltage Symbol VIH SymbolNote 1 VIH Conditions MIN. 2.2 TYP. MAX. VDDP + 0.3 Unit V
VIL
VIL 0 VI VDDPNote 2 IOH = -400 A IOL = 2.1 mA 0 VO VDDP, OE = VIH Program memory write mode Program memory read mode
-0.3
+0.8 10
V
ILIP VOH
ILI VOH
A
V
2.4
VOL
VOL
0.45 10
V
ILO
-
A
VDDP
VCC
6.25 4.5 12.2
6.5 5.0 12.5 VPP = VDDP 10 10 5 1.0
6.75 5.5 12.8
V V V V
VPP supply voltage
VPP
VPP
Program memory write mode Program memory read mode
VDDP supply current
IDD
IDD
Program memory write mode Program memory read mode
40 40 50 100
mA mA mA
VPP supply current
IPP
IPP
Program memory write mode Program memory read mode
A
Notes 1. Symbols for the corresponding PD27C1001A 2. The VDDP represents the VDD pin as viewed in the programming mode.
50
PD78P4038
AC PROGRAMMING CHARACTERISTICS (TA = 25 5C, VSS = 0 V) PROM Write Mode (Page Program Mode)
Parameter Address setup time CE set time Input data setup time Address hold time SymbolNote 1 tAS tCES tDS tAH tAHL tAHV Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time Valid data delay time from OE OE pulse width in the data latch PGM setup time CE hold time OE hold time tDH tDF tVPS tVDSNote 2 tPW tOES tOE tLW tPGMS tCEH tOEH 1 2 2 2 Conditions MIN. 2 2 2 2 2 0 2 0 2 2 0.095 2 1 2 0.1 0.105 130 TYP. MAX. Unit
s s s s s s s
ns
s s
ms
s
ns
s s s s
Notes 1. These symbols (except tVDS) correspond to those of the corresponding PD27C1001A. 2. For PD27C1001A, read tVDS as tVCS.
51
PD78P4038
PROM Write Mode (Byte Program Mode)
Parameter Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time Valid data delay time from OE SymbolNote 1 tAS tCES tDS tAH tDH tDF tVPS tVDSNote 2 tPW tOES tOE Conditions MIN. 2 2 2 2 2 0 2 2 0.095 2 1 2 0.1 0.105 130 TYP. MAX. Unit
s s s s s
ns
s s
ms
s
ns
Notes 1. These symbols (except tVDS) correspond to those of the corresponding PD27C1001A. 2. For PD27C1001A, read tVDS as tVCS. PROM Read Mode
Parameter Data output time from address Delay from CE to data output Delay from OE to data output Data hold time to OE or CE Note 2 Data hold time to address SymbolNote 1 tACC tCE tOE tDF tOH Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL or OE = VIL CE = OE = VIL 0 0 1 1 MIN. TYP. MAX. 200 2 2 60 Unit ns
s s
ns ns
Notes 1. These symbols correspond to those of the corresponding PD27C1001A. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
52
PD78P4038
PROM Write Mode Timing (Page Program Mode)
Page data latch
Page program
Program verify
A2-A16 tAS A0, A1 tDS D0-D7 Hi-Z tVPS VPP VPP VDDP tVDS VDDP + 1.5 VDDP VDDP tCES VIH CE VIL VIH PGM VIL VIH OE VIL tLW tOES tPW tCEH tOEH Data input tDH Hi-Z tPGMS tOE Data output tDF Hi-Z tAHL tAHV
tAH
53
PD78P4038
PROM Write Mode Timing (Byte Program Mode)
Program Program verify
A0-A16 tAS D0-D7 Hi-Z tDS Data input tDH Hi-Z Data output tAH tDF Hi-Z
tDS VPP VPP VDDP
tVPS VDDP + 1.5 VDDP VDDP tVDS VIH CE VIL tCES VIH PGM VIL VIH OE VIL tOES tOE tPW
Cautions 1. VDDP must be applied before VPP, and must be cut after VPP. 2. VPP including overshoot must not exceed +13.5 V. 3. Plugging in or out the board with the VPP pin supplied with +12.5 V may adversely affect its reliability. PROM Read Mode Timing
A0-A16 Valid address
CE tCE OE tACC D0-D7
Note 1
tOE
Note 1
tDF tOH Data output
Note 2
Hi-Z
Hi-Z
Notes 1. For reading within tACC, the delay of the OE input from falling edge of CE must be within tACC-tOE. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
54
PD78P4038
12. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
CD
S Q R
80 1
21 20
F G H P I
M
J K M N L
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. S80GC-65-3B9-5
55
PD78P4038
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
C
D
S R Q
80 1
21 20
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. INCHES 0.6770.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. P80GC-65-8BT
56
PD78P4038
80 PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end
C
D
S Q R
80 1 20
21
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.000.20 12.000.20 12.000.20 14.000.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.000.20 0.500.20 0.145 +0.055 -0.045 0.10 1.05 0.100.05 55 1.27 MAX. INCHES 0.5510.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.5510.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0040.002 55 0.050 MAX. P80GK-50-BE9-5
57
PD78P4038
80 PIN CERAMIC WQFN
A B K
Q
T
U1
C
D
W
80 H IM J 1 R
U
Z X80KW-65A-1 NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K Q R S T U U1 W Z MILLIMETERS 14.0 0.2 13.6 13.6 14.0 0.2 1.84 3.6 MAX. 0.45 0.10 0.06 0.65 (T.P.) 1.0 0.15 C 0.3 0.825 0.825 R 2.0 9.0 2.1 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 C 0.012 0.032 0.032 R 0.079 0.354 0.083 0.030+0.006 -0.007 0.004
58
F
G
S
PD78P4038
13. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the PD78P4038. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 13-1. Soldering Conditions for Surface-Mount Devices (1/2) (1) PD78P4038GC-3B9: 80-pin plastic QFP (14 x 14 x 2.7 mm)
Soldering Process Infrared ray reflow Soldering Conditions Peak package's surface temperature: 235C Reflow time: 30 seconds or less (210C or more) Maximum allowable number of reflow processes: 3 Peak package's surface temperature: 215C Reflow time: 40 seconds or less (200C or more) Maximum allowable number of reflow processes: 3 Solder temperature: 260C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120C max. (measured on the package surface) Terminal temperature: 300C or less Heat time: 3 seconds or less (for one side of a device) Symbol IR35-00-3
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating method
-
Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). (2) PD78P4038GC-8BT: 80-pin plastic QFP (14 x 14 x 1.4 mm)
Soldering Process Infrared ray reflow Soldering Conditions Peak package's surface temperature: 235C Reflow time: 30 seconds or less (210C or more) Maximum allowable number of reflow processes: 2 Peak package's surface temperature: 215C Reflow time: 40 seconds or less (200C or more) Maximum allowable number of reflow processes: 2 Solder temperature: 260C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120C max. (measured on the package surface) Terminal temperature: 300C or less Heat time: 3 seconds or less (for one side of a device) Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
-
Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections).
59
PD78P4038
Table 13-1. Soldering Conditions for Surface-Mount Devices (2/2) (3) PD78P4038GK-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Soldering Process Infrared ray reflow Soldering Conditions Peak package's surface temperature: 235C Reflow time: 30 seconds or less (210C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125C afterward) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Peak package's surface temperature: 215C Reflow time: 40 seconds or less (200C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125C afterward) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Terminal temperature: 300C or less Heat time: 3 seconds or less (for one side of a device) Symbol IR35-107-2
VPS
VP15-107-2
Partial heating method
-
Note Maximum number of days during which the product can be stored at a temperature of 25C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections).
60
PD78P4038
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78P4038. See also (5). (1) Language processing software
RA78K4 CC78K4 DF784038 CC78K4-L Assembler package for all 78K/IV Series models C compiler package for all 78K/IV Series models Device file for PD784038 Subseries models C compiler library source file for all 78K/IV Series models
(2) PROM write tools
PG-1500 PA-78P4026GC PA-78P4038GK PA-78P4026KK PG-1500 controller PROM programmer Programmer adaptor, connects to PG-1500
Control program for PG-1500
(3) Debugging tools * When using the in-circuit emulator IE-78K4-NS
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator for all 78K/IV Series models Power supply unit for IE-78K4-NS Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine IE-70000-CD-IF PC card and interface cable when a PC-9800 series notebook is used as the host machine Interface adapter when the IBM PC/ATTM or compatible is used as the host machine Emulation board for evaluating PD784038 Subseries models Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types) Emulation probe for 80-pin plastic TQFP (GK-BE9 type) Socket for mounting on target system board made for 80-pin plastic QFP (GC-3B9 and GC-8BT types) Adapter for mounting on target system board made for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) Tool used to remove the PD78P4038KK-T from the EV-9200GC-80 Integrated debugger for IE-78K4-NS System simulator for all 78K/IV Series models Device file for PD784038 Subseries models
IE-70000-PC-IF-C
IE-784038-NS-EM1Note NP-80GC NP-80GKNote EV-9200GC-80
TGK-080SDW
EV-9900 ID78K4-NS SM78K4 DF784038
Note Under development
61
PD78P4038
* When using the in-circuit emulator IE-784000-R
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C IE-70000-98N-IF In-circuit emulator for all 78K/IV Series models Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine Interface adapter and cable when a PC-9800 series notebook is used as the host machine Interface adapter when the IBM PC/AT or compatible is used as the host machine Interface adapter and cable when the EWS is used as the host machine Emulation board for evaluating PD784038 Subseries models Emulation board for all 78K/IV Series models Conversion board for 80 pins to use the IE-784038-NS-EM1 on the IE-784000-R. The board is not needed when the conventional product IE-784038-R-EM1 is used. Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types) Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) for all PD784038 Subseries Socket for mounting on target system board made for 80-pin plastic QFP (GC-3B9 and GC-8BT types) TGK-080SDW Adapter for mounting on target system board made for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) Tool used to remove the PD78P4038KK-T from the EV-9200GC-80 Integrated debugger for IE-784000-R System simulator for all 78K/IV Series models Device file for PD784038 Subseries models
IE-70000-PC-IF-B IE-70000-PC-IF-C IE-78000-R-SV3 IE-784038-NS-EM1Note IE-784038-R-EM1 IE-78400-R-EM IE-78K4-R-EX2Note
EP-78230GC-R EP-78054GK-R
EV-9200GC-80
EV-9900 ID78K4 SM78K4 DF784038
Note Under development (4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV Series models OS for 78K/IV Series models
62
PD78P4038
(5) Notes when using development tools * The ID78K4-NS, ID78K4, and SM78K4 can be used in combination with the DF784038. * The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784038. * The NP-80GC is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales representative for purchasing. * The TGK-080SDW is a product from TOKYO ELETECH CORPORATION. Refer to: Daimaru Kogyo, Ltd. Tokyo Electronic Components Division (03-3820-7112) Osaka Electronic Components Division (06-244-6672) * The host machines and operating systems corresponding to each software are shown below.
Host Machine [OS] PC [WindowsTM] EWS
Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
PC-9800 Series HP9000 Series 700TM [HP-UXTM] IBM PC/AT and compatibles [Windows] SPARCstationTM [SunOSTM] NEWSTM (RISC) [NEWS-OSTM]
Note Note Note
- -
-
Note Note
Note Software under MS-DOS
63
PD78P4038
APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW)
(1) Conversion socket (EV-9200GC-80) package drawings and recommended pattern to mount the socket Connect the PD78P4038YKK-T (80-pin ceramic WQFN (14 x 14 mm)) and EP-78230GC-R to the circuit board in combination with the EV-9200GC-80. Figure B-1. Package Drawings of EV-9200GC-80 (Reference) (unit: mm)
Based on EV-9200GC-80 (1) Package drawing (in mm)
A E B F M N O
R D C S J
K
EV-9200GC-80
1
No.1 pin index
P
G H I EV-9200GC-80-G0E ITEM A B C D E F G H I J K L M O N P Q R S MILLIMETERS 18.0 14.4 14.4 18.0 4-C 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 INCHES 0.709 0.567 0.567 0.709 4-C 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
2.3
1.5
Q
0.091
0.059
64
L
PD78P4038
Figure B-2. Recommended Pattern to Mount EV-9200GC-80 on a Substrate (Reference) (unit: mm)
Based on EV-9200GC-80 (2) Pad drawing (in mm)
G
J K
E D F H
L
C B A EV-9200GC-80-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 19.7 15.0 INCHES 0.776 0.591
0.650.02 x 19=12.350.05 0.026+0.001 x 0.748=0.486 +0.003 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 0.591 0.776 0.236 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 2.3 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
I
65
PD78P4038
(2) Conversion adapter (TGK-080SDW) package drawings Connect the PD78P4038GK-BE9 (80-pin plastic TQFP (fine pitch: 12 x 12 mm)) to the circuit board in combination with the TGK-080SDW. Figure B-3. Package Drawings of TGK-080SDW (Reference) (unit: mm)
TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm)
A B C D R Q Q Q P S O O O N I JJJ K L L LM gv k j i h p l n m
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 18.0 11.77 0.5x19=9.5 0.5 0.5x19=9.5 11.77 18.0 0.5 1.58 1.2 7.64 1.2 1.58 1.58 1.2 7.64 1.2 1.58 INCHES 0.709 0.463 0.020x0.748=0.374 0.020 0.020x0.748=0.374 0.463 0.709 0.020 0.062 0.047 0.301 0.047 0.062 0.062 0.047 0.301 0.047 0.062 ITEM a b c d e f g h i j k l m n o p q r s t u v MILLIMETERS 0.5x19=9.50.10 0.25 INCHES 0.020x0.748=0.3740.004 0.010
T
U V
c
e b a
M2 screw
GFE
H
d
W X Y u r t s q
Z
f
Protrusion : 4 places
o
5.3 5.3 1.3 3.55 0.3
1.850.2 3.5 2.0 3.0 0.25 14.0 1.40.2 1.40.2 h=1.8 1.3 0~5 5.9 0.8 2.4 2.7 3.9
0.209 0.209 0.051 0.140 0.012
0.0730.008 0.138 0.079 0.118 0.010 0.551 0.0550.008 0.0550.008 h=0.071 0.051 0.000~0.197 0.232 0.031 0.094 0.106 0.154 TGK-080SDW-G1E
3.55
C 2.0 12.31 10.17 6.8 8.24 14.8 1.40.2
0.140
C 0.079 0.485 0.400 0.268 0.324 0.583 0.0550.008
note: Product by TOKYO ELETECH CORPORATION.
66
PD78P4038
APPENDIX C RELATED DOCUMENTS
Documents Related to Devices
Document Name Document No. English Japanese U11507J U10847J U10848J U11316J U11090J U10905J U10594J U10595J U10095J
PD784031 Data Sheet PD784035, 784036, 784037, 784038 Data Sheet PD78P4038 Data Sheet PD784038, 784038Y Sub-Series User's Manual, Hardware PD784038 Sub-Series Special Function Registers
78K/IV Series User's Manual, Instruction 78K/IV Series Instruction Summary Sheet 78K/IV Series Instruction Set 78K/IV Series Application Note, Software Basic
U11507E U10847E This manual U11316E - U10905E - - -
Documents Related to Development Tools (User's Manual)
Document Name Document No. English RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Series Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Base PG-1500 Controller IBM PC Series (PC DOSTM) Base IE-78K4-NS IE-784000-R IE-784038-NS-EM1 IE-784038-R-EM1 EP-78230 EP-78054GK-R SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference Reference U11334E U11162E U11743E U11572E U11571E U12322E U11940E EEU-1291 U10540E To be released soon EEU-1534 To be created U11383E EEU-1515 EEU-1468 U10093E U10092E Japanese U11334J U11162J U11743J U11572J U11571J U12322J U11940J EEU-704 EEU-5008 U13356J U12903J To be created U11383J EEU-985 EEU-932 U10093J U10092J
ID78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Base
U12796E U10440E U11960E
U12796J U10440J U11960J
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base Reference
Caution The above documents may be revised without notice. Use the latest versions when you design application systems.
67
PD78P4038
Documents Related to Software to Be Incorporated into the Product (User's Manual)
Document Name Document No. English 78K/IV Series Real-Time OS Basic Installation Debugger OS for 78K/IV Series MX78K4 Basic U10603E U10604E - - Japanese U10603J U10604J U10364J U11779J
Other Documents
Document Name Document No. English IC PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide for Products Related to Microcomputer: Other Companies C10943X C10535E C11531E C10983E C11892E - - C10535J C11531J C10983J C11892J C12769J U11416J Japanese
Caution The above documents may be revised without notice. Use the latest versions when you design application systems.
68
PD78P4038
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
69
PD78P4038
IEBus and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation.
70
PD78P4038
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J98. 2
71
PD78P4038
Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed The customer must judge the need for license : PD78P4038KK-T : PD78P4038GC-3B9, PD78P4038GC-xxx-3B9, PD78P4038GC-8BT PD78P4038GK-BE9, PD78P4038GK-xxx-BE9
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

▲Up To Search▲

Price & Availability of UPD78P4038

	To Download UPD78P4038 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .