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| CXA3275Q PLL/OSC/MIX IC for Digital Tuner Description The CXA3275Q is a monolithic tuner IC for single conversion system digital broadcast tuners. This IC integrates three sets of local oscillator and mixer circuits (VHF Low Band/ VHF High Band/UHF Band), an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. Features * Balanced oscillators with low-phase noise and excellent oscillation stability (UHF: 4 pins, VHF: 2 pins) * High linearity mixer and IF amplifier * IF output switchable between balanced and unbalanced * Low-phase noise PLL synthesizer (3-wire bus format) * Reference frequency programmable in 4 bits * On-chip high voltage drive transistor for charge pump * On-chip 4-output band switch (PNP transistor on/off) * 40-pin QFP package Applications Digital CATV tuners Structure Bipolar silicon monolithic IC 40 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25C) * Supply voltage Vcc, PLLVcc -0.3 to +6.0 V IFVcc -0.3 to +6.0 V * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD 1.58 W (when mounted on a printed circuit board) Operating Conditions * Supply voltage Vcc, PLLVcc IFVcc * Operating temperature Topr 4.5 to 5.5 4.5 to 5.5 -40 to +80 V V C This IC has pins whose electrostatic discharge strength is weak as a high-frequency process is used for this IC. Take care when handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E00461-PS CXA3275Q Block Diagram and Pin Configuration VHIN1 VHIN2 VLIN1 VLIN2 30 29 28 27 26 25 24 23 22 21 PLLVcc 31 VLMIX CP 32 VHMIX UMIX UIN1 BS4 BS3 BS2 BS1 NC 20 UIN2 19 Vcc VT 33 18 MIXOUT1 XI 34 17 MIXOUT2 XO 35 Ref OSC Charge Pump Band SW 16 GND PLLGND 36 Ref Div. LOCK 37 Bus Interface Lock Det Phase Det Program Div. 15 IFIN1 14 IFIN2 SDA 38 13 RFGND SCL 39 IF Amp CE 40 VLOSC VHOSC UOSC 12 UOSCB1 11 UOSCE1 1 IFOUT1 2 IFOUT2 3 IFVcc 4 IFGND 5 VLOSC2 6 VLOSC1 7 VHOSC2 8 VHOSC1 9 UOSCB2 10 UOSCE2 -2- CXA3275Q Pin Description and Equivalent Circuit Pin No. Symbol Pin voltage [V] 3 Equivalent circuit IFVcc Description IF outputs. IFOUT1 and IFOUT2 output a balanced signal. When taking a signal as an unbalanced output, connect the pin not used for output to IFVCC. At this time the output stage current is saved. IF amplifier power supply. IF amplifier GND. 1 IFOUT1 40k 2.5 2 IFOUT2 1 2 3 4 IFVcc IFGND -- -- 5 19 6 20k Vcc 5 VLOSC2 2.5 3k 3k 20k External resonance circuit connection for VL oscillator. 20k 20k 6 VLOSC1 2.5 7 19 8 20k Vcc 7 VHOSC2 2.5 3k 3k 20k External resonance circuit connection for VH oscillator. 20k 8 VHOSC1 2.5 20k 9 UHF: 2.2 UOSCB2 VL/VH: 2.3 UOSCE2 UOSCE1 UOSCB1 RFGND UHF: 1.5 VL/VH: - UHF: 1.5 VL/VH: - UHF: 2.2 VL/VH: 2.3 -- 9 19 3k 10 11 12 Vcc 10 11 12 13 3k External resonance circuit connection for UHF oscillator. Analog GND. -3- CXA3275Q Pin No. Symbol Pin voltage [V] 3 Equivalent circuit IFVcc Description 14 IFIN2 2.7 14 15 5k 5k IF inputs. 15 IFIN1 2.7 16 GND 0 18 17 20 20 GND 17 MIXOUT2 -- Mixer outputs. 18 MIXOUT1 -- 19 Vcc -- Band switch, mixer and local oscillator circuit power supply. Vcc 20 UIN2 VL/VH: 0 UHF: 1.9 19 UHF inputs. 21 UIN1 VL/VH: 0 UHF: 1.9 20 21 22 VHIN2 23 24 25 VHIN1 VLIN2 VLIN1 VH: 3 VL: 3.16 UHF: 3.24 VH: 3 VL: 3.16 UHF: 3.24 VH: 3.16 VL: 3 UHF: 3.24 VH: 3.16 VL: 3 UHF: 3.24 19 22 24 23 25 5k 5k Vcc VH and VL inputs. -4- CXA3275Q Pin No. Symbol Pin voltage [V] 19 Equivalent circuit Vcc 20k Description 26 BS1 ON: 4.9 OFF: 0 Pin 26: Band switch 1 output. Pin 29: Band switch 4 output. The pin corresponding to the band selected by the data goes High. 26 29 29 BS4 19 Vcc 20k 27 BS2 ON: 4.9 OFF: 0 27 28 70k 30k Pin 27: Band switch 2 output. Pin 28: Band switch 3 output. The pin corresponding to the band selected by the data goes High. 28 BS3 30 31 NC PLLVcc -- -- 31 PLLVcc NC. PLL VCC. 32 CP -- 32 33 50 Charge pump output. Connects the loop filter. 33 VT -- Transistor open collector output for varicap diode drive. Connects the loop filter. PLLVcc 31 34 XI 3.1 500 34 35 External reference clock input. Connects the crystal when used as a reference oscillator. 35 XO 3.0 Connects the crystal when used as a reference oscillator. 36 PLLGND -- PLL GND. -5- CXA3275Q Pin No. Symbol Pin voltage [V] 31 Equivalent circuit PLLVcc Description 5.0 (lock) 37 Lock detection. High when locked, Low when unlocked. 37 LOCK 0.2 (unlock) 31 5k 38 PLLVcc 38 SDA -- 20 Data input. 31 5k PLLVcc 39 SCL -- 39 Clock input. 31 150k PLLVcc 40 CE 1.25 (when open) 40 50k Enable pin. -6- CXA3275Q Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.) (Vcc = 5V, IFVcc = 5V, PLLVcc = 5V, Ta = 25C) Circuit Current Item Symbol Iccv1 Measurement conditions During VHF operation Unbalanced output Band switch output open During UHF operation Unbalanced output Band switch output open During VHF operation Balanced output Band switch output open During UHF operation Balanced output Band switch output open Min. 80 Typ. 113 Max. 145 Unit mA Iccu1 Circuit current Iccv2 85 120 151 mA 91 130 170 mA Iccu2 100 137 177 mA OSC/MIX/IF Amplifier Block Item Symbol CG1-1 CG1-2 Conversion gain 1 1 (Unbalanced) CG1-3 CG1-4 CG1-5 CG1-6 CG2-1 CG2-2 Conversion gain 2 1, 2 CG2-3 (Balanced) CG2-4 CG2-5 CG2-6 NF1 NF2 Noise figure 1, 3 (Unbalanced) NF3 NF4 NF5 NF6 Measurement conditions VL operation VL operation VH operation VH operation fRF = 50MHz, fIF = 39MHz fRF = 150MHz, fIF = 39MHz fRF = 150MHz, fIF = 39MHz fRF = 450MHz, fIF = 39MHz Min. 18.5 19 19 19 23.5 24.5 25.5 26 26 26 30.5 31.5 Typ. 21.5 22 22 22 26.5 27.5 28.5 29 29 29 33.5 34.5 15.5 15 15 15 10.5 10.5 Max. 25 25.5 25.5 25.5 30 31 32 32.5 32.5 32.5 37 38 18.5 18 18 18 13.5 13.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB UHF operation fRF = 450MHz, fIF = 39MHz UHF operation fRF = 850MHz, fIF = 39MHz VL operation VL operation VH operation VH operation fRF = 50MHz, fIF = 39MHz fRF = 150MHz, fIF = 39MHz fRF = 150MHz, fIF = 39MHz fRF = 450MHz, fIF = 39MHz UHF operation fRF = 450MHz, fIF = 39MHz UHF operation fRF = 850MHz, fIF = 39MHz VL operation VL operation VH operation VH operation fRF = 50MHz, fIF = 39MHz fRF = 150MHz, fIF = 39MHz fRF = 150MHz, fIF = 39MHz fRF = 450MHz, fIF = 39MHz UHF operation fRF = 450MHz, fIF = 39MHz UHF operation fRF = 850MHz, fIF = 39MHz -7- CXA3275Q OSC/MIX/IF Amplifier Block (cont.) Item Symbol CM1-1 CM1-2 1, 4 1% cross modulation 1 (Unbalanced) CM1-3 CM1-4 CM1-5 CM1-6 CM2-1 CM2-2 1, 5 1% cross modulation 2 (Unbalanced) CM2-3 CM2-4 CM2-5 CM2-6 Maximum output power Phase noise 1 6 Measurement conditions VL operation fD = 50MHz, fIF = 39MHz, fUD = 6MHz (80% AM) VL operation fD = 150MHz, fIF = 39MHz, fUD = 6MHz (80% AM) VH operation fD = 150MHz, fIF = 39MHz, fUD = 6MHz (80% AM) VH operation fD = 450MHz, fIF = 39MHz, fUD = 6MHz (80% AM) UHF operation fD = 450MHz, fIF = 39MHz, fUD = 6MHz (80% AM) UHF operation fD = 850MHz, fIF = 39MHz, fUD = 6MHz (80% AM) VL operation fD = 50MHz, fIF = 39MHz, fUD = 12MHz (40% AM) VL operation fD = 150MHz, fIF = 39MHz, fUD = 12MHz (40% AM) VH operation fD = 150MHz, fIF = 39MHz, fUD = 12MHz (40% AM) VH operation fD = 450MHz, fIF = 39MHz, fUD = 12MHz (40% AM) UHF operation fD = 450MHz, fIF = 39MHz, fUD = 12MHz (40% AM) UHF operation fD = 850MHz, fIF = 39MHz, fUD = 12MHz (40% AM) Min. 83.5 83.5 83 83 78 77 91.5 91.5 90 89 85 84 +10 Typ. 87.5 87.5 87 87 82 81 95.5 95.5 94 93 89 88 +13 73 Max. Unit dB dB dB dB dB dB dB dB dB dB dB dB dBm dBc/Hz Pomax 50 load, saturation output, fIF = 45MHz PN 1 1kHz offset Phase comparison frequency = 218.75kHz Charge pump current: 900A 10kHz offset Phase comparison frequency = 218.75kHz Charge pump current: 900A 50kHz offset Phase comparison frequency = 218.75kHz Charge pump current variable Phase noise 2 6 PN 2 90 dBc/Hz 6, 7 Oscillator phase noise C/N 60 70 dBc -8- CXA3275Q 1 Value measured with the untuned input. 2 Value compensated for the loss due to the external parts connected to Pins 1 and 2, and converted to the IC output pin amplitude. 3 Noise figure is the direct-reading value of NF meter in DSB. 4 SG1 Ypad fD -30dBm SG2 fD 6MHz AM80%, Audio 100kHz Input value (SG2, 50 termination) when S/I = 46dB with the spectrum analyzer DUT Spectrum analyzer 5 SG1 Ypad fD -30dBm SG2 fD 12MHz AM40%, Audio 100kHz Input value (SG2, 50 termination) when S/I = 46dB with the spectrum analyzer DUT Spectrum analyzer 6 Value when 14MHz (300mVp-p) is SG (Hewlett-Packard Japan, Ltd.: 8644A) input as the external REF CLOCK. 7 The spectrum analyzer is set for SPAN:100kHz, RBW:3kHz and VBW:100Hz. -9- CXA3275Q PLL Block Item Lock-up time 1 Lock-up time 2 Reference leak CL and DA input "H" level input voltage "L" level input voltage "H" level input current "L" level input current CE input "H" level input voltage "L" level input voltage "H" level input current "L" level input current CPO (charge pump) Output current 1 Output current 2 VT (VC voltage output) Maximum output voltage Minimum output voltage REFOSC Oscillation frequency range FXTOSC Drive frequency Drive level Band SW Output current Saturation voltage Leak current LOCK "H" output voltage "L" output voltage VLOCKH VLOCKH When locked When unlocked Vcc - 1 Vcc - 0.3 0 0.1 Vcc 0.5 V V IBS VSAT LeakBS When ON When ON Source current = 5mA 150 0.5 -5 300 3 mA mV A REFIN1 REFIN2 External reference clock: sine wave 3 3 250 4 14 350 5 20 500 MHz MHz mVp-p VTH VTL Sink current = 1mA 0.3 33 0.8 V V ICPO2 ICPO4 When 300A is selected When 900A is selected 210 600 300 900 420 1215 A A VIH VIL IIH IIL VIH = Vcc VIL = GND 3 GND 100 -35 Vcc 1 200 -100 V V A A VIH VIL IIH IIL VIH = Vcc VIL = GND 3 GND 0 -0.2 Vcc 1.5 -0.1 -4 V V A A Symbol LUT1 LUT2 REFL Measurement conditions fosc 89MHz fosc 479MHz fosc 479MHz fosc 889MHz Phase comparison frequency = 218.75kHz Min. Typ. 10 10 65 Max. Unit ms ms dBc When OFF IFVCC = 5.5V - 10 - CXA3275Q PLL Block (cont.) Item Bus timing (3-wire bus) Data setup time Data hold time Enable waiting time Enable setup time Enable hold time Symbol Measurement conditions Min. Typ. Max. Unit tSD tHD tWE tSE tHE 300 600 300 300 600 ns ns ns ns ns - 11 - CXA3275Q Electrical Characteristics Measurement Circuit Inductance Constants Wire diameter Number of windings Winding diameter L1 L2 L3 0.5 0.5 0.5 7.5T 1.5T 1.5T 3.2 3.2 3.4 VHF Low 100k 100k 100k 100k 1n VLIN1 VLIN2 BS4 BS3 BS2 BS1 1n VHIN1 1n VHIN2 1n UIN1 1n 4T UIN2 20 Vcc 19 MIXOUT1 18 MIXOUT2 17 GND 16 IFIN1 15 IFIN2 14 RFGND 13 UOSCB1 12 UOSCE1 11 39p 1n 1n 1.3k 39p 1n 4T 1n 5V UHF NC 10 1n 30V 5V 30k 1n PLLVcc 47n 5.1k CP VT XI XO PLLGND LOCK 56p 200 56p 200 1n 2k DA CL CE 31 32 33 34 35 36 37 38 39 40 30 29 28 27 26 25 24 VHF High 23 22 21 100n 20 200 100p 1 51 REF CLOCK 10n 10 6T 6T -com For IF balanced output 1 1n 180 4T 2 1n 180 1n 1 IFOUT1 2 IFOUT2 3 IFVcc 4 IFGND 5 VLOSC2 6 VLOSC1 7 VHOSC2 8 VHOSC1 9 UOSCB2 10 UOSCE2 8p 2.5p 4p 10k 8p 56p 3.3k 30 1n IF 5V 12p 12p 30 12p 20 12p 20 56p 0.5p (UK) 0.5p (UK) 4T IF 10k 1T363 220p L1 3k 1T363 100p L2 0.5p (UK) 1T363 L3 0.5p (UK) 1T363 10k 3k 3.3k 1: 14MHz, sine wave, 300mVp-p input (Hewlett-Packard Japan, Ltd.: 8644A) - 12 - CXA3275Q Description of Operation The CXA3275Q is a tuner IC which frequency converts 55 to 860MHz cable digital broadcasts to IF. In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillation frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VLIN, VHIN or UIN and the local oscillation signal. There are three sets of mixer circuits for VHF Low Band, VHF High Band and UHF Band. VHF Low and VHF High are common emitter type mixer input circuits, and UHF is a common base type mixer input circuit. 2. Local oscillation circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. There are three sets of oscillation circuits for VHF Low Band, VHF High Band and UHF Band. VHF Low and VHF High are 2-pin fully differential oscillation circuits and UHF is a 4-pin fully differential oscillation circuit. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. IF output is low impedance (emitter follower output), and can be selected from balanced and unbalanced output. When unbalanced output is selected, the output stage current can be saved by connecting the pin not used for output to IFVCC. 4. PLL circuit This PLL circuit controls the local oscillation frequency. It consists of a programmable divider, phase comparator, charge pump and reference oscillator. The control format supports the 3-wire bus format. 5. Band switch circuit The MT58A has four sets of built-in PNP transistors which can be controlled by the bus data. These outputs switch the on-chip mixer and oscillator circuits, and the relationship with the control data is as shown in the table below. Relationship between the Band Switch Data and Mixer/Oscillator Operation Band switch data BS1 BS2 1 0 0 BS3 0 1 0 BS4 Mixer circuit VHF Low VHF High O X X X O X UHF X X O Oscillation circuit VHF Low VHF High O X X X O X UHF X X O : Don't care O: Operating X: Not operating - 13 - CXA3275Q Description of PLL Block The CXA3275Q supports the 3-wire bus control format. Serial data is transferred using the DA pin (DATA), CL pin (CLOCK) and CE pin (ENABLE) inputs. Data is loaded to the shift register at the falling edge of the clock signal, and is latched at the falling edge of the enable signal. The clocks during the enable period are counted, and 28 bits of data as counted from the rising edge of the enable signal are loaded as valid data. The MT58A has the power-on reset function and the register data become all "0" after the power is turned on. The threshold value of the power-on reset is approximately 3.0V. The VCO lock frequency is obtained according to the following formula. fosc = fref x (16M + S) fosc: Local oscillator frequency fref: Phase comparison frequency M: Main divider frequency division ratio S: Swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. S < M 8191 0 S 15 The control format is as shown below. Serial data (total 28 bits): Band data (4 bits) + various settings (3 bits) + reference frequency data (4 bits) + frequency data (17 bits) Invalid data Band switch data Various data Frequency data Invalid data DATA BS4 BS3 BS2 BS1 0 CD CP R2 R1 R0 R3 M12 M11 S2 S1 S0 1 CLOCK 4 5 11 12 28 ENABLE Time Latch M0 to: S0 to: CD: CP: BS1 to BS4: R0 to R3: Main divider frequency division ratio setting Swallow counter frequency division ratio setting Charge pump OFF and varicap output OFF (when "1") Charge pump current switching (See the Charge Pump Current Table.) Band switch control (Output PNP transistor ON when "1". See the Band Switch Output Table.) Reference divider frequency division ratio setting. (See the Reference Divider Frequency Division Ratio Table.) - 14 - CXA3275Q Charge Pump Current Table Charge pump current 300A 900A CP 0 1 Reference Divider Frequency Division Ratio Table R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency division ratio 2 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 Band Switch Output Table Band switch data BS1 1 0 0 0 BS2 0 1 0 0 BS3 0 0 1 0 BS4 0 0 0 1 BS1 ON OFF OFF OFF Band switch pins BS2 OFF ON OFF OFF BS3 OFF OFF ON OFF BS4 OFF OFF OFF ON Operating mode (MIX/OSC) UHF VL VH UHF CXA3275Q 3-wire Bus Timing Chart tSD 3V 1.5V tHD DATA CLOCK 3V 1.5V ENABLE 3V 1.5V tWE tSE tHE: Enable hold time tWE: Enable waiting time tHE tSD: Data setup time tHD: Data hold time tSE: Enable setup time - 16 - CXA3275Q Characteristics Graphs Circuit current vs. Supply voltage (Unbalanced output) 150 140 130 Circuit current [mA] 120 110 100 90 80 70 60 50 4.4 4.6 4.8 5.0 5.2 5.4 5.6 UHF VHF Circuit current [mA] 170 160 150 140 130 120 110 100 90 80 70 4.4 Circuit current vs. Supply voltage (Balanced output) UHF VHF 4.6 4.8 5.0 5.2 5.4 5.6 Supply voltage [V] Supply voltage [V] Band SW output voltage vs. Output current 5.5 5.4 5.3 5.2 Output voltage [V] 5.1 5.0 4.9 4.8 4.7 4.6 4.5 0 2 4 6 8 10 12 14 16 Output current [mA] BS1 BS2 BS3 BS4 - 17 - CXA3275Q Conversion gain vs. Reception frequency (Untuned input) 35 CG - Conversion gain [dB] 30 25 VL 20 15 10 fIF = 39MHz 5 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] VH UHF 35 30 NF - Noise figure [dB] Noise figure vs. Reception frequency (Untuned input, in DSB) fIF = 39MHz 25 20 VL 15 10 5 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] VH UHF 1% adjacent cross modulation vs. Reception frequency (Untuned input) CM - 1% adjacent cross modulation [dB] 120 100 80 60 40 20 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] fIF = 39MHz (100kHz 80% AM) fD - 6MHz fD + 6MHz 1% adjacent cross modulation vs. Reception frequency (Untuned input) CM - 1% adjacent cross modulation [dB] 120 100 80 60 40 20 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] fIF = 39MHz (100kHz 40% AM) fD - 12MHz fD + 12MHz VL VH UHF VL VH UHF - 18 - CXA3275Q OSC phase noise vs. Reception frequency (Untuned input) 120 110 100 90 80 70 60 50 40 30 20 10 0 0 Oscillation frequency supply voltage fluctuation (PLL off) 600 400 OSC phase noise [dBc/Hz] VL VH UHF 200 +B drift [kHz] VL VH UHF 0 -200 -400 -600 -800 Supply voltage = 5V VCC - 10% VCC + 10% 0 200 400 600 800 1000 fIF = 39MHz 1kHz offset 10kHz offset 100kHz offset 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] Reception frequency [MHz] Input/output characteristics (Untuned input) 20 10 0 Output level [dBm] -10 fIF = 39MHz -20 fRF = 50MHz (VL) fRF = 440MHz (VH) fRF = 850MHz (UHF) -30 -40 -50 -60 -50 -40 -30 -20 -10 0 10 20 Input level [dBm] (SG setting value) - 19 - CXA3275Q VHF Low Input Impedance j50 j100 j25 0 50 55M 150M 24 25 1n S11 -j25 -j50 -j100 VHF High Input Impedance j50 j100 j25 0 50 150M 22 23 1n S11 450M -j25 -j50 -j100 - 20 - CXA3275Q UHF Input Impedance j50 j100 j25 800 700 600 900 500 400 0 50 20 21 1n S11 -j25 -j50 -j100 IF Output Impedance j50 j100 j25 50M 40M 20M 0 30M 50 1 2 3 1n S11 5V -j25 -j50 -j100 - 21 - CXA3275Q Package Outline Unit: mm 40PIN QFP (PLASTIC) 9.0 0.4 + 0.4 7.0 - 0.1 30 21 + 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 31 20 A 40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1 11 10 0.24 M 0 to 10 0.5 0.2 (8.0) PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707 NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). - 22 - Sony Corporation |
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