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CXG1015N
Power Amplifier/Antenna Switch for PHS
Description The CXG1015N is a power amplifier/antenna switch MMIC for PHS. This is designed using the Sony's GaAs J-FET process and operates at a single positive power supply. Features * Single positive power supply 3.0 V * Output power 20.2 dBm (Antenna switch transfer output pin power) * Low current consumption 160 mA (Output power of 20.2 dBm) * High power gain 39 dB Typ. (Output power of 20.2 dBm) * Low insertion loss 0.5 dB Typ. * Small mold package 20-pin SSOP (Pin interval of 0.5 mm pitch) Structure GaAs J-FET MMIC Applications * Power amplifiers for PHS * Antenna switches for PHS 20 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD 6 * Voltage between gate and source Vgs0 1.5 * Drain current IDD 550 * Power dissipation PD 3 * Channel temperature * Operating temperature * Storage temperature Tch Topr Tstg 150 -35 to +85 -65 to +150
V V mA W C C C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97749-TE
CXG1015N
Electrical Characteristics Power Amplifier + Antenna Switch Transfer Block VDD=3.0 V, VCTL=2.0 V, f=1.90 GHz Item Current consumption Gate voltage adjustment value Output power
(Power Amplifier + Antenna Switch Transfer Block)
(Ta=25 C) Min. 0 20.2 35.5 39 -59 42 -54 Typ. 160 0.25 Max. 0.7 Unit mA V dBm dB dBc
Symbol IDD VGG2 POUT GP ACPR600
Power gain Adjacent channel leak power ratio (600 kHz100 kHz)
Values where VGG1 and VGG2 are adjusted so that IDD becomes 160 mA when the power amplifier output pin and the antenna switch transfer input pin are connected on the Sony's recommended evaluation board and the output power on the antenna switch transfer output pin is 20.2 dBm.
Antenna Switch Receive Block VCTL(L)=0 V, VCTL(H)=3.0 V Item Insertion loss Isolation Control pin current Symbol IL ISO ICTL Min. 20 Typ. 0.5 24 40 Max. 0.8 100
(Ta=25 C) Unit dB dB A
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CXG1015N
Block Diagram
VDD1 VDD2 VDD3 RX VCTL2
PAIN
ANT
VGG1
VPCTL
VGG2 PAOUT TX VCTL1
Pin Configuration
1 PAIN GND VDD1 GND VDD2 GND VDD3 GND RX VCTL2 20 VGG1 VPCTL GND VGG2 GND PAOUT GND TX VCTL1 ANT
Antenna Switch Operation VCTL1=3 V VCTL2=0 V VCTL1=0 V VCTL2=3 V ANT-TX ANT-RX ANT-TX ANT-RX ON OFF OFF ON
Gate Bias Circuit of Power Amplifier Block
VGG2 Gate voltage adjustment pin 1k VGG1
Recommended Current Adjustment Method (1) VGG2/PIN separate adjustment (VGG2 adjustment 1) (PIN adjustment 1) When the RF input (PIN) off, the current consumption (IDD) is adjusted to 160 mA. Variation of IDD and POUT due to adjustment (2) Simple adjustment (IDD read) When the RF input (PIN) is off, the gate voltage (VGG2) is set to 0.4 V and IDD is read. The output power (POUT) is adjusted to 20.2 dBm. IDD=16020 mA POUT=20.2 dBm
(VGG2 adjustment 2) The current consumption (IDD) is finely adjusted to 160 mA. IDD=160 mA POUT=20.20.2 dBm
(PIN adjustment 2) The output power (POUT) is finely adjusted to 20.2 dBm. IDD=1605 mA POUT=20.2 dBm
(VGG2 setting) The formula where VGG2=f (IDD: VGG2=0.4 V) is used to set VGG2. e.g. VGG2=a-b x IDD
(PIN adjustment) The output power (POUT) is adjusted to 20.2 dBm. IDD=1605 mA POUT=20.2 dBm
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CXG1015N
Recommended Evaluation Circuit
PAIN
VGG2 R1=1k GND L1=1.8nH L2=2.2nH L3=18nH C1=1pF C2=30pF C3=100pF C4=1nF C5=10nF
VDD
L2 L3 C4 C4 C5 C2 L3 C3 C1 L2 C2 C2 C3 C3 C2 R1
C4
VPCTL
RX
L1
GND Via Hole VCTL2
VCTL1
ANT
Glass fabric-base epoxy board GND for the overall back side Dimension : 25 mm x 25 mm Thickness : 0.2 mm
Recommended Gate Bias Circuit and Circuit Characteristics
(V) 3.0V VGG2
100
6.8k RV1 Variable resistor RV RV2 10k (Max.) 180
VGG2
0.5
1k
0
5 RV1 (k)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXG1015N
Recommended External Circuit
2.2nH PAIN
1 2
1nF 18nH 1nF
20 100pF
(VGG1)
19
VPCTL
VDD1
3 4
18
1k
17
VGG2
1nF 18nH 30pF VDD2
5 6
16 1pF 2.2nH (PAOUT)
15
10nF 1.8nH VDD3
7 8
14 30pF 13 100pF VCTL1 30pF (TX)
30pF RX
9
10 100pF
12
VCTL2
11
ANT
Example of Representative Characteristics (Ta=25 C) Antenna Switch Receive Block
IL, Iso. vs. Freq. 0 IL -1 -10 0
IL-Insertion loss (dB)
-2
-20
-3
Iso.
-30
-4
-40
-5 0 1 2 Frequency (GHz) 3
-50
--5--
Iso.-Isolation (dB)
CXG1015N
Example of Representative Characteristics Power Amplifier + Antenna Switch Transfer Block
25
-40
ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset)
45 Gain 40
-40
20
-45
-45
15 POUT 10
-50
35
-50
-55
30
-55
5
-60
25
-60
0 ACPR -5 -45 -40 -35 -30 -25 -20 PIN-Input power (dBm) -15
-65
20 ACPR 15 0.0 0.5 1.0 1.5 2.0 2.5 VPCTL-Gain control voltage (V)
-65
-70 -10
-70 3.0
22 POUT
-50
ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset)
45
-50
POUT-Output power (dBm)
Gain-Power gain (dB)
21
-55
Gain 40 -55
20
-60
35
-60
19 ACPR 18 2.0 2.5 3.0 3.5 4.0 VDD-Supply voltage (V) 4.5
-65
ACPR 30 -65 110 120 130 140 150 160 170 180 190 200 210 220 230 IDD-Drain current (mA)
-70 5.0
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ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset)
POUT, ACPR vs. VDD VDD=var., VPCTL=2.0V, VGG=const., IDD=160mA (@POUT=20.2dBm), PIN=-19.2dBm
Gain, ACPR vs. IDD VDD=3.0V, VPCTL=2.0V, VGG=var., IDD=var., PIN=var., POUT=20.2dBm
ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset)
POUT, ACPR vs. PIN VDD=3.0V, VPCTL=2.0V, VGG=const., IDD=160mA (@POUT=20.2dBm), PIN=var.
Gain, ACPR vs.VPCTL VDD=3.0V, VPCTL=var., VGG=const., IDD=160mA (@VPCTL=2V), PIN=var., POUT=20.2dBm
POUT-Output power (dBm)
Gain-Power gain (dB)
CXG1015N
Package Outline
Unit : mm
20PIN SSOP(PLASTIC)
5.0 0.05
1.25MAX S 11
0.1
A 20
4.4 0.05
6.4 0.2
A
1
10 0.5 0.1 M S A 0.25 0.1 0.1
0.1
0.6 0.15
+ 0.07 0.2 - 0.03 (0.2)
0 to 10 DETAIL A
(0.5)
B
DETAIL B
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L03 SSOP020-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 0.1g
--7--
(0.15) + 0.05 0.15 - 0.01

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