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PRELIMINARY
K7A203600A
Document Title
64Kx36-Bit Synchronous Pipelined Burst SRAM
64Kx36 Synchronous SRAM
Revision History
Rev. No. 0.0 0.1 History Initial draft Change tOH Min value from 1.3 to 1.0 at tCYC 5.0 Change tHZC Min value from 1.3 to 1.0 at tCYC 5.0 Add tCYC 183MHz, 225MHz Change DC Characteristics. Icc value from 260mA to 280mA at -72 ISB1 value from 10mA to 20mA ISB2 value from 10mA to 20mA Final spec release. Add VDDQ Supply voltage( 2.5V ) Draft Date May. 19. 1998 July. 13. 1998 Remark Preliminary Preliminary
0.2
Aug. 31. 1998
Preliminary
1.0 2.0
Nov. 16. 1998 Dec. 02. 1998
Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
FEATURES
* * * * * * * * * * * * * * * * * Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD= 3.3V+0.3V/-0.165V Power Supply. VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. 5V Tolerant Inputs Except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. LBO Pin allows a choice of either a interleaved burst or a linear burst. Three Chip Enables for simple depth expansion with No Data Contention ; 2 cycle Enable, 1 cycle Disable. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. TTL-Level Three-State Output. 100-TQFP-1420A
64Kx36 Synchronous SRAM
64Kx36-Bit Synchronous Pipelined Burst SRAM
GENERAL DESCRIPTION
The K7A203600A is a 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 36bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A203600A is fabricated using SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -22 4.4 3.1 3.1 -20 5.0 3.1 3.1 -18 5.4 3.1 3.1 -16 6.0 3.5 3.5 -15 6.7 3.8 3.8 -14 7.2 4.0 4.0 Unit ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO CONTROL REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1 ADDRESS REGISTER A2~A15 A0~A1
64Kx36 MEMORY ARRAY
ADSP
A0~A15
CS1 CS2 CS2 GW BW WEa WEb WEc WEd OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd
DATA-IN REGISTER REGISTER
CONTROL
CONTROL LOGIC
OUTPUT REGISTER BUFFER
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
PIN CONFIGURATION(TOP VIEW)
ADSC ADSP WEd WEb WEa WEc ADV 83 CLK CS1 CS2 CS2 VDD GW VSS BW OE A6 A7 A8 82 A9 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
64Kx36 Synchronous SRAM
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
LBO
N.C.
N.C.
VSS
N.C.
N.C.
A15
PIN NAME
SYMBOL A0-A15 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 81,82,99,100 83 84 85 89 98 97 92 93,94,95,96 86 88 87 64 31 SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,43,50,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
Output Power Supply (2.5V or 3.3V) Output Ground
-3-
N.C.
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
December 1998 Rev 2.0
PRELIMINARY
K7A203600A
FUNCTION DESCRIPTION
The K7A203600A is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to control signals by disabling CS1. All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows; ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high). Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected.
64Kx36 Synchronous SRAM
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1
(Interleaved Burst) Case 4 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
BURST SEQUENCE TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 A1 1 0 0 1
(Linear Burst)
Case 4 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H L L L L L L L X H X H X H X H CS2 X L X L X H H H X X X X X X X X CS2 X X H X H L L L X X X X X X X X ADSP X L L X X L H H H X H X H X H X ADSC L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H WRITE X X X X X X L H H H L L H H L L CLK ADDRESS ACCESSED N/A N/A N/A N/A N/A External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address OPERATION Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle
64Kx36 Synchronous SRAM
Notes : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by . 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW H H H H H H L BW H L L L L L X WEa X H L H H L X WEb X H H L H L X WEc X H H H L L X WEd X H H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE BYTE c and d WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time.
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE OPERATION Write Cycle, All bytes Address=An-1, Data=Dn-1 Write Cycle, All bytes Address=An-1, Data=Dn-1 Write Cycle, All bytes Address=An-1, Data=Dn-1 Write Cycle, One byte Address=An-1, Data=Dn-1 Write Cycle, One byte Address=An-1, Data=Dn-1 WRITE All L PRESENT CYCLE OPERATION Initiate Read Cycle Address=An Data=Qn-1 for all bytes No new cycle Data=Qn-1 for all bytes No new cycle Data=High-Z Initiate Read Cycle Address=An Data=Qn-1 for one byte No new cycle Data=Qn-1 for one byte CS1 L WRITE H OE L Read Cycle Data=Qn No carryover from previous cycle No carryover from previous cycle Read Cycle Data=Qn No carryover from previous cycle NEXT CYCLE
64Kx36 Synchronous SRAM
All L All L
H H
H H
L H
One L
L
H
L
One L
H
H
L
Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Voltage on I/O Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias SYMBOL VDD VDDQ VIN VIO PD TSTG TOPR TBIAS RATING -0.3 to 4.6 VDD -0.3 to 6.0 -0.3 to VDDQ+0.5 1.2 -65 to 150 0 to 70 -10 to 85 UNIT V V V V W C C C
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0C TA70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 3.135 0 Typ. 3.3 3.3 0 MAX 3.6 3.6 0 UNIT V V V
OPERATING CONDITIONS at 2.5V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 2.375 0 Typ. 3.3 2.5 0 MAX 3.6 2.9 0 UNIT V V V
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
MIN -
MAX 5 7
UNIT pF pF
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
PARAMETER Input Leakage Current(except ZZ) Output Leakage Current SYMBOL IIL IOL
64Kx36 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70C, VDD=3.3V+0.3V/-0.165V)
TEST CONDITIONS VDD=Max ; VIN=VSS to VDD Output Disabled, VOUT=VSS to VDDQ -22 -20 Operating Current ICC Device Selected, IOUT=0mA, ZZVIL, All Inputs=VIL or VIH Cycle TimetCYC min -18 -16 -15 -14 -22 -20 ISB Standby Current Device deselected, IOUT = 0mA, ZZVIL, f = Max, All Inputs0.2V orVDD-0.2V -18 -16 -15 -14 ISB1 ISB2 Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O)
* VIL(Min)=-2.0(Pulse Width tCYC/2) ** VIH(Max)=4.6(Pulse Width tCYC/2) ** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
MIN -2 -2 2.4 2.0 -0.5* 2.0 -0.3* 1.7
MAX +2 +2 440 400 380 360 320 280 110 100 100 90 80 70 20 20 0.4 0.4 0.8 VDD+0.5** 0.7 VDD+0.5**
UNIT A A
mA
mA
Device deselected, IOUT = 0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f = Max, All InputsVIL orVIH IOL = 8.0mA IOH = -4.0mA IOL = 1.0mA IOH = -1.0mA
mA mA V V V V V V V V
VOL VOH VOL VOH VIL VIH VIL VIH
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70C) PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load VALUE 0 to 3V 0 to 2.5V 1ns 1ns 1.5V VDDQ/2 See Fig. 1
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
Output Load(A)
64Kx36 Synchronous SRAM
Output Load(B) (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Dout 353 / 1538 319 / 1667
Dout Z0=50
RL=50 30pF*
5pF*
* Capacitive Load consists of all components of the test environment. Fig. 1
* Including Scope and Jig Capacitance
AC TIMING CHARACTERISTICS(TA=0 to 70C, VDD=3.3V+0.3V/-0.165V)
-22 -20
Max Min Max Min
-18
Max Min
-16
Max Min
-15
Max Min
-14
Max Unit
PARAMETER
Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High (GW, BW, WEX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High (GW, BW, WEX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up
SYMBOL tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS
Min
4.4 0 1.0 0 1.0 2.0 2.0 1.4 1.4 1.4 1.4 1.4 1.4 0.5 0.5 0.5 0.5 0.5 0.5 2 2
3.1 3.1 3.1 3.1 -
5.0 0 1.0 0 1.0 2.0 2.0 1.4 1.4 1.4 1.4 1.4 1.4 0.5 0.5 0.5 0.5 0.5 0.5 2 2
3.1 3.1 3.1 3.1 -
5.4 0 1.0 0 1.0 2.0 2.0 1.4 1.4 1.4 1.4 1.4 1.4 0.5 0.5 0.5 0.5 0.5 0.5 2 2
3.1 3.1 3.1 3.1 -
6.0 0 1.5 0 1.5 2.0 2.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2
3.5 3.5 3.5 3.5 -
6.7 0 1.5 0 1.5 2.4 2.4 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2
3.8 3.8 3.8 3.8 -
7.2 0 1.5 0 1.5 2.8 2.8 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2
4.0 4.0 4.0 4.0 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
cycle cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
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December 1998 Rev 2.0
TIMING WAVEFORM OF READ CYCLE
tCH tCL
CLOCK
tSH tCYC
K7A203600A
tSS
ADSP
tSS tSH
ADSC
tAH A2 tWS tWH A3
BURST CONTINUED WITH NEW BASE ADDRESS
tAS
ADDRESS
A1
-9tCSH tADVH
(ADV INSERTS WAIT STATE)
WRITE
tCSS
CS
tADVS
ADV
OE
tOE tHZOE Q1-1 tLZOE tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4
Data Out
Dont Care Undefined
64Kx36 Synchronous SRAM
PRELIMINARY
December 1998 Rev 2.0
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
CLOCK
tSH tCYC
K7A203600A
tSS
ADSP
tSS tSH
ADSC
tAH A1 A2
(ADSC EXTENDED BURST)
tAS
ADDRESS
A3 tWS tWH
WRITE
tCSH
- 10 (ADV SUSPENDS BURST)
tCSS
CS
tADVS tADVH
ADV
OE
tDS D1-1 tHZOE Q0-4 D2-1 D2-2 D2-2 D2-3 D2-4 D3-1 D3-2 tDH D3-3 D3-4
Data In
Data Out
Q0-3
Dont Care Undefined
64Kx36 Synchronous SRAM
PRELIMINARY
December 1998 Rev 2.0
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH)
tCH tCL
CLOCK
tSS tSH tCYC
K7A203600A
ADSP
tAS tAH A2 A3 tWH A1
ADDRESS
tWS
WRITE
- 11 tADVS tADVH tDS D2-1 tOE tCD tLZC Q1-1 tHZOE tLZOE Q2-1 tDH
CS
ADV
OE
Data In
tHZC
tOH Q3-1 Q3-2 Q3-3 Q3-4
Data Out
Dont Care Undefined
64Kx36 Synchronous SRAM
PRELIMINARY
December 1998 Rev 2.0
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH)
tCH tCL
CLOCK
tCYC
K7A203600A
tSS
tSH
ADSC
tWS tWH A8 A9 A2 tWS tWH A3 A4 A5 A6 A7
ADDRESS
A1
WRITE
tCSS
tCSH
- 12 tOE tLZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 tHZOE
CS
ADV
OE
tCD Q7-1 tDH D7-1 Q8-1 tOH Q9-1
Data Out
Data In
Dont Care Undefined
64Kx36 Synchronous SRAM
PRELIMINARY
December 1998 Rev 2.0
TIMING WAVEFORM OF POWER DOWN CYCLE
tCH tCL
CLOCK
tCYC
K7A203600A
tSS
tSH
ADSP
ADSC
tAS
tAH A2 tWS tWH
ADDRESS
A1
WRITE
- 13 tOE tLZOE tHZC Q1-1 tPUS tPDS
ZZ Recovery Cycle ZZ Setup Cycle Sleep State
tCSS
tCSH
CS
ADV
OE
Data In
tHZOE
D2-1
D2-2
Data Out
Normal Operation Mode
ZZ
Dont Care Undefined
64Kx36 Synchronous SRAM
PRELIMINARY
December 1998 Rev 2.0
PRELIMINARY
K7A203600A
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 64Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic. Data Address A[0:16] A[16] A[0:15] I/O[0:71] A[16] A[0:15]
64Kx36 Synchronous SRAM
CLK
Address CS2 CS2
Data
Address CS2 CS2
Data
64-Bits Microprocessor
CLK Address CLK Cache Controller ADSC WEx
64Kx36 SPB SRAM (Bank 0)
CLK ADSC WEx
64Kx36 SPB SRAM (Bank 1)
OE CS1 ADV ADSP
OE CS1 ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS tSH
ADSP
tAS tAH A2 tWS tWH A1
ADDRESS [0:n] WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE
Data Out (Bank 0) Data Out (Bank 1)
tLZOE Q1-1 Q1-2 Q1-3
tHZC Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Dont Care
Undefined
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December 1998 Rev 2.0
PRELIMINARY
K7A203600A
PACKAGE DIMENSIONS
64Kx36 Synchronous SRAM
100-TQFP-1420A
22.00 0.30 20.00 0.20
Units:millimeters/inches
0~8
0.10 0.127 + 0.05 -
16.00 0.30 14.00 0.20 0.10 MAX
(0.83) 0.50 #1 0.65 0.30 0.10 0.10 MAX (0.58)
0.10
1.40 0.50 0.10
0.10
1.60 MAX
0.05 MIN
- 15 -
December 1998 Rev 2.0

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