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| UL (R) LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 LS7082 (631) 271-0400 FAX (631) 271-0405 October 2000 PIN ASSIGNMENT - TOP VIEW A3800 QUADRATURE CLOCK CONVERTER FEATURES: * x1, x2 and x4 mode selection * Up to 16 MHz output clock frequency * INDEX input and output * UP/DOWN indicator output * Programmable output clock pulse width * On-chip filtering of inputs for optical or magnetic encoder applications. * TTL and CMOS compatible I/Os * +4.5V to +10.0V operation (VDD-VSS) * LS7082 (DIP); LS7082-S (SOIC ) - See Figure 1 DESCRIPTION: The LS7082 is a monolithic CMOS silicon gate quadrature clock converter. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B Inputs of the LS7082, are converted to strings of Up Clocks and Down Clocks. Pulses derived from the Index Track of an encoder, when applied to the INDX input, produce absolute position reference pulses which are synchronized to the Up Clocks and Down Clocks. These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. INPUT/OUTPUT DESCRIPTION: VDD (Pin 1) Supply Voltage positive terminal. INDX (Pin 2) Encoder Index pulses are applied to this input. RBIAS (Pin 3) Input for external component connection. A resistor connected between this input and VSS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A,B pulse separation (TOW TPS). VSS (Pin 4) Supply Voltage negative terminal. A (Pin 5) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. x2 (Pin 8) A low level applied to this input selects x2 mode of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. B (Pin 9) Quadrature Clock Input B. This input has a filter circuit identical to input A. 7082-100600-1 V DD (+V) 1 LSI 14 INDX INDX 2 13 UPCK RBIAS V SS (-V) 3 12 DNCK LS7082 4 11 UP/DN A NC 5 10 x4/x1 B 6 9 8 FIGURE 1 NC 7 x2 TABLE 1. MODE SELECTION TRUTH TABLE x2 Input 0 1 1 x4/x1 Input Don't Care 0 1 MODE x2 x1 x4 x4/x1 (Pin 10) This input selects between x1 and x4 modes of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. UP/DN (Pin 11) The count direction at any instant is indicated at this output. An UP count direction is indicated by a high, and a DOWN count direction is indicated by a low (See Figure 2). DNCK (Pin 12) This DOWN Clock output consists of low-going pulses generated when A input lags the B input (See Figure 2). UPCK (Pin 13) This UP Clock output consists of low-going pulses generated when A input leads the B input (See Figure 2). INDX (Pin 14) This output consists of low-going pulses generated by clock transitions at the A input when INDX input is high and B input is low (See Figure 2). NOTE: All unused input pins must be tied to VDD or VSS. ABSOLUTE MAXIMUM RATINGS: PARAMETER SYMBOL DC Supply Voltage VDD - VSS Voltage at any input VIN Operating temperature TA Storage temperature TSTG DC ELECTRICAL CHARACTERISTICS: (All voltages referenced to VSS, TA = 0C to 70C.) PARAMETER Supply voltage Supply current SYMBOL VDD IDD VALUE 11.0 VSS -.3 to VDD +.3 0 to +70 -55 to +150 UNITS V V C C MIN 4.5 - MAX 10.0 6.0 UNITS V A CONDITION VDD = 10.0V, All input frequencies = 0 Hz RBIAS = 2M VDD = 4.5V VDD = 9V VDD = 10.0V VDD = 4.5V VDD = 9V VDD = 10.0V x4/x1, x2, INDX Logic Low A,B Logic Low VIL VIL 0.7VDD 3.1 5.0 5.6 0.3VDD 0.6 1.0 1.1 - V V V V V V V V x4/x1, x2, INDX Logic High A,B Logic High VIH VIH ALL OUTPUTS: Sink Current VOL = 0.4V IOL 1.75 5.0 5.7 1.0 2.5 3.0 - mA mA mA mA mA mA VDD = 4.5V VDD = 9V VDD = 10.0V VDD = 4.5V VDD = 9V VDD = 10.0V Source Current VOH = VDD - 0.5V TRANSIENT CHARACTERISTICS: (TA = 0C to 70C) PARAMETER A,B inputs: Validation Delay IOH SYMBOL TvD MIN TVD+TOW MAX 85 100 160 Infinite UNITS ns ns ns ns CONDITION VDD = 10.0V VDD = 9V VDD = 4.5V - A,B inputs: Pulse Width A to B or B to A Phase Delay TPW TPS TOW Infinite 1 2TPW ns - A,B frequency fA,B - Hz - Input to Output Delay TDS - 120 150 235 ns ns ns VDD = 10.0V VDD = 9V VDD = 4.5V Includes input validation delay See Fig. 4 & 5 Output Clock Pulse Width TOW 50 - ns 7082-100600-2 TPW A B TPS INDX UPCK (x1) DNCK (x1) UPCK (x2) DNCK (x2) UPCK (x4) DNCK (x4) INDX TDS UP/DN TDS Tow FIGURE 2. LS7082 INPUT/OUTPUT TIMING DIAGRAM RBIAS 3 CURRENT MIRROR 14 11 INDX UP/DN A 5 FILTER DUAL ONE-SHOT CLOCK AND DIRECTION DECODE 13 x2 CLOCK MUX 12 B 9 FILTER DUAL ONE-SHOT INDX 2 x4/x1 10 x2 VDD VSS 8 1 +V -V 4 FIGURE 3. 7082-100100-3 LS7082 BLOCK DIAGRAM 1500 VDD=5V 30 VDD=5V OUTPUT CLOCK PULSE WIDTH, Tow, ns 1250 1000 VDD=10.0V OUTPUT CLOCK PULSE WIDTH, Tow, s VDD=9V 25 20 VDD=9V 750 15 VDD=10.0V 500 10 250 5 100 200 300 400 500 2 4 6 8 10 12 Figure 4. Tow vs RBIAS, K Figure 5. Tow vs RBIAS, M +V 8 x2 A CLOCK B CLOCK INDEX 5 9 B 2 INDX INDX A 10 x4/x1 1 V DD UPCK 13 5 4 DNCK 14 RESET V SS RBIAS 3 V SS 4 8 16 V DD +V UPCK ENCODER L S 7 0 8 2 DNCK 12 14 40193 RB FIGURE 6. A TYPICAL APPLICATION IN x4 MODE The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7082-100100-4 |
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