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INTEGRATED CIRCUITS
74F225 16X5 asynchronous FIFO (3-State)
Product specification IC15 Data Handbook 1992 Jun 15
Philips Semiconductors
Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
FEATURES
* Independent synchronous inputs and outputs * Organized as 16 words of 5 bits * DC to 25MHz data rate * 3-State outputs * Cascadable in word-width and depth direction
DESCRIPTION
This 80-bit active element First-In-First-Out (FIFO) is a monolithic Schottky-clamped transistor-transistor logic (STTL) array organized as 16-words of 5-bits each. A memory system using the 'F225 can be easily expanded in multiples of 16-words of 5-bits as shown in Figure 1. The 3-State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The 'F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the 'F225 is provided by three outputs, Input
Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are non-inverting with respect to the data inputs and are disabled when the OE input is High. When OE is Low, the data outputs are enabled to function as totem-pole outputs. TYPICAL SUPPLY CURRENT ( TOTAL) 65mA
TYPE 74F225
TYPICAL fMAX 25MHz
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F225N N74F225D PKG DWG #
20-pin plastic DIP 20-pin plastic SOL
SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS CPA, CPB D0 - D4 OE UNCPIN MR IR UNCPOUT Q0 - Q4 DESCRIPTION Load clock A and load clock B inputs Data inputs Output enable input (active-Low) Unload clock input Master reset input (active-Low) Input ready output Unload clock output (active-Low) Data outputs 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 50/33 50/33 150/40 50/33 LOAD VALUE HIGH/LOW 20A/20A 20A/20A 20A/20A 20A/20A 20A/20A 1.0mA/20mA 1.0mA/20mA 3.0mA/24mA 1.0mA/20mA
OR Output ready output NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
RESET MODE
A High-to-Low transition on the Master Reset (MR) input invalidates all data stored in the FIFO by clearing the control logic and setting OR Low. This High-to-Low transition on the MR input does not effect the data outputs but since OR is driven Low, it signifies invalid data on the outputs.
READ MODE
The Output Ready (OR) output is High when valid data is present on the data outputs. Data in the array is shifted on the Low-to-High transition of the Unload Clock Input (UNCPIN). In order for Output Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be High.
WRITE MODE
Data may be written into the array on the Low-to-High transition of either load clock (CPA or CPB) input. When writing data into the FIFO, one of the load clock inputs must be held High while the other strobes data into the FIFO. This arrangement allows either load clock to function as an inhibit for the other. Input Ready (IR) monitors the status of the last word location and signifies when the FIFO is full. This output is High whenever the FIFO is available to accept new data. The unload clock output (UNCPOUT) also monitors the last word location. This output generates a Low-logic-level pulse (synchronized to the internal clock pulse) when the last word location is vacant
June 15, 1992
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853-1652 06992
Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
PIN CONFIGURATION
CPA IR 1 2 20 19 18 17 16 15 14 13 12 11 VCC CPB MR OR UNCPIN
IEC/IEEE SYMBOL
9 18 EN5 CT=0 CT<16 1 19 CT>0 & & 1 + G1 G2/Z3 2CT<16 4 5 FIFO 16 X 5 CTR 3 3
UNCPOUT 3 D0 D1 D2 D3 D4 OE 4 5 6 7 8 9
2 17 15 14 13 12 11
- Z4
Q0 Q1 Q2 Q3 Q4
16 4 1D 5 6 7 8
GND 10
SF00334
SF00336
LOGIC SYMBOL
4 5 67 8
D0 D1 D2 D3 D4 1 19 16 9 18 CPA CPB UNCPIN OE MR Q0 Q1 Q2 Q3 Q4 IR OR UNCPOUT 3
VCC = Pin 20 GND = Pin 10
15 14 13 12 11 2 17
SF00335
June 15, 1992
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Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
LOGIC DIAGRAM
Word 16 (last word) Word 15 Word 3-14 same as 2 or 16 Word 2 Word 1 (first word)
Detail A
4 D0 15 QO
5 D1 6 D2 7 D3 8 D4 Detail A Detail A Detail A Detail A
14 13 12 11 9
Q1 Q2 Q3 Q4
OE 1 19 CP D CLR 3 UNCPOUT IR MR 2 18 VCC = pin 20 GND = pin 10 16 UNCPIN
CPA CPB
Q
17 OR
SF00337
June 15, 1992
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Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Current applied to output in Low output state Tamb Tstg Operating free air temperature range Storage temperature range IR, OR, UNCPOUT Data outputs PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 48 0 to +70 -65 to +150 UNIT V V mA V mA mA
C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIN VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current IR, OR, UNCPOUT Data outputs IR, OR, UNCPOUT Data outputs Operating free air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 -3 20 24 +70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA mA mA UNIT
C
June 15, 1992
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Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER IR, OR, VOH High-level output voltage UNCPOUT Data outputs VOL VIK II IIH IIL IOZH IOZL IOS ICC Low-level output voltage TEST CONDITIONS1 MIN VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Offset-output current, High-level voltage applied Offset-output current, Low-level voltage applied Short-circuit output current3 Supply current (total) VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX -60 65 LIMITS TYP2 MAX V V V V 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -20 50 -50 -150 95 V V V 2.5 2.7 2.4 2.7 UNIT
10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC
A A
A
A A
mA mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of High-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
June 15, 1992
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Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tSK tPLH tPLH tPLH tPHL tw(L) tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency, Cascade mode Propagation delay UNCPIN to Qn Propagation delay UNCPIN to OR Output skew Qn to OR Propagation delay UNCPIN to IR Propagation delay CPA or CPB to OR Propagation delay CPA or CPB to UNCPOUT Pulse width, Low UNCPOUT Propagation delay CPA or CPB to IR Propagation delay MR to OR Propagation delay MR to IR Output enable time to High or Low level Output disable time from High or Low level Waveform 2 and 3 Waveform 2 Waveform 2 Waveform 4 Waveform 2 Waveform 4 Waveform 4 Waveform 4 Waveform 3 Waveform 3 Waveform 3 Waveform 5 Waveform 6 Waveform 5 Waveform 6 11.0 5.5 2.0 1.5 2.5 1.5 2.0 25 10.0 9.5 16.0 6.0 2.0 50 55 20.0 8.5 60 65 23.0 11.5 12.0 13.5 8.5 4.0 3.5 4.5 3.5 4.0 17.0 11.5 7.0 6.5 7.5 7.0 7.0 9.0 5.0 1.5 1.0 2.0 1.0 1.5 19.0 13.0 7.5 7.0 9.0 7.5 7.5 13.0 12.0 20.0 8.5 19.5 16.0 25.0 11.0 12.0 70 75 27.0 15.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% MIN 25 9.0 8.5 14.0 5.0 0.0 50 50 17.0 7.5 22.0 19.0 29.0 12.0 15.0 85 90 29.0 16.0 MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns UNIT CL = 50pF, RL = 500
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) trec tw(H) tw(L) tw(L) tw(L) Setup time, High or Low Dn to CPA or CPB Hold time, High or Low Dn to CPA or CPB Recovery time MR to CPA or CPB CPA or CPB pulse width, High or Low UNCPIN pulse width, High or Low MR pulse width, Low Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 1 0.0 0.0 14.0 12.5 0.0 6.5 3.0 24.0 3.5 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% MIN 0.0 0.0 16.5 14.0 0.0 8.5 3.5 28.0 4.0 4.5 MAX ns ns ns ns ns ns UNIT CL = 50pF, RL = 500
June 15, 1992
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Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
TYPICAL TIMING DIAGRAM
MR
CPA
CPB
Dn
Word 1
Word 2
Word 3 is Low
Word 16
UNCPIN
IR
UNCPOUT
OR
Qn Word 1 Clear Load words 3-15 Load word 1 Load word 2 Load word 16 Unload word 2 Unload word 3 Word 1 Word 2 Word 3 Unload words 4-15 Unload word 16 Word 16
SF00338
NOTE: Shaded areas Indicates irrelevant input conditions.
June 15, 1992
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Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
AC WAVEFORMS
tw(L) CP VM VM tw(H) th tsu Dn VM VM VM tsu tw(L) MR VM VM OR UNCPOUT VM VM CPA or CPB VM tPHL VM tPLH VM tSK tw(L) VM
1/fMAX
VM tPLH VM
SF00339
Waveform 1. MR and Clock Pulse Widths, Data Setup and Hold Times and MR to Clock Setup Time
Qn
VM
1/fMAX
tw(L) UNCPIN VM VM tw(H) tPLH Qn VM tPHL OR VM tPLH VM tPLH IR VM Qn VM VM tPHL VM OE
SF00342
Waveform 4. CPA or CPB to UNCPOUT and OR Delay, UNCPOUT Pulse Width and Qn to OR Skew
VM tPZH VM
VM tPHZ VOH -0.3V
0V
SF00343
SF00340
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 2. UNCPIN to Output Delays
VM tPZL Qn VM VOL +0.3V VM tPLZ
1/fMAX
CPA or CPB VM VM
OE
MR tPHL VM
VM tPLH VM tPHL
SF00344
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
IR
OR
VM
SF00341
Waveform 3. CPA or CPB to IR Delay and MR to IR and OR Delay NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance.
June 15, 1992
9
Philips Semiconductors
Product specification
16 x 5 asynchronous FIFO (3-State)
74F225
APPLICATION
Load clock NC CPA CPB UNCPOUT IR D0 D1 5-bit data input D2 D3 D4 MR OE Q0 Q1 Q2 Q3 Q4 UNCPIN NC OR CPA CPB UNCPOUT IR D0 D1 D2 D3 D4 MR OE Q0 Q1 Q2 Q3 Q4 UNCPIN NC OR CPA CPB UNCPOUT IR D0 D1 D2 D3 D4 MR OE Q0 Q1 Q2 Q3 Q4 5-bit data output UNCPIN Unload clock OR Output ready
Master reset Input ready MR CPA CPB NC UNCPOUT IR D0 D1 5-bit data input D2 D3 D4 Q0 Q1 Q2 Q3 Q4 UNCPIN NC OE OR CPA CPB UNCPOUT IR D0 D1 D2 D3 D4 Q0 Q1 Q2 Q3 Q4 UNCPIN NC MR OE OR CPA CPB UNCPOUT IR D0 D1 D2 D3 D4 Q0 Q1 Q2 Q3 Q4 UNCPIN MR OE OR
Output enable
5-bit data output
SF00345
Figure 1. Expanding the 74F225 FIFO (48 words of 10 bits)
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for Open Collector Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00128
June 15, 1992
10
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1992 Jun 15
11
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1992 Jun 15
12
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
NOTES
1992 Jun 15
13
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05099
Philips Semiconductors
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