View 74LV273_116897.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
74LV273 Octal D-type flip-flop with reset; positive-edge trigger
Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook 1998 May 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
FEATURES
* Wide operating voltage: 1.0 to 5.5V * Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, * Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, * Ideal buffer for MOS microprocessor or memory * Common clock and master reset * Output capability: standard * ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn; MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The 74LV273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.
CONDITIONS CL = 15pF VCC = 3.3V
TYPICAL 12 13 110 3.5
UNIT ns MHz pF pF
Notes 1 and 2
20
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD VCC2 x fi )S (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic DIL 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV273 N 74LV273 D 74LV273 DB 74LV273 PW NORTH AMERICA 74LV273 N 74LV273 D 74LV273 DB 74LV273PW DH PKG. DWG. # SOT146-1 SOT163-1 SOT339-1 SOT360-1
1998 May 29
2
853-1965 19466
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
PIN CONFIGURATION
LOGIC SYMBOL
11
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
CP 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
GND 10
1
SV00366
SV00367
PIN DESCRIPTION
PIN NUMBER 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL MR Q0 to Q7 D0 to D7 GND CP VCC FUNCTION Master reset input (active-LOW) Flip-flop outputs Data inputs Ground (0V) Clock input (LOW-to-HIGH, edgetriggered) Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
11 1
C1 R
3 4 7 8 13 14 17 18
1D
2 5 6 9 12 15 16 19
SV00368
1998 May 29
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
FUNCTIONAL DIAGRAM
FUNCTION TABLE
INPUTS OPERATING MODES MR L H H CP X Dn X h l OUTPUTS Q0 to Q7 L H L
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
Reset (clear) Load (`1') Load (`0') H h L l X
FF0 to FF7
= HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH clock transition = Don't care
1 11
MR CP
SV00369
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 -40 -40 - - - - - - - TYP. 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
ns/V
NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 May 29
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK IOK IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with -standard outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 50 -65 to +150 750 500 400 UNIT V mA mA mA mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5V VCC = 1.2V VIL LOW level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5 VCC = 1.2V; VI = VIH or VIL; -IO = 100A HIGH level output voltage all outputs out uts voltage; VOH HIGH level output voltage; g STANDARD outputs VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VCC = 4.5V;VI = VIH or VIL; -IO = 100A VCC = 3.0V;VI = VIH or VIL; -IO = 6mA VCC = 4.5V;VI = VIH or VIL; -IO = 12mA VCC = 1.2V; VI = VIH or VIL; IO = 100A VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V;VI = VIH or VIL; IO = 100A VCC = 4.5V;VI = VIH or VIL; IO = 100A LOW level output voltage; g STANDARD outputs VCC = 3.0V;VI = VIH or VIL; IO = 6mA VCC = 4.5V;VI = VIH or VIL; IO = 12mA 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 0.2 0.2 0.2 0.2 0.50 V 0.65 V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC V V MAX UNIT
LOW level output voltage out uts voltage; all outputs VOL
1998 May 29
5
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
DC CHARACTERISTICS FOR THE LV FAMILY (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V) SYMBOL II ICC ICC PARAMETER Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input TEST CONDITIONS VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V LIMITS -40C to +85C 1.0 20.0 500 -40C to +125C 1.0 160 850 UNIT A A A
NOTE: 1. All typical values are measured at Tamb = 25C.
AC CHARACTERISTICS
GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay CP to Qn Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL Propagation delay MR to Qn Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Clock pulse width HIGH or LOW Figure 1 2.7 3.0 to 3.6 2.0 tW Master reset pulse width LOW Figure 2 2.7 3.0 to 3.6 1.2 trem Removal time MR to CP Figure 2 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time Dn to CP Figure 3 2.0 2.7 3.0 to 3.6 1.2 th Hold time Dn to CP Figure 3 2.0 2.7 3.0 to 3.6 2.0 fmax Maximum clock pulse frequency ulse Figure 1 2.7 3.0 to 3.6 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. MIN - - - - - - - - - - 34 25 20 34 25 20 - 5 5 5 - 22 16 13 - 5 5 5 14 19 24 LIMITS -40 to +85 C TYP1 75 26 19 142 - 80 27 20 152 - 9 6 52 10 8 62 -10 -4 -3 -22 20 7 5 42 -10 -4 -3 -22 40 75 1002 MAX - 32 24 19 16 - 44 33 26 22 - - - - - - - - - - - - - - - - - - - - - LIMITS -40 to +125 C MIN - - - - - - - - - - 41 30 24 41 30 24 - 5 5 5 - 26 19 15 - 5 5 5 12 16 20 MAX - 41 30 24 20 - 56 41 33 28 - - - - - - - - - - - - - - - - - - - - - MHz ns ns ns ns ns ns ns UNIT
1998 May 29
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load.
VI CP INPUT GND
t su t su
VM
1/fMAX VI CP INPUT GND tw tPHL VOH Qn OUTPUT VOL VM tPLH VM
VI
Dn INPUT GND VOH
Qn OUTPUT VOL
Figure 3.
SV00370
Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT
Vcc
VI MR INPUT GND VI CP INPUT GND VOH Qn OUTPUT VOL tPHL VM tw trem VM VM VM
PULSE GENERATOR RT
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST tPLH/tPHL
SV00372
Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagations delay and the master reset to clock (CP) removal time
Figure 4.
1998 May 29
7
IIIIIIII IIII IIIIIIII IIII IIIIIIII IIII
VM VM
th
th
SV00371
Data set-up and hold times for the data input (Dn)
Vl D.U.T.
VO
50pF CL
RL= 1k
Test Circuit for Outputs
VCC < 2.7V 2.7-3.6V 4.5 V
VI VCC 2.7V VCC
SV00902
Load circuitry for switching times
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1998 May 29
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 May 29
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1998 May 29
10
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1998 May 29
11
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger
74LV273
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04443
Philips Semiconductors
1997 Apr 07 12

▲Up To Search▲

Price & Availability of 74LV273

	To Download 74LV273 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .