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CDP1881C, CDP1882, CDP1882C
March 1997
CMOS 6-Bit Latch and Decoder Memory Interfaces
Description
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit memory latch and decoder circuits intended for use in CDP1800 series microprocessor systems. They can interface directly with the multiplexed address bus of this system at maximum clock frequency, and up to four 4K x 8-bit memories to provide a 16K byte memory system. With four 2K x 8-bit memories an 8K byte system can be decoded. The devices are also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general purpose memorysystem applications. The CDP1881C, CDP1882 and CDP1882C are intended for use with 2K or 4K byte RAMs and are identical except that in the CDP1882 MWR and MRD are excluded. The CDP1882 is functionally identical to the CDP1882C. It differs in that the CDP1882 has recommended operating voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V. The CDP1881C, CDP1882 and CDP1882C are supplied in 20 lead and 18 lead packages, respectively. The CDP1881C is supplied only in a dual-in-line plastic package (E suffix). The CDP1882 is supplied in dual-in-line, hermetic side-brazed ceramic (D suffix) and in plastic (E suffix) packages.
Features
* Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed * Decodes Up to 16K Bytes of Memory * Interfaces Directly with CDP1800-Series Microprocessors at Maximum Clock Frequency * Can Replace CDP1866 and CDP1867 (Upward Speed and Function Capability)
Ordering Information
TEMP. RANGE (oC) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PKG. NO. E20.3 E18.3 E18.3 D18.3
PACKAGE PDIP PDIP PDIP Burn-In SBDIP
5V CDP1881CE CDP1882CE CDP1882CEX -
10V CDP1882D
Pinouts
CDP1881C (PDIP) TOP VIEW CDP1882, CDP1882C (PDIP, CERDIP) TOP VIEW
CLOCK MA5 MA4 MA3 MA2 MA1 MA0 MRD MWR VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD A8 A9 A10 A11 CS0 CS1 CS2 CS3 CE
CLOCK MA5 MA4 MA3 MA2 MA1 MA0 CE VSS
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDD A8 A9 A10 A11 CS0 CS1 CS2 CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1367.2
4-1
CDP1881C, CDP1882, CDP1882C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1881C and CDP1882C. . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) 18 Lead PDIP . . . . . . . . . . . . . . . . . . . 85 N/A 20 Lead PDIP . . . . . . . . . . . . . . . . . . . 80 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 85 22 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CDP1882 CDP1881C, CDP1882C MAX 10.5 VDD MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER DC Operating Voltage Range Input Voltage Range
MIN 4 VSS
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, Except as Noted: CONDITIONS CDP1882 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 (NOTE 1) TYP 1 10 3.2 6.4 -2.3 -4.6 0 0 5 10 CDP1881C, CDP1882C (NOTE 1) TYP 5 3.2 -2.3 0 5 -
PARAMETER Quiescent Device Current
SYMBOL IDD
VO (V) -
VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 -
MIN 1.6 3.2 -1.15 -2.3 4.9 9.9 3.5 7
MAX 10 100 0.1 0.1 1.5 3 -
MIN 1.6 -1.15 4.9 3.5 -
MAX 50 0.1 1.5 -
UNITS A A mA mA mA mA V V V V V V V V
Output Low Drive (Sink) Current
IOL
0.4 0.5
Output High Drive (Source) Current
IOH
4.6 9.5
Output Voltage Low-Level (Note 2)
VOL
-
Output Voltage High-Level (Note 2)
VOH
-
Input Low Voltage
VIL
0.5, 4.5 1, 9
Input High Voltage
VIH
0.5, 9.5 1, 9
4-2
CDP1881C, CDP1882, CDP1882C
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, Except as Noted: (Continued) CONDITIONS VO (V) Any Input VIN (V) 0, 5 0, 10 Operating Current (Note 2) IDD1 0, 5 0, 10 Input Capacitance Output Capacitance Minimum Data Retention Voltage Data Retention Current NOTES: 1. Typical values are for TA = +25oC. 2. IOL = IOH = 1A. 3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuits (equivalent to typical CDP1800 system at 3.2MHz, 5V; and 6.4MHz, 10V). CIN COUT VDR 0, 5 0, 10 VDD = VDR VDD (V) 5 10 5 10 CDP1882 (NOTE 1) TYP 5 10 2 CDP1881C, CDP1882C (NOTE 1) TYP 5 10 2
PARAMETER Input Leakage Current
SYMBOL IIN
MIN -
MAX 1 2 2 4 7.5 15 2.4
MIN -
MAX 1 2 7.5 15 2.4
UNITS A A mA mA pF pF V
IDR
VDD = 2.4V
-
0.01
1
-
0.5
5
A
MA0
7
DQ C
19 A8
MA0
7
DQ C
17 A8
MA1
6
DQ C
18 A9
MA1
6
DQ C
16 A9
MA2
5
DQ C
17 A10
MA2
5
DQ C
15 A10
MA3
4
DQ C
16 A11
MA3
4
DQ C
14 A11
MA4
3
DQ CQ
15 CS0
MA4
3
DQ CQ
13 CS0
14 CS1 MA5 2 DQ CQ 13 CS2 CLOCK 1 12 CS3 MRD 8 CLOCK 1 MA5 2 DQ CQ
12 CS1
11 CS2
10 CS3
MWR
9
VDD = 20 VSS = 10
CE
8
VDD = 18 VSS = 9
CE 11
FIGURE 1. FUNCTIONAL DIAGRAM FOR THE CDP1881C
FIGURE 2. FUNCTIONAL DIAGRAM FOR THE CDP1882, CDP1882C
4-3
CDP1881C, CDP1882, CDP1882C
TRUTH TABLE INPUTS (NOTE 1) MWR 1 X 0 0 0 0 0 X X X X X NOTE: 1. CDP1881C Only (NOTE 1) MRD 1 X X X X X X 0 0 0 0 0 CE X 1 0 0 0 0 0 0 0 0 0 0 CLK X X 1 1 1 1 0 1 1 1 1 0 MA4 X X 0 1 0 1 X 0 1 0 1 X MA5 X X 0 0 1 1 X 0 0 1 1 X 0 1 1 1 CS0 1 1 0 1 1 1 OUTPUTS CS1 1 1 1 0 1 1 CS2 1 1 1 1 0 1 CS3 1 1 1 1 1 0
Previous State 1 0 1 1 1 1 0 1 1 1 1 0
Previous State
INPUTS CE X X X CLK 1 1 0 MA0, MA1, MA2, MA3 1 0 X
OUTPUTS A8, A9, A10, A11 1 0 Previous State
Logic 1 = High, Logic 0 = Low, X = Don't Care
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, (See Figure 1) CDP1882 VDD (V) (NOTE 1) TYP 10 8 8 8 50 25 (NOTE 2) MAX 35 25 25 25 75 40 CDP1881C, CDP1882C (NOTE 1) TYP 10 8 50 (NOTE 2) MAX 35 25 75 -
PARAMETER Minimum Setup Time Memory Address to CLOCK Minimum Hold Time Memory Address After CLOCK Minimum CLOCK Pulse Width tCLCL tCLMA tMACL
MIN -
MIN -
UNITS ns ns ns ns ns ns
5 10 5 10 5 10
4-4
CDP1881C, CDP1882, CDP1882C
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, (See Figure 1) (Continued) CDP1882 VDD (V) (NOTE 1) TYP (NOTE 2) MAX CDP1881C, CDP1882C (NOTE 1) TYP (NOTE 2) MAX
PARAMETER PROPAGATION DELAY TIMES Chip Enable to Chip Select tCECS
MIN
MIN
UNITS
5 10
-
75 45 75 40 100 65 100 65 100 75 80 40
150 100 150 100 175 125 175 125 175 125 125 60
-
75 75 100 100 100 80 -
150 150 175 175 175 125 -
ns ns ns ns ns ns ns ns ns ns ns ns
MRD or MRW to Chip Select (Note 3)
tMCS
5 10
CLOCK to Chip Select
tCLCS
5 10
CLOCK to Address
tCLA
5 10
Memory Address to Chip Select
tMACS
5 10
Memory Address to Address
tMAA
5 10
NOTES: 1. Typical values are for TA = 25oC. 2. Maximum limits of minimum characteristics are the values above which all devices function. 3. For CDP1881C type only.
CE tCECS CS0, CS1, CS2, CS3 (A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY MRD OR MWR tMCS CS0, CS1, CS2, CS3 (B) MRD OR MWR TO CHIP SELECT PROPAGATION DELAY (CDP1881C ONLY) MA0 - MA5 tMACL CLOCK tCLCL CS0, CS1, CS2, CS3 tCLA A8 - A11 (C) MEMORY ADDRESS SETUP AND HOLD TIME tMAA tMAA tCLCS tMACS tMACS tCLMA tMCS VALID CHIP ENABLE tCECS
FIGURE 3. TIMING WAVEFORMS
4-5
CDP1881C, CDP1882, CDP1882C Signal Descriptions/Pin Functions
CLOCK: Latch-Input Control - a high at the clock input will allow data to pass through the latch to the output pin. Data is latched on the high to low transition of the clock input. This input is connected to TPA in CDP1800-series systems. MA0 - MA3: Address inputs to the high-byte address latches. MA4 - MA5: High byte address inputs decoded to produce chip selects CS0 - CS3. MRD, MWR: MEMORY READ (MRD) and MEMORY WRITE (MWR) signal inputs on the CDP1881C. A low at either input, when the CE pin is low, will enable the decoder chip select outputs (CS0 - CS3). CE: CHIP ENABLE input - a low at the CE input of CDP1882, CDP1882C will enable the chip select decoder. A low at the CE input of CDP1881C, coincident with a low at either MRD or MRW pin, will enable the chip select decoder. A high on this pin forces CS0, CS1, CS2, and CS3 to a high (false) state. A8 - A11: Latched high-byte address outputs. CS0 - CS3: One of four latched and decoded Chip Select outputs. VDD, VSS: Power and ground pins, respectively.
Application Information
The CDP1881C, CDP1882, CDP1882C can interface directly with the multiplexed address bus of the CDP1800series microprocessor family at maximum clock frequency. A single CDP1881C or CDP1882 is capable of decoding up to 16K-bytes of memory. The CDP1881C is provided with MRD and MWR inputs for controlling bus contention, and is especially useful for interfacing with RAMs that do not have an output enable function (OE). Figure 4 shows the CDP1881C in a minimum system configuration which includes the CDP1833 ROM (1K x 8) and two 2K x 8 RAMS. The CDP1881C in this example performs the following functions: 1) Latch and decode high-order address bits for use as chip selects. 2) Gate chip selects with MRD and MWR to prevent bus contention with the CPU. 3) Latch high-order address bits A8 to A11. A system using the CDP1882 is shown in Figure 5. The CDP1882 performs the memory address latch and decoder functions. Note that the RAM has an output enable (OE) pin which eliminates the need for MRD and MWR inputs on the latch/decoder. Instead, the MRD line is connected directly to the RAM output enable (OE) pin. In Figure 6 the CDP1882 is used to decode a 16K-byte ROM system consisting of four CDM5332s.
ADDRESS BUS
A0 - A7 WAIT CLR TPA CDP1800 SERIES CPU TPA CDP1883 1K x 8 ROM
MA0 - MA5 CLK CDP1881C LATCH/ DECODER A11 A8 - A10
A0 - A7 (2) 2K x 8 RAMS
CEA (NOTE 1) CEB (NOTE 1)
CS0 CS1 CEO MRD MWR MRD CE MRD MWR CS2 CS3 R/W CS
DATA BUS NOTE: CEA = CE RAM NUMBER 1 CEB = CE RAM NUMBER 2
FIGURE 4. MINIMUM 1800-SERIES USING THE CDP1881C
4-6
CDP1881C, CDP1882, CDP1882C
CDP1882 LATCH/ DECODER CS3 CLK CE CS2 CS1 TO OTHER CHIP SELECTS
CS0 MA0 - MA5 A8 - A11
WAIT ADDRESS BUS CLR
TPA CDP1800 SERIES CPU ADDRESS BUS
A8 - A11 CS2 A0 - A7 CDM5332 4K x 8 ROM CSI/OE
A8 - A10 CE A0 - A7 CDM6116A 2K x 8 RAM OE WE
MRD MWR
DATA BUS
FIGURE 5. CDP1800-SERIES SYSTEM USING THE CDP1882
CDP1882 LATCH/ DECODER CS3 CLK CE CS2 CS1
CS0 MA0 - MA5 A8 - A11
WAIT CLR ADDRESS BUS
TPA
A8 - A11 CS2 ADDRESS BUS A0 - A7 CDM5332 4K x 8 ROM CSI/OE
A8 - A11 CS2 A0 - A7 CDM5332 4K x 8 ROM CSI/OE
A8 - A11 CS2 A0 - A7 CDM5332 4K x 8 ROM CSI/OE
A8 - A11 CS2 A0 - A7 CDM5332 4K x 8 ROM CSI/OE
CDP1800 SERIES CPU MRD
DATA BUS
FIGURE 6. 6K-BYTE ROM SYSTEMS USING THE CDP1882
4-7
CDP1881C, CDP1882, CDP1882C
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8

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