 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CXA3516R 3-channel 8-bit 165MSPS A/D Converter Amplifier PLL For the availability of this product, please contact the sales office. Description The CXA3516R is a 3-channel 8-bit 165MSPS A/D converter with built-in amplifier and PLL developed for LCD projectors and LCD monitors. The CXA3516R inputs RGB graphics signals from personal computers or others. After the input levels are controlled, the A/D conversion is performed with a clock generated by PLL. The digital output levels are compatible with TTL. This IC operates at a maximum conversion rate of 165MHz, and can support up to UXGA. Control register supports both I2C and 3-wire bus. Features * Supply voltage: 5V, 3.3V * Power consumption: 1.8W typ. (165MSPS) * 144-pin LQFP * 3-ch AMP and PLL eliminate design time for mutual connections. Structure Bipolar silicon monolithic IC Applications * LCD monitors * LCD projectors * Digital TVs * PDPs 144 pin LQFP (Plastic) Functions and Performance * Power save function * Supports both I2C and 3-wire bus Amplifier block * Clamp * Main contrast: 8-bit * Sub contrast: 8-bit x 3 * Main brightness: 8-bit x 3 * CbCr offset: 6-bit x 2 * Supports YCbCr input * Two input systems * AMP monitor output/SW monitor output * SYNCSEP function A/D converter block * Maximum conversion rate: 165MSPS * Supports UXGA input * Supports demultiplexed output * Supports both in-phase and alternate phase during demultiplexing * Supports YUV4:2:2 output * Output high impedance mode * Built-in reference voltage PLL block * Sync input frequency: 10kHz to 130kHz * Clock delay: 1/32 to 64/32CLK * VCO counter: 12-bit * Low clock jitter * CLK inversion * CLK and 1/2CLK outputs * Phase comparison hold * Output high impedance mode Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99Y28A07-PS CXA3516R Absolute Maximum Ratings (Ta = 25C) Item DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, AVCCVCO, DVCCPLL, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB AVCCAD3, DVCCAD3 ADDRESS, XPOWERSAVE, XSENABLE, 3WIRE/I2C, HOLD, XTLOAD, EVEN/ODD, XCLKIN, CLKIN, SYNCIN1, SYNCIN2, CLPIN, RC1, RC2, R/CrIN1, R/CrIN2, R/CrCLP, G/YCLP, B/CbCLP, SOGIN1, G/YIN1, SOGIN2, G/YIN2, B/CbIN1, B/CbIN2, RCrOUT, G/YOUT, B/CbOUT, DACTESTOUT SDA, SCL Storage temperature Allowable power dissipation Tstg PD Maximum ratings 5.5 5.5 Unit V V Supply voltage Input voltage GND - 0.5 to 5V VCC + 0.5 or 5.5 V GND - 0.5 to 5.5 -65 to +150 5 V C W Recommended Operating Conditions Item DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, DVCCPLL, AVCCVCO, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB AVCCAD3, DVCCAD3 TTL input pin XPOWERSAVE, HOLD, XTLOAD, EVEN/ODD, SYNCIN1, SYNCIN2, CLPIN High level Low level High level PECL input pin CLKIN, XCLKIN Low level Straight mode Maximum conversion rate DMUX mode YUV4:2:2 D2 mode YUV4:2:2 special mode Operating ambient temperature Ta Min. 4.75 3 2 -- DVCCPLL -0.8 -- 100 165 100 100 -10 Typ. 5 3.3 -- -- -- -- -- -- -- -- -- Max. 5.25 3.6 -- 0.8 -- DVCCPLL -1.6 -- -- -- -- +75 Unit V V V V V V MSPS MSPS MSPS MSPS C Supply voltage -2- CXA3516R Pin Configuration (Top View) DSYNC/DIVOUT DGNDPLLTTL AGNDADREF DGNDADTTL DGNDADTTL DVCCPLLTTL DVCCADTTL DVCCADTTL EVEN/ODD DGNDAD3 DGNDAD3 AGNDAD3 AVCCAD3 DVCCAD3 SOGOUT UNLOCK 1/2XCLK XTLOAD DVCCAD DPGND 1/2CLK HOLD XCLK VRB GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 GA7 GA6 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 XCLKIN 109 CLKIN 110 SYNCIN1 111 SYNCIN2 112 CLPIN 113 DVCCPLL 114 DGNDPLL 115 AVCCVCO 116 AGNDVCO 117 RC1 118 RC2 119 AVCCIR 120 IREF 121 DPGND 122 AGNDIR 123 G/YIN1 124 AVCCAMPG 125 G/YIN2 126 AGNDAMPG 127 G/YCLP 128 B/CbCLP 129 R/CrCLP 130 DPGND 131 SOGIN1 132 B/CbIN1 133 AVCCAMPB 134 SOGIN2 135 B/CbIN2 136 AGNDAMPB 137 DPGND 138 R/CrIN1 139 AVCCAMPR 140 R/CrIN2 141 AGNDAMPR 142 G/YOUT 143 DACTESTOUT 144 1 B/CbOUT 2 ADDRESS 3 R/CrOUT 4 NC 5 NC 6 XPOWER SAVE 7 DGNDREG 8 DVCCREG 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3WIRE/I2C DVCCADTTL AVCCADREF DGNDADTTL DVCCADTTL XSENABLE DVCCAD3 AVCCAD3 SCL SEROUT SDA DGNDADTTL DPGND RA0 RA1 DGNDAD3 RA2 RA3 RA4 RA5 RA6 AGNDAD3 DGNDAD3 RA7 RB0 RB1 VRT RB2 72 GA4 71 GA3 70 GA2 69 GA1 68 GA0 67 DGNDADTTL 66 DGNDAD3 65 DVCCADTTL 64 BB7 63 BB6 62 BB5 61 BB4 60 BB3 59 GNDAD3 58 BB2 57 BB1 56 BB0 55 DGNDADTTL 54 DVCCADTTL 53 BA7 52 BA6 51 BA5 50 DGNDAD3 49 BA4 48 BA3 47 BA2 46 BA1 45 BA0 44 DGNDADTTL 43 DGNDAD3 42 DVCCADTTL 41 RB7 40 RB6 39 RB5 38 RB4 37 RB3 -3- GA5 CLK TOP Block Diagram CLPIN R/CrOUT G/YOUT B/CbOUT VRT VRB VRB VRT SW SW SW R/CrIN1 AMP R Cr Offset (6) ADC R SW R Sub Contrast (8) Sub Brightness (8) RB7 to RB0 RA7 to RA0 R/CrIN2 R/CrCLP Sub Contrast (8) Sub Brightness (8) AMP G ADC G GB7 to GB0 GA7 to GA0 G/YIN1 SW G G/YCLP Sub Contrast (8) Sub Brightness (8) AMP B Cb Offset (6) ADC B BA7 to BA0 PLL PD SW PLL CP (3) VCO CLK XCLK COUNTER (12) REGISTER 1/2DIV Width (2) COARSE DELAY (2) 1/2CLK 1/2XCLK DSYNC/DIVOUT BB7 to BB0 SDA SCL HOLD RC1 RC2 SOGOUT SEROUT ADDRESS 3WIRE/I2C UNLOCK XTLOAD XPOWER SAVE XSENABLE EVEN/ODD -4- FINE DELAY (6) SW SOGT SW SOGO B/CbIN1 SW B B/CbIN2 B/CbCLP VTH (4) VHYS (2) Main Contrast (8) SW SOGP SYNCSEP DIV 1, 2, 4, 8 SYNCIN1 SYNCIN2 SW SYNCIN SOGIN1 SYNCSEP SOGIN2 SYNCTIP CLP SYNCSEP DATA MODE G/YIN2 CXA3516R Amplifier Block Diagram CLPIN POL 1bit CLP CLP GCA DRV ADC R VRT Sub Brightness Cr Offset 8bit 6bit VRB Sub Contrast 8bit CLP SW R CLPOFF 1bit SW 1bit R/CrCLP R/CrOUT RGB/YUV 1bit Rch R/CrIN1 R/CrIN2 G/YCLP G/YOUT Gch SW CLP CLP GCA DRV VRT Sub Brightness 8bit VRB Sub Contrast 8bit CLP SW G G/YIN1 ADC G G/YIN2 -5- B/CbCLP B/CbOUT SW CLP CLP GCA DRV VRT Sub Brightness Cb Offset 8bit 6bit VRB Sub Contrast 8bit CLP SW B Main Contrast 8bit SYNC SEP SYNC SEP SW SOGP SYNC SEP VTH 4bit VHYS 2bit Bch AMP POWER SAVE 1bit ADC B B/CbIN1 B/CbIN2 SYNC SEP POWER SAVE SOGIN1 SYNC TIP CLP SYNC ON GREEN SEPARATOR 1bit SYNC TIP CLP SOGIN2 SYNC ON GREEN SYNCT1 SYNC ON GREEN SYNCT2 SYNC ON GREEN SYNCP DACTEST DACTEST OUT CXA3516R PLL Block Diagram PLL RC1 RC2 Coarse Delay 2bit DSYNC By-pass 1bit TTLIN M/S SW M DIVOUT Delay DIVOUT WIDTH 1bit 2bit DIVOUT Delay Reset Pulse Generator DIVOUT Pulse Width Polarity TTLOUT SW Coarse Delay J K Q Q EVEN/ODD (TTL) CLKIN (PECL) XCLKIN (PECL) PECLIN DSYNC Enable 1bit DSYNC/DIVOUT (TTL) DSYNC POL 1bit CLK Enable 1bit DSYNC HOLD 1bit DSYNC HOLD TTLOUT XCLK Enable 1bit CLK (TTL) SOG Enable 1bit SOGOUT (TTL) TTLOUT 1bit RGBIN1/2SEL SW SYNC ON GREEN SYNCT1 SYNC ON GREEN SYNCT2 Phase Detector Charge Pump VCO + 1/4 SW DIV 1, 2, 4, 8 3bit 6bit 1bit PD POL Programmable Counter 1bit VCO By-pass 2bit DIV 1, 2, 4, 8 RESET Fine Delay SW Polarity SW 1bit 1bit SYNC OUT SW SOG OUT POL Polarity TTLOUT XCLK (TTL) CLK (ADC) 1/2CLK Enable 1bit TTLOUT 1/2CLK (TTL) SYNC ON GREEN SYNCP SYNCIN1 (TTL) 1bit SYNC POL 1/2 -6- 12bit VCO DIV 1/256 to 1/4096 Polarity HOLD POL 1bit Polarity CLP POL 1bit TTLIN PLL Power Save 1bit Clamp Pulse XTLOAD (TTL) TTLIN SW SW SYNCIN2 (TTL) TTLIN 1bit SYNCP/HSYNC M/S SW M UNLOCK Enable 1bit UNLOCK Detect 1bit HSYNC1/2 1/2XCLK Enable 1bit TTLOUT 1/2XCLK (TTL) 1/2CLK (ADC) HOLD (TTL) TTLIN UNLOCK CLPIN (TTL) TTLIN DAC IREF CXA3516R SYNC Block Diagram R1 SYNCP1 SYNCT SYNC SEP SW SOGT SW SOGO SYNCT1 R/CrIN1 AMP BLOCK PLL BLOCK G1 G/YIN1 SYNC OUT SW 1bit SOG OUT POL 1bit PEDESTAL CLAMP B/CbIN1 B1 SOGIN1 SYNC TIP CLAMP POL SYNCIN1 TTL OUT 1bit SOG Enable SOGOUT H1 -7- SW SOGP SYNC SEP SW PLL SW SYNCIN SYNCT2 SYNC SEP 1bit HSYNC1/2 4bit 2bit VTH VHYS 1bit RGB IN 1/2 Select POL PLL R2 R/CrIN2 G2 G/YIN2 PEDESTAL CLAMP SYNCP2 1bit 1bit SYNC POL SYNCP/HSYNC B/CbIN2 B2 SOGIN2 SYNC TIP CLAMP SYNCIN2 H2 CXA3516R ADC Block Diagram VRB VRB RA7 to RA0 RB7 to RB0 VRB ADC R 8 VRT 8 AMP R VRB ADC G VRT MODE 8 8 GA7 to GA0 GB7 to GB0 AMP G CLK 1/2CLK -8- VRB VRT VRT ADC B 8 8 BA7 to BA0 BB7 to BB0 CLK CONT DATA FORMAT DATA INV 1bit 3bit VRT CXA3516R AMP B ADC Power Save 1bit CXA3516R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16, 94 17 18, 92 Symbol B/CbOUT ADDRESS R/CrOUT NC NC XPOWER SAVE DGNDREG DVCCREG SDA SCL XSENABLE SEROUT 3WIRE/I2C AVCCADREF AVCCAD3 VRT DVCCAD3 I/O O I O -- -- I -- -- I I I O I -- -- O -- -- -- O -- -- O O O O O -- O -- Typical signal 1.83V -- 1.83V -- -- TTL GND 5V -- -- TTL TTL -- 5V 3.3V 2.9V 3.3V 5V GND TTL GND GND TTL TTL TTL TTL TTL 5V 1.9V GND Description Amplifier output signal monitor I2C slave address setting Amplifier output signal monitor Not used Not used Power save setting Register GND Register power supply Control register data input Control register CLK input Enable signal input for 3-wire control register 3-wire control register data readout Selection of input between I2C bus and 3-wire bus Reference power supply for A/D converter Analog power supply for A/D converter Top reference voltage output for A/D converter Digital power supply for A/D converter TTL output power supply for A/D converter TTL output GND for A/D converter Data output for R-channel port A side Digital GND for A/D converter Analog GND for A/D converter Data output for R-channel port B side Data output for B-channel port A side Data output for B-channel port B side Data output for G-channel port A side Data output for G-channel port B side Digital power supply for A/D converter Bottom reference voltage output for A/D converter Reference voltage GND for A/D converter -9- 19, 32, 42, 54, DVCCADTTL 65, 76, 90 20, 33, 44, 55, DGNDADTTL 67, 77, 89 21, 22, 24 to 28, 31 RA0 to RA7 23, 30, 43, 50, DGNDAD3 59, 66, 79, 86 29, 80 34 to 41 45 to 49, 51 to 53 56 to 58, 60 to 64 68 to 75 78, 81 to 85, 87, 88 91 93 95 AGNDAD3 RB0 to RB7 BA0 to BA7 BB0 to BB7 GA0 to GA7 GB0 to GB7 DVCCAD VRB AGNDADREF CXA3516R Pin No. 96 97 98 99 100 101 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 124 125 126 127 128 129 130 132 133 Symbol DVCCPLLTTL I/O -- Typical signal 5V GND TTL TTL TTL TTL TTL Description TTL output power supply for PLL TTL output GND for PLL Inverted CLK output CLK output Inverted 1/2CLK output 1/2CLK output DSYNC or DIVOUT signal output DGNDPLLTTL -- XCLK CLK 1/2XCLK 1/2CLK DSYNC/ DIVOUT UNLOCK SOGOUT HOLD XTLOAD EVEN/ODD XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVCCPLL DGNDPLL AVCCVCO AGNDVCO RC1 RC2 AVCCIR IREF AGNDIR G/YIN1 AVCCAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP SOGIN1 B/CbIN1 O O O O O O O I I I I I I I I -- -- -- -- -- -- -- I -- I -- I -- -- -- -- I I Open collector Unlock signal output TTL TTL TTL TTL PECL PECL TTL TTL TTL 5V GND 5V GND 2.1V 2 to 4.5V 5V 1.2V GND -- 5V -- GND -- -- -- 2.8V -- Output for SYNC ON GREEN Input for phase comparison disable signal Programmable counter reset setting Inverted pulse input of ADC sampling CLK Inverted CLK input for testing CLK input for testing Sync input 1 Sync input 2 Clamp pulse input Digital power supply for PLL Digital GND for PLL Analog power supply for PLL VCO Analog GND for PLL VCO External pin for PLL loop filter External pin for PLL loop filter Analog power supply for IREF Current setup Analog GND for IREF G/Y signal input 1 Power supply for G/Y amplifier block G/Y signal input 2 GND for G/Y amplifier block Clamp capacitor for brightness Clamp capacitor for brightness Clamp capacitor for brightness SYNC ON GREEN signal input 1 B/Cb signal input 1 - 10 - CXA3516R Pin No. 134 135 136 137 139 140 141 142 143 144 Symbol AVCCAMPB SOGIN2 B/CbIN2 AGNDAMPB R/CrIN1 AVCCAMPR R/CrIN2 AGNDAMPR G/YOUT DAC TEST OUT I/O -- I I -- I -- I -- O O -- Typical signal 5V 2.8V -- GND -- 5V -- GND 1.83V 5V GND Description Power supply for B/Cb amplifier block SYNC ON GREEN signal input 2 B/Cb signal input 2 GND for B/Cb amplifier block R/Cr signal input 1 Power supply for R/Cr amplifier block R/Cr signal input 2 GND for R/Cr amplifier block Monitor pin for amplifier output signal DAC testing output for amplifier block control register GND 14, 102, 122, DPGND 131, 138 - 11 - CXA3516R Pin Description and Pin Equivalent Circuit Pin No. Symbol I/O Typical signal Equivalent circuit Description Amplifier output signal monitor. Each monitor can output either the entered signal immediately before A/D converter or the signal after switching between 2 types of input signals. The 2 types of input signals can be selected by the control register and output. These pins are emitter follower outputs, but the internal bias current is so small that a 820 resistor should be connected between these pins and GND to monitor high frequency signals. When not used, connect to AVCCAMP. 3 R/CrOUT O 1.83V AVCCAMP 100 3 143 G/YOUT O 1.83V 143 1 280 AGNDAMP 1 B/CbOUT O 1.83V 140 125 134 142 127 137 AVCCAMPR AVCCAMPG AVCCAMPB AGNDAMPR AGNDAMPG AGNDAMPB -- -- -- -- -- -- 5V 5V 5V GND GND GND DVCCPLL Power supply for amplifier block. GND for amplifier block. DVCCPLLTTL 100k 105 SOGOUT O TTL 105 DGNDPLLTTL DGNDPLL Sync separated SYNC signal output. Separates and outputs the SYNC signal from SYNC ON GREEN input signal. (SYNC signal input from SYNCIN1 and SYNCIN2 pins can be output.) Both positive and negative polarity outputs are supported. The polarity is selected by the control register. 132 SOGIN1 I 2.8V AVCCAMPG 132 135 150 135 SOGIN2 I 2.8V AGNDAMPG 100 SYNC ON GREEN signal inputs. Input via a 0.1F capacitor. When not used, connect to AVCC. The SYNC TIP clamp level is approximately 2.0V + Vf (0.8V) = approximately 2.8V. At this time, if the pin voltage is lowered, these pins go to low impedance and current flows from the IC. When these pins are at the SYNC TIP level or higher, the clamp circuit is off and only an input base current of approximately 1.2A flows. - 12 - CXA3516R Pin No. Symbol I/O Typical signal Equivalent circuit Description Amplifier block 1 Analog input signal. Input via a 0.1F ceramic capacitor. The typical signal level is 0.7V. Signals from 0.5V (min.) to 1.0V (max.) can be supported. IN1 and IN2 are selected by the control register. Leave these pins open when not used. RGB input and YCbCr input can be selected by the control register. 1 The clamp level typical values are as follows. In case RGB is input 2.2V + Vf (0.8V) = approximately 3V In case YCbCr is input G/YIN: 2.2V + Vf (0.8V) = approximately 3V R/CrIN, B/CbIN: 2.7V + Vf (0.8V) = approximately 3.5V Clamp period: A clamp current of 1.2mA (max.) flows. Signal period: A base current of 0.5A flows to the IC. Clamp capacitor connector for brightness. Connect 0.1F ceramic capacitors between these pins and GND. 2 Typical levels of the clamp are as AVCCAMP 250 130 128 129 500 AGNDAMP 100 100 300 100k 139 R/CrIN1 I 141 R/CrIN2 I 1 AVCCAMP 124 G/YIN1 I 1 139 126 141 133 124 136 25k 100 25k 250 100 500 126 G/YIN2 I 1 AGNDAMP 400 100 133 B/CbIN1 I 1 136 B/CbIN2 I 1 130 R/CrCLP -- 2 128 G/YCLP -- 2 129 B/CbCLP -- 2 follows. In case RGB is input SUB BRIGHTNESS 00H: 2.68V 80H: 2.81V FFH: 2.94V In case YCbCr is input G/YCLP is the same as above. R/Cr, B/CbCLP are as follows. CbCr Offset 00H: 3.04V 20H: 3.07V 3FH: 3.102V Clamp period: A clamp current of 1.2mA (max.) flows. Signal period: A base current of 0.5A flows to the IC. - 13 - CXA3516R Pin No. Symbol I/O Typical signal Equivalent circuit DVCCPLL 1.5k Description Clamp pulse input for the signal of analog input clamp and brightness clamp. Both positive and negative polarity inputs are supported. The polarity is selected by the control register. The input pulse width should be 200ns or more. 113 CLPIN I TTL 192 113 1.5V DGNDPLL A/D converter block 99 CLK O TTL DVCCPLLTTL 98 XCLK O TTL 100k 98 99 101 100 CLK output. Output the same frequency CLK as that of ADC sampling. These are complemental TTL levels. These pins can be independently controlled on and off (power save) by the control register. 1/2CLK output. Output a half frequency CLK of that of ADC sampling. These are complemental TTL levels. These pins can be independently controlled on and off (power save) by the control register. Data output for R-channel port A side. 101 1/2CLK O TTL DGNDPLLTTL DGNDPLL 100 1/2XCLK O TTL 21, 22, 24 to 28, RA0 to RA7 31 34 to 41 68 to 75 RB0 to RB7 GA0 to GA7 O TTL DVCCADTTL O O TTL TTL Data output for R-channel port B side. Data output for G-channel port A side. Data output for G-channel port B side. 100k 78, 81 to 85, GB0 to GB7 87, 88 45 to 49, BA0 to BA7 51 to 53 56 to 58, BB0 to BB7 60 to 64 15 95 16, 94 29, 80 18, 92 91 AVCCADREF AGNDADREF AVCCAD3 AGNDAD3 DVCCAD3 DVCCAD O TTL DGNDADTTL DGNDAD3 O O -- -- -- -- -- -- TTL TTL 5V GND 3.3V GND 3.3V 5V Data output for B-channel port A side. Data output for B-channel port B side. Reference power supply for A/D converter. Reference GND for A/D converter. Analog power supply for A/D converter. Analog GND for A/D converter. Digital power supply for A/D converter. Digital power supply for A/D converter. - 14 - CXA3516R Pin No. Symbol I/O Typical signal Equivalent circuit Description 23, 30, 43, 50, DGNDAD3 59, 66, 79, 86 19, 32, 42, 54, DVCCADTTL 65, 76, 90 20, 33, 44, 55, DGNDADTTL 67, 77, 89 -- GND Digital GND for A/D converter. -- 5V TTL output power supply for A/D converter. -- GND TTL output GND for A/D converter. AVCCADREF 90 17 VRT O 2.9V 17 2k 20 Top reference voltage output for A/D converter input dynamic range. Connect to AVCCAD3 via a 1F ceramic capacitor. AGNDADREF AVCCADREF 20 93 VRB O 1.9V 93 4k 80 AGNDADREF Bottom reference voltage output for A/D converter input dynamic range. Connect to AVCCAD3 via a 1F ceramic capacitor. - 15 - CXA3516R Pin No. PLL block Symbol I/O Typical signal Equivalent circuit Description 111 SYNCIN1 I TTL Input SYNC signal at TTL level. The input polarity is switched by the control register. Leave this pin open when not used. Input SYNC signal at TTL level. The input polarity is switched by the control register. Leave this pin open when not used. Input signal for phase comparison HOLD. Phase comparison is stopped, and VCO oscillation frequency is held. When not be hold, fix the pin as follows. When HOLDPOL register is "1", fix this pin to low level. When HOLDPOL register is "0", leave this pin open or fix to high level. 1.5V 112 SYNCIN2 I TTL DVCCPLL 106 HOLD I TTL 40k 106 107 108 111 112 192 108 EVEN/ODD I TTL DGNDPLL Input the signal used to invert the A/D converter sampling CLK. Low: EVEN mode High: ODD mode Normally fix it to low level. Programmable counter reset. Normally fix it to high level or leave open. In programmable counter test mode, set it to low level to call up the register contents. When not used, leave this pin open or fix to high level. 107 XTLOAD I TTL DVCCPLL 110 CLKIN I PECL 110 109 14k 500 14k 500 CLK input for ADC operation check. Input PECL level signal complementally. When using this pin, set CLK to external input by the control register. Leave this pin open when not used. 109 XCLKIN I PECL DGNDPLL - 16 - CXA3516R Pin No. Symbol I/O Typical signal Equivalent circuit DVCCPLL DVCCPLLTTL Description 103 DSYNC/ DIVOUT 100k O TTL 103 This pin can output either DSYNC signal or DIVOUT signal. It can be selected by the control register. In addition, the output polarity can be selected by the control register. DGNDPLLTTL DGNDPLL DVCCPLLTTL 104 UNLOCK -- -- 100k 104 DGNDPLLTTL DGNDPLL UNLOCK signal output. Make a discrimination between lock and unlock in the analog manner by connecting the external circuit. Leave this pin open when not used. Do not connect this pin to neither power supply nor GND. AVCCIR 118 RC1 -- 2.1V 118 External pin for PLL loop filter. 119 119 RC2 -- 2 to 4.5V AGNDIR AVCCIR External pin for PLL loop filter. DPGND 121 IREF I 1.2V 121 AGNDIR DPGND Connect an external resistor (3k) to supply a stabilized current to the inside of the IC. (charge pump current, etc.) Connect this pin to GND via 0.1F ceramic capacitor connected as close to the pin as possible. The band gap voltage is output. 114 115 96 DVCCPLL DGNDPLL DVCCPLLTTL -- -- -- 5V GND 5V - 17 - Digital power supply for PLL. Digital GND for PLL. TTL output power supply for PLL. CXA3516R Pin No. 97 120 123 116 117 Symbol DGNDPLLTTL AVCCIR AGNDIR AVCCVCO AGNDVCO I/O -- -- -- -- -- Typical signal GND 5V GND 5V GND Equivalent circuit Description TTL output GND for PLL. Analog power supply for IREF. Analog GND for IREF. Analog power supply for PLL VCO. Analog GND for PLL VCO. Control register block DVCCREG 200k 4k 9 9 SDA I -- Input control register data. Switching between the I2C and 3-wire bus mode is performed by the 3WIRE/I2C pin. DGNDREG DVCCREG 200k 4k 10 10 SCL I -- Input control register CLK. Switching between the I2C and 3-wire bus mode is performed by the 3WIRE/I2C pin. 10k DGNDREG DVCCREG 15 1k Set slave address when using I2C bus mode. Slave address: 1 0 0 1 1 S2 S1 0 VCC to 3/4VCC 3/4VCC to 2/4VCC 2/4VCC to 1/4VCC 1/4VCC to GND S2 0 1 1 0 S1 1 1 0 0 2 ADD I -- 2 15 15 DGNDREG Connect this pin to GND during 3-wire bus mode. - 18 - CXA3516R Pin No. Symbol I/O Typical signal Equivalent circuit DVCCREG 200k 4k 11 Description 11 XSENABLE I TTL Inputs enable signal for 3-wire bus. High level: Control disabled Low level: Control enabled Connect this pin to GND when using I2C. DGNDREG DVCCREG 100k 100k 13 Selection of input between I2C bus and 3-wire bus. VCC to 2/3VCC 2/3VCC to 1/3VCC 1/3VCC to GND 3-wire bus mode I2C 3V mode I2C 5V mode 13 3WIRE/I2C I -- 100k 15 DGNDREG DVCCREG 15 12 12 SEROUT O TTL 100k When using the read mode of 3-wire bus mode, the register information written once is output in series order from the LSB of the setting sub address data. DGNDREG 7 8 DGNDREG DVCCREG -- -- GND 5V DVCCREG 10 GND for register. Power supply for register. 6 XPOWER SAVE I TTL 1k 6 Power save for all functions including the control register block. High level: Normal operation Low level: Power save DGNDREG - 19 - CXA3516R Pin No. Symbol I/O Typical signal Equivalent circuit DVCCREG Description 144 DAC TEST OUT O 5V 144 DAC test output for control register of amplifier block. Current is output by open collector. Normally connect to AVCC. DGNDREG 14, 102, 122, 131, DPGND 138 4 5 NC NC -- GND This pin is connected to the die pad. Connect to the specified GND in Application Circuit. Not used. Leave this pin open or connect to GND. Not used. Leave this pin open or connect to GND. -- -- -- -- - 20 - CXA3516R Electrical Characteristics (Ta = 25C, AVCC, DVCC = 5V, AVCC3, DVCC3 = 3.3V) Supply Current Item Current during operating 5V current consumption 3.3V current consumption ICC5 ICC3 CLK = DC CLK = DC -- -- 180 180 240 226 mA mA Symbol Measurement conditions Min. Typ. Max. Unit Register control power save current 5V power save current consumption 3.3V power save current consumption ICC5PS ICC3PS -- -- 26 3.0 42 7.2 mA mA XPOWER SAVE pin control power save current 5V power save current consumption 3.3V power save current consumption ICC5XPS ICC3XPS -- -- 9.0 3.0 22 7.2 mA mA Register Item Symbol Measurement conditions Min. Typ. Max. Unit 3-wire control bus (SDA, SCL, SENABLE) High level input voltage Low level input voltage High level input current Low level input current Threshold voltage High Low Threshold voltage Low High Input capacitance SCL clock frequency XSENABLE setup time XSENABLE hold time XSENABLE high level pulse width SDA setup time SDA hold time SDA delay time VIH VIL IIH IIL VTHHL1 VTHLH1 CI FSCL1 TENS TENH TENPW TDS TDH TD in WRITE/READ mode in WRITE/READ mode in WRITE/READ mode in WRITE/READ mode in WRITE/READ mode in WRITE/READ mode in READ mode 2.0 0 -2.0 -5.0 -- -- -- -- 3 0 300 3 0 -- -- -- -- -- 1.3 1.65 -- -- 10 10 -- 10 10 11 5.0 0.8 0 0 -- -- 10 10 -- -- -- -- -- -- V V A A V V pF MHz ns ns ns ns ns ns - 21 - CXA3516R Register (Cont.) Item I2C control bus (SDA, SCL) High level input voltage VIH I2C (High) mode Low level input voltage VIL 2.3 0 -2.0 -5.0 -- -- 2.0 0 -1.0 -5.0 -- -- IOH = 3mA 0 -- 0 4.7 START condition: After this period, first clock is generated. -- -- -- -- 1.6 1.95 -- -- -- -- 1.3 1.65 0.15 -- 50 5.0 5.0 1.0 0 0 -- -- 5.0 0.8 0 0 -- -- 0.5 10 100 -- V V A A V V V V A A V V V pF kHz s Symbol Measurement conditions Min. Typ. Max. Unit High level input current IIH Low level input current Threshold voltage High Low Threshold voltage Low High IIL VTHHL2 VTHLH2 High level input voltage VIH I2C (Low) mode Low level input voltage VIL High level input current IIH Low level input current Threshold voltage High Low Threshold voltage Low High IIL VTHHL3 VTHLH3 SDA low level output voltage VOL Input capacitance SCL clock frequency Bus free-time STOP START Hold time (resend) Hold time in SCL clock at Low state Hold time in SCL clock at High state Setup time under resend START condition Data hold time Data setup time Rise time Fall time Setup time under STOP condition Capacitive load of each bus line CI FSCL2 TBUF THD;STA 4.0 5.0 -- s TLOW THIGH TSU;STA THD;DAT TSU;DAT TR TF TSU;STO Cb - 22 - 4.7 4.0 4.7 0 250 -- -- 4.0 -- 5.0 5.0 5.0 5.0 5000 -- -- 5.0 -- -- -- -- -- -- 1000 300 -- 400 s s s s ns ns ns s pF CXA3516R AMP Item Brightness characteristics Brightness level H (ADC OUT) Brightness level L Brightness level M Brightness level H Brightness level Low side variable range Brightness level High side variable range Clamp characteristics Cb, Cr clamp level M (ADC OUT) Cb, Cr clamp level L Cb, Cr clamp level M Cb, Cr clamp level H Cb, Cr clamp level Low side variable range Cb, Cr clamp level High side variable range Clamp pulse minimum width TWCLP Contrast characteristics Main Contrast = 0 Sub Contrast = 128 Vin = 1.2Vp-p RGB/YUV mode, G, B, R OUT Main Contrast = 128 Sub Contrast = 128 Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT Main Contrast = 255 Sub Contrast = 128 Vin = 0.45Vp-p RGB/YUV mode, G, B, R OUT Main Contrast = 128 Sub Contrast = 0 Vin = 0.85Vp-p RGB/YUV mode, G, B, R OUT - 23 - VCLMAD VCLL VCLM VCLH Cb, Cr offset = 32 ADC output conversion level Cb, Cr offset = 0 B, R OUT pin voltage Cb, Cr offset = 32 B, R OUT pin voltage Cb, Cr offset = 63 B, R OUT pin voltage VCLL - VCLM VCLH - VCLM 120 1.94 1.99 2.03 -- -- 200 128 2.23 2.28 2.34 -60 60 -- 136 2.46 2.51 2.58 -- -- -- LSB V V V mV mV ns VBRHAD VBRL VBRM VBRH Sub Brightness G, B, R = 255 ADC output conversion level Sub Brightness G, B, R = 0 G, B, R OUT pin voltage Sub Brightness G, B, R = 128 G, B, R OUT pin voltage Sub Brightness G, B, R = 255 G, B, R OUT pin voltage VBRL - VBRM VBRH - VBRM 53 1.388 1.63 1.86 -- -- 61 1.588 1.83 2.06 -242 230 69 1.788 2.03 2.26 -- -- LSB V V V mV mV Symbol Measurement conditions Min. Typ. Max. Unit Main contrast control L VMCL 0.62 0.78 0.94 times Main contrast control M VMCM 1.23 1.53 1.84 times Main contrast control H VMCH 1.79 2.24 2.69 times Sub contrast control L VSCL 0.96 1.2 1.44 times CXA3516R AMP (Cont.) Item Symbol Measurement conditions Main Contrast = 128 Sub Contrast = 255 Vin = 0.55Vp-p RGB/YUV mode, G, B, R OUT Main Contrast = 128 Sub Contrast = 128 Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT Min. Typ. Max. Unit Sub contrast control H VSCH 1.48 1.85 2.22 times Gain difference among RGB Gain -8 0 8 % Frequency response Main Contrast = 128 Sub Contrast = 128 FC - 3dB Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT -- 220 -- MHz Cross talk characteristics Cross talk between channels CTC Main Contrast = 128 Sub Contrast = 128 fin = 100MHz, Vin = 0.6Vp-p Main Contrast = 128 Sub Contrast = 128 fin = 100MHz, Vin = 0.6Vp-p -- -35 -- dB Cross talk among RGB CTB -- -30 -- dB SYNCSEP Item Symbol Measurement conditions Min. Typ. Max. Unit SYNC SEP input characteristics SYNC TIP input minimum amplitude SYNC TIP input minimum duty SYNC SEP threshold voltage SYNC SEP hysteresis voltage VSYN DSYN VTH VHYS SYNC SEP VTH = 1000 SYNC SEP VHYS = 10 SYNC SEP VTH = 1000 SYNC SEP VHYS = 10 0.2 5 116 36 -- -- 145 45 -- -- 174 54 Vp-p % mV mV - 24 - CXA3516R PLL Item Hold characteristics RC1 pin leak current Ileak -- -- 1.0 nA Symbol Measurement conditions Min. Typ. Max. Unit SYNC signal input characteristics SYNC signal input frequency range VCO characteristics Clock frequency Clock frequency Clock frequency Clock frequency VCO lock range VCO gain 1 VCO gain 2 VCO gain 3 VCO gain 4 Jitter characteristics SYNC input signal - Clock output jitter (NTSC) SYNC input signal - Clock output jitter (VGA) SYNC input signal - Clock output jitter (SVGA) SYNC input signal - Clock output jitter (XGA) SYNC input signal - Clock output jitter (SXGA) SYNC input signal - Clock output jitter (UXGA) Delay sync - Clock output jitter Triggered at SYNC Fsync = 15.73kHz Fclk = 12.27MHz N = 780 Triggered at SYNC Fsync = 31.47kHz Fclk = 25.18MHz N = 800 Triggered at SYNC Fsync = 48.08kHz Fclk = 50.00MHz N = 1040 Triggered at SYNC Fsync = 56.48kHz Fclk = 75.00MHz N = 1328 Triggered at SYNC Fsync = 79.98kHz Fclk = 135.01MHz N = 1688 Triggered at SYNC Fsync = 75.00kHz Fclk = 162.00MHz N = 2160 Triggered at DSYNC - 25 - FCLK1 FCLK2 FCLK3 FCLK4 Vlock KVCO1 VCO frequency divider DIV = 1/1 KVCO2 VCO frequency divider DIV = 1/2 KVCO3 VCO frequency divider DIV = 1/4 KVCO4 VCO frequency divider DIV = 1/8 VCO frequency divider DIV = 1/1 VCO frequency divider DIV = 1/2 VCO frequency divider DIV = 1/4 VCO frequency divider DIV = 1/8 80 40 14 5 2.0 300 150 75 37.5 -- -- -- -- -- -- -- -- -- 165 80 40 14 4.5 500 250 125 62.5 MHz MHz MHz MHz V Mrad/sv Mrad/sv Mrad/sv Mrad/sv FSYNC 10 -- 130 kHz Tj1p-p 2.4 2.7 3 ns Tj2p-p 1.6 1.8 2.0 ns Tj3p-p 1.3 1.4 1.5 ns Tj4p-p 0.9 1.0 1.1 ns Tj5p-p 0.8 0.9 1.0 ns Tj6p-p 0.8 0.85 1.0 ns Tj7p-p -- -- 0.1 ns CXA3516R ADC Item Resolution DC characteristics Integral linearity error Differential linearity error Reference voltage Top reference voltage Bottom reference voltage Input dynamic range AC characteristics Maximum conversion frequency of Straight Data out Mode Maximum conversion frequency of DMUX Parallel Data out Mode Maximum conversion frequency of DMUX Interleaved Data out Mode Maximum conversion frequency of 4:2:2 Data out D2 Mode Maximum conversion frequency of 4:2:2 Data out Special Mode Fc 100 -- -- MSPS VRT VRB VTB AVccAD3 as a reference AVccAD3 as a reference VRT - VRB -0.3 -1.3 0.9 -0.4 -1.4 1.0 -0.6 -1.6 1.1 V V V ILE DLE -- -- 1.0 0.4 -- 0.7 LSB LSB Symbol Measurement conditions Min. -- Typ. 8 Max. -- Unit bit Fc 165 -- -- MSPS Fc 165 -- -- MSPS Fc 100 -- -- MSPS Fc 100 -- -- MSPS - 26 - CXA3516R I/O Item Digital input (PECL) Digital input voltage: H Digital input voltage: L Digital input current: H Digital input current: L Digital input (TTL) Digital input voltage: H Digital input voltage: L Threshold voltage Digital input current: H Digital input current: L Digital output (TTL) VOH1 Digital output voltage: H VOH2 VOH3 VOH4 Digital output voltage: L VOL IOH = -2mA IOH = -2mA IOH = -2mA IOH = -2mA IOL = 1mA 2.4 2.3 2.05 1.85 -- 2.95 2.7 2.45 2.2 0.2 3.3 3.0 2.75 2.5 0.5 V V V V V VIH2 VIL2 VTH IIH2 IIL2 VIH = 3.5V VIL = 0.2V 2.0 -- -- -10 -20 -- -- 1.5 -- -- -- 0.8 -- -5 0 V V V A A VIH1 VIL1 IIH1 IIL1 DVccPLL as a reference DVccPLL as a reference VIH1 = DVCCPLL - 0.8V VIL1 = DVCCPLL - 1.6V -1.15 -- -100 -200 -- -- -- -- -- -1.5 100 0 V V A A Symbol Measurement conditions Min. Typ. Max. Unit - 27 - CXA3516R Timing Characteristics Item Clock output rise time Clock output fall time Delay sync output rise time Delay sync output fall time Data output rise time Data output fall time HOLD signal setup time HOLD signal hold time Delay sync delay time coarse delay Delay sync delay time fine delay Clock output delay from SYNC input signal Delay time between clock output and DSYNC/DIVOUT signal DIVOUT signal output delay time Clock - 1/2 clock 1/2 clock - Data Clock - Data Symbol TR_CLK TF_CLK TR_DSYNC TF_DSYNC TR_DATA TF_DATA Ths Thh Td_1 Td_2 Td_3 CL = 9pF Measurement conditions 0.8 to 2.0V (CLK, 1/2CLK) 2.0 to 0.8V (CLK, 1/2CLK) 0.8 to 2.0V (DSYNC, DIVOUT, SOGOUT) 2.0 to 0.8V (DSYNC, DIVOUT, SOGOUT) 0.8 to 2.0V 2.0 to 0.8V Min. 0.8 1.0 0.8 1.0 0.9 0.9 20 20 3 1/32 6.0 Typ. 1.4 1.5 1.4 1.5 1.2 1.2 -- -- -- -- 7.0 Max. 2.3 2.8 2.3 2.8 2.0 2.0 -- -- 6 64/32 8.0 Unit ns ns ns ns ns ns ns ns CLK CLK ns Td_4 CL = 9pF Difference between delay sync signal and DIVOUT signal 0.8 1.0 1.3 ns Td_5 Td_6 Td_7 Td_8 4 0.9 2.3 2.2 -- 1.2 2.6 2.8 5 1.6 3.2 3.8 CLK ns ns ns - 28 - Electrical Characteristics Measurement Circuit (3-wire Control) 1 5k AGNDADREF AVCCAD3 DVCCAD DVCCADTTL GB7 DGNDADTTL GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 GB0 DGNDAD3 DGNDADTTL DVCCADTTL GA7 GA6 72 71 70 GA2 GA1 GA0 DGNDADTTL DGNDAD3 DVCCADTTL BB7 BB6 BB5 BB4 BB3 GNDAD3 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 BB2 BB1 BB0 DGNDADTTL DVCCADTTL BA7 BA6 BA5 DGNDAD3 BA4 BA3 BA2 BA1 BA0 DGNDADTTL DGNDAD3 DVCCADTTL RB7 RB6 RB5 RB4 RB3 69 68 67 66 65 64 63 62 61 60 59 GA3 GA4 RB1 RB2 VRB EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 5 NC NC SCL SDA SEROUT DVCCREG DGNDREG XSENABLE XPOWER SAVE 6 7 8 R/CrOUT B/CbOUT ADDRESS 2 3 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 RA0 RA1 RA2 RA3 RA4 RA5 RA6 DPGND AVCCAD3 VRT DVCCAD3 3WIRE/I2C DGNDAD3 AGNDAD3 DVCCADTTL DGNDAD3 RA7 AVCCADREF DGNDADTTL DVCCADTTL DGNDADTTL RB0 1 EXT XCLK XCLKIN EXT CLK CLKIN HSYNC SYNCIN1 CLAMP PULSE SYNCIN2 CLPIN DVCCPLL DGNDPLL AVCCVCO AGNDVCO RC1 330p 3.3k RC2 0.33 AVCCIR ANALOG SIGNAL 100p 3k IREF DPGND AGNDIR 0.1 G/YIN1 75 AVCCAMPG 820 820 4.7k 4.7k - 29 - BUS CONTROLER 0.1 G/YIN2 75 AGNDAMPG G/YCLP B/CbCLP R/CrCLP ANALOG SIGNAL 0.1 DPGND SOGIN1 0.1 0.1 B/CbIN1 75 AVCCAMPB SOGIN2 0.1 B/CbIN2 ANALOG SIGNAL 75 AGNDAMPB DPGND 0.1 R/CrIN1 75 AVCCAMPR 0.1 R/CrIN2 75 AGNDAMPR G/YOUT 820 DACTESTOUT DVCCPLLTTL DVCCAD3 GA5 A A A AVCC5V DVCC5V 3.3V CXA3516R DGND AGND Control Register Functions Table bit Register Name D7 D4 m1 m0 n2 m7 m8 n1 m6 m4 m3 m2 D6 D2 D5 D3 D1 0 1 Control Range (typ.) Register No. Data D0 n0 m5 Block Function PLL 12 VCO DIV Feedback programmable counter control Frequency division ratio = (m + 1) x 8 + n PLL 2 DIV1, 2, 4, 8 O O VCO frequency divider control 1 00: 1/1 01: 1/2 10: 1/4 11: 1/8 000000: 1/32CLK 111111: 64/32CLK 2 O O O PLL 6 FINE DELAY Delay control (lower order) O O O PLL 2 Delay control (higher order) COARSE DELAY 2 O 00: 3CLK 01: 4CLK 10: 5CLK 11: 6CLK O - 30 - 3 Charge.Pump 000: 100A 001: 200A 010: 300A 011: 400A 100: 500A 101: 600A 110: 700A 111: 800A 3 2 00: 1CLK 01: 2CLK DIVOUT WIDTH 10: 4CLK 11: 8CLK DIVOUT DELAY DSYNC POL HOLD POL 0: 4CLK 1: 5CLK 0: NEGATIVE 1: POSITIVE 0: NEGATIVE 1: POSITIVE 3 1 1 1 3 4 4 PLL Charge pump current control O O O PLL DIVOUT signal pulse width control O O PLL DIVOUT signal delay control O O CXA3516R PLL Delay sync output polarity control PLL Hold input polarity control O Block D6 D4 D3 O O O O O O O O O 5 5 6 6 6 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 6 6 O O O O O O D1 D2 D0 D5 1 PD POL SYNC POL SOG OUT POL CLP POL VCO By-pass 0: DIVOUT DSYNC By-pass 1: DSYNC 5 5 5 DSYNC Hold SYNC OUT SW SYNCP/ HSYNC HSYNC 1/2 CLK Enable XCLK Enable 1/2CLK Enable 1/2XCLK Enable DSYNC Enable 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 0: EXT SYNC1 1: EXT SYNC2 0: SYNCP 1: HSYNC1, 2 0: SYNCT 1: SYNCP/HSYNC 0: NORMAL 1: HOLD 0: EXT CLK 1: INT VCO 5 0: NEGATIVE 1: POSITIVE 4 0: NEGATIVE 1: POSITIVE 4 0: NEGATIVE 1: POSITIVE 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0: NEGATIVE 1: POSITIVE 4 Function bit Register Name Control Range (typ.) Register No. D7 Data PLL Phase comparison input positive/negative control PLL Sync input polarity control PLL SOG OUT polarity control PLL Clamp pulse input polarity control PLL External clock/internal VCO switching PLL Delay sync output/DIVOUT switching PLL Delay sync hold function - 31 - PLL Output SOG/HSYNC switching PLL HSYNC1, 2 input/SOGA switching PLL HSYNC1 input/HSYNC2 input switching PLL TTL output off function (clock) PLL TTL output off function (inverse clock) PLL TTL output off function (1/2 clock) PLL TTL output off function (inverse 1/2 clock) CXA3516R PLL TTL output off function (delay sync) Block Register Name D7 D4 D1 D0 O O O O O O O O O 13 14 15 16 16 0: IN1 1: IN2 16 O O O O O O 12 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O D6 D2 D5 D3 UNLOCK Enable 6 6 6 7 8 9 10 11 SOG Enable SEROUT Enable MAIN CONTRAST SUB CONTRAST G SUB CONTRAST B SUB CONTRAST R 00000000: VRB - 61LSB SUB BRIGHTNESS G 11111111: VRB + 61LSB 00000000: VRB - 61LSB SUB BRIGHTNESS B 11111111: VRB + 61LSB 00000000: VRB - 61LSB SUB BRIGHTNESS R 11111111: VRB + 61LSB Cb Offset Cr Offset YCbCr mode 00000000: 128LSB - 16LSB 11111111: 128LSB + 16LSB 00000000: 128LSB - 16LSB 11111111: 128LSB + 16LSB 0: RGB IN 1: YCbCr IN 00000000: Mgain = x 0.79 11111111: Mgain = 1.21 00000000: Mgain = x 0.79 11111111: Mgain = 1.21 00000000: Mgain = x 0.79 11111111: Mgain = 1.21 00000000: Mgain = x 0.78 11111111: Mgain = x 2.24 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON 0: TTL out OFF 1: TTL out ON Control Range (typ.) 1 1 1 8 8 8 8 8 8 8 6 6 1 1 1 Function bit Register No. Data PLL TTL output off function (UNLOCK) PLL TTL output off function (SOG OUT) REGISTER TTL output off function (SER OUT) AMP Main contrast AMP Sub contrast Gch AMP Sub contrast Bch AMP Sub contrast Rch - 32 - 0: AMP OUT RGB Out Select 1: SW OUT RGB In Select AMP Sub brightness Gch AMP Sub brightness Bch AMP Sub brightness Rch AMP Cb input clamp level adjustment in YUV mode AMP Cr input clamp level adjustment in YUV mode AMP YCbCr input mode clamp level switching AMP RGB OUT output signal selection SW output and AMP output CXA3516R AMP RGB2 input selection Block D6 D4 D3 O D1 D2 D0 D5 1 Brightness CLP 0: ON 1: OFF 16 Function bit Register Name Control Range (typ.) Register No. D7 Data AMP Brightness clamp off SYNC SEP 2 SYNC SEP VHYS 17 SYNC SEP hysteresis level setting during SYNC ON GREEN 00: 2mV 01: 20mV 10: 45mV 11: 70mV 0000: 75mV 10mV step 1111: 215mV 17 O O 18 O O O O SYNC SEP 4 SYNC SEP VTH 0: all 1 all 0(NEGATIVE) DATA OUT POL 1: all 0 all 1(POSITIVE) 1 SYNC SEP threshold level setting during SYNC ON GREEN ADC ADC DATA output polarity control O ADC 3 DATA output mode switching DATA OUT MODE 18 000: Straight 001: DMUX Parallel 010: DMUX Interleaved 011: YUV4:2:2 D2 111: YUV4:2:2 Special 0: active 1: power save 19 19 19 19 0: active 1: power save 0: active 1: power save 0: active 1: power save O O O - 33 - 1 1 1 1 SYNC SEP Power Save PLL Power Save AMP Power Save ADC Power Save 2 TTLOUT CLP 00: 2.20V 01: 2.45V 10: 2.70V 11: 2.95V 19 ADC ADC power save O O O O AMP AMP power save PLL PLL power save SYNC SEP SYNC SEP power save TTLOUT TTLOUT CLP LEVEL O O CXA3516R Register Assignment Data Sub Address D2 D1 D0 VCODIV Bit0 38 (H) 0 0 0 0 0 VCODIV Bit8 15 (H) 0 1 Fine Delay Bit0 0 VCODIV Bit1 0 VCODIV Bit9 0 Fine Delay Bit1 0 VCODIV Bit2 0 VCODIV Bit10 1 Fine Delay Bit2 0 HEX code A4 A3 A2 A1 A0 HEX code D6 VCODIV Bit6 VCODIV Bit3 1 VCODIV Bit11 0 Fine Delay Bit3 0 0 DIV1, 2, 4, 8 Bit1 0 Fine Delay Bit5 1 DIVOUT DELAY 1 0 PD POL 1 DSYNC Hold 0 1/2CLK Enable 1 1 DSYNC By-pass 1 XCLK Enable 1 HOLD POL 1 CLP POL 1 1 SYNC OUT SW 1 1/2XCLK Enable 1 HSYNC1/2 0 SOG Enable 1 1 1 UNLOCK Enable DSYNC Enable 1 SYNCP/ HSYNC IN 1 SOGOUT POL SYNC IN POL 0 0 0 Fine Delay Bit4 1 DIV1, 2, 4, 8 Bit0 1 1 VCODIV Bit5 VCODIV Bit4 D5 D4 D3 Register No. Register Name D7 Register 0 VCODIV1 VCODIV Bit7 0 00 (H) Reference 0 0 Register 1 VCODIV2 0 0 1 01 (H) Reference Register 2 0 DELAY Coarse Delay Coarse Delay Bit0 Bit1 20 (H) 0 0 0 1 0 02 (H) Reference 0 PLL Register 3 CP DIVOUT Width DIVOUT Width Charge Pump Charge Pump Charge Pump Bit0 Bit1 Bit2 Bit1 Bit0 23 (H) 1 DSYNC POL 3F (H) 1 VCO By-pass 1B (H) 1 CLK Enable FF (H) 1 0 0 0 1 1 03 (H) Reference Register 4 POLARITY 0 0 1 0 0 04 (H) AMP - 34 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reference Register 5 SYNC 0 0 1 0 1 05 (H) Reference Register 6 TTLOUT ENABLE SEROUT Enable 0 0 1 1 0 06 (H) Reference 1 Register 7 MAIN CONTRAST Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Bit0 Bit4 Bit2 Bit5 Bit1 Bit6 Bit3 Bit7 80 (H) 0 0 0 0 1 1 1 07 (H) Reference 1 Register 8 SUB CONTRAST G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Sub Contrast G Bit0 Bit4 Bit2 Bit5 Bit1 Bit6 Bit3 Bit7 80 (H) 0 0 0 1 0 0 0 08 (H) Reference 1 Register 9 SUB CONTRAST B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Sub Contrast B Bit0 Bit4 Bit2 Bit5 Bit1 Bit6 Bit3 Bit7 80 (H) 0 0 0 1 0 0 1 09 (H) Reference 1 CXA3516R Register 10 SUB CONTRAST R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Sub Contrast R Bit0 Bit4 Bit2 Bit5 Bit1 Bit6 Bit3 Bit7 80 (H) 0 0 0 1 0 1 0 0A (H) Reference 1 Data D6 D4 D0 D3 D1 D5 D2 HEX code A4 A3 A2 A1 A0 HEX code Sub Address Register No. Register Name D7 SUB Register BRIGHTNESS G 11 Reference 0 1 0 1 1 0 0 Sub Brightness B Bit3 80 (H) 0 1 0 Sub Brightness R Bit2 Sub Brightness R Bit1 0 Cb Offset Bit1 0 Cr Offset Bit1 0 RGB Out Select 0 0 Cr Offset Bit0 0 YCbCr mode 0 1 0 1 DATA OUT MODE Bit0 0 TTLOUT CLP TTLOUT CLP Bit0 Bit1 1 1 Sync Sep Power Save 0 0 PLL Power Save 0 1 AMP Power Save 0 0 DATA OUT POL 1 ADC Power Save 30 (H) 0 1 0 0 1 1 03 (H) 1 0 0 1 0 0 0 0 1 00 (H) 1 0 0 0 0 20 (H) 0 1 1 1 1 Cb Offset Bit0 0 20 (H) 0 1 1 1 0 0 Cb Offset Bit2 0 Cr Offset Bit2 0 RGB In1/2 Select 0 Sub Brightness R 80 (H) Bit0 0 0 0 0 1 1 0 1 Sub Brightness B Bit2 Sub Brightness B Bit1 Sub Brightness B Bit0 1 Sub Brightness B Bit6 0 Sub Brightness R Bit6 0 0 Cb Offset Bit3 0 Cr Offset Bit3 0 Brightness CLP 0 Cb Offset Bit5 1 Cr Offset Bit5 1 0 Cr Offset Bit4 0 Cb Offset Bit4 0 0 Sub Brightness R Bit5 Sub Sub Brightness R Brightness R Bit4 Bit3 0 0 Sub Brightness B Bit5 Sub Brightness B Bit4 0 0 0 0 0 0 0 Sub Brightness G Bit7 Sub Brightness G Bit6 Sub Brightness G Bit5 Sub Brightness G Bit2 Sub Sub Brightness G Brightness G Bit4 Bit3 Sub Sub Brightness G Brightness G 80 (H) Bit0 Bit1 0B (H) 1 SUB Register BRIGHTNESS B 12 Reference Sub Brightness B Bit7 0C (H) 1 AMP SUB Register BRIGHTNESS R 13 Reference Sub Brightness R Bit7 0D (H) 1 Register 14 CbOFFSET 0E (H) Reference Register 15 CrOFFSET 0F (H) Reference SYNC SEP ADC POWER SAVE - 35 - 1 0 0 DATA OUT DATA OUT MODE MODE Bit1 Bit2 Register 16 AMP MODE 10 (H) Reference Register 17 SYNCSEP Sync Sep VTH Sync Sep VTH Sync Sep VTH Sync Sep VTH Sync Sep VHYS Sync Sep VHYS Bit0 Bit2 Bit0 Bit3 Bit1 Bit1 22 (H) 11 (H) Reference Register 18 OUTPUT MODE 12 (H) Reference Register 19 POWER SAVE 13 (H) Reference CXA3516R CXA3516R Description of Operation Control Register Programmable control can be performed for many functions of this IC. 1) Mode selection Both I2C bus and 3-wire bus mode can be supported, and either of these modes can be selected by the 3WIRE/I2C (Pin 13). 3WIRE/I2C pin voltage Setting mode 0V I2C (High) 1/2VCC I2C (Low) VCC (5V) 3-wire bus The pin threshold voltages are set at 1/3VCC and 2/3VCC. 2) Threshold voltage In I2C bus mode, both SDA (Pin 9) and SCL (Pin 10) are input. These input logic signals can have two threshold voltages by the 3-wire/I2C. These threshold voltages have the following hysteresis. SDA, SCL pin threshold voltages Threshold voltage (Low High) I2C (High) mode 1.95V Threshold voltage (Low High) I2C (Low) mode 1.65V Threshold voltage (High Low) 1.6V Threshold voltage (High Low) 1.3V In 3-wire bus mode, the threshold voltages of the logic signal input to the SDA, SCL and XSENABLE pins have the following hysteresis. SDA, SCL and XSENABLE pin threshold voltages Threshold voltage (Low High) 3-wire bus mode 1.65V Threshold voltage (High Low) 1.3V - 36 - CXA3516R 3-wire Bus Mode Various control can be performed by setting the internal control register values via the serial interface comprised of the three pins SDA (Pin 9), SCL (Pin 10) and XSENABLE (Pin 11). Data can be accepted when XSENABLE is low level. When XSENABLE is high level, data cannot be accepted. The SDA pins of multiple IC can also be connected to the same bus line and each IC can be controlled independently by XSENABLE. XSENABLE may change the state when SCL is high level. 1) Write mode 8-bit control data consisting of a 7-bit sub address and 1-bit READ/WRITE setting is input in series from the LSB to the SDA pin. When READ/WRITE setting is "1", data can be written to register. When this IC is used in 3-wire bus mode, the sub address is 5 bits, so always set the 2 MSB bits to "0". Input the clock to the SCL pin. Data is loaded to the SDA pin at the rising edge of this clock. The data is set in the register at the rising edge of XSENABLE. The SDA and SCL pins are also used in I2C bus control mode. TENPW XSENABLE SCL SDA A0 LSB SUB ADDRESS A1 A2 A3 A4 0 A5 0 A6 MSB 1 D0 LSB DATA D1 D2 D3 D4 D5 D6 D7 MSB READ/WRITE READ/WRITE 0: READ Mode 1: WRITE Mode TENS XSENABLE SCL SDA TDS TDH TENH Set the VCO post-stage frequency divider (DIV1, 2, 4, 8) and programmable counter (VCODIV) in the following order. The data is set when Register1 is sent. Register0 (SUB ADDRESS (H): 00) Register1 (SUB ADDRESS (H): 01) - 37 - CXA3516R 2) Read mode Input the 7-bit sub address and 1-bit READ/WRITE setting to the SDA pin. When READ/WRITE setting is "0", the 8-bit internally set data is output in series from the LSB by the SEROUT (Pin 12). While data is being output from the SEROUT pin, don't care what data is input to the SDA pin. Use the read function to check whether the data is set correctly inside the IC. TENPW XSENABLE SCL SDA SEROUT A0 LSB A1 A2 A3 A4 0 A5 0 A6 MSB D0 LSB SUB ADDRESS READ/WRITE READ/WRITE 0: READ Mode 1: WRITE Mode TENS XSENABLE SCL SDA SEROUT TDS TDH TD TENH DATA D1 D2 D3 D4 D5 D6 D7 MSB 0 The SEROUT pin is TTL output. When not using the READOUT function, the TTL output circuit can be turned off by control register. Register: SEROUT ENABLE SEROUT output status 0 1 Function off Function on Power-on Reset When the power supply rises, the power-on reset circuit operates and all the control register data is set to "1". AMP, ADC, PLL and SYNCSEP are all set to power save mode, and all the TTL output pins are set to high impedance mode. Therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes. - 38 - CXA3516R I2C BUS Mode Various control can be performed by setting the internal control register values via the serial interface comprised of the SDA (Pin 9) and SCL (Pin 10). This mode has only a write mode for setting data, and there is no read mode. Therefore, address "S0" set READ/WRITE is always "0". S7 SLAVE ADDRESS 1 S6 0 S5 0 S4 1 S3 1 S2 x S1 x S0 0 Four different kinds of slave address (IC address) can be set by externally setting the ADDRESS (Pin 2) to a specific voltage. ADDRESS pin voltage SLAVE ADDRESS 0V 1/3VCC 2/3VCC VCC (5V) 1001 1000 1001 1100 1001 1110 1001 1010 The pin threshold voltages are set to 1/4VCC, 1/2VCC and 3/4VCC. An 8-bit slave address (IC address), 8-bit sub address, and a number of 8-bit data strings are input in series from the MSB to the SDA pin. When this IC is used in I2C bus mode, sub address is 5 bits, and 3 bits of MSB side are set to always "0". ACK signal is returned from the IC to confirm that the data has been received for each 8-bit data. The sub address can be designated optionally. The sub address is auto-incremented in order from the designated sub address, and the data strings are loaded in succession. To set the data at a specific separated sub address, either send the stop condition and then reset the sub address, or also send the data of unchanged portions so that the data is continuous. Only auto-increment mode is supported, and the sub address + data + sub address + data mode where only specific sub addresses are designated is not supported. 0 0 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 SDA S7 S6 S5 S4 S3 S2 S1 S0 ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK A7 A6 A5 A4 A3 A2 A1 A0 SLAVE ADDRESS MSB LSB SCL SUB ADDRESS DATA DATA START CONDITION STOP CONDITION * START CONDITION When SCL pin is high level, the signal input to SDA pin has a falling edge, there is START CONDITION. * STOP CONDITION When SCL pin is high level, the signal input to SDA pin has a rising edge, there is STOP CONDITION. - 39 - CXA3516R I2C BUS Control Signals SDA TBUF TLOW TR_REG TF_REG THD;STA SCL P S THD;STA THD;DAT THIGH TSU;DAT Sr TSU;STA P TSU;STO Power-on Reset When the power supply rises, the power-on reset circuit operates and all the control register data are set to "1". AMP, ADC, PLL and SYNCSEP are all set to power save mode, and all the TTL output pins are set to high impedance mode. Therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes. - 40 - CXA3516R Amplifier This is a 3-channel AMP that optimizes the AC coupled RGB analog input signals and YCbCr analog input signals for ADC input. Switch input mode between RGB input or YCbCr input with the control register. The AC coupled analog input signals are synchronously clamped by the externally input clamp pulse at a pedestal level. An input capacitor of 0.1F is recommended. Allowing two lines of input to be selected for the analog input signal, the AMP includes a high frequency, low cross talk video switch circuit for input switching. Switching is performed using a control register. When using only one line, leave the unused line open. The input band of the analog input signal is 220MHz in the -3dB bandwidth range. There are main contrast and sub-contrast of the gain used to adjust the analog input signal to full scale (1V typ.) of the ADC. Each can be adjusted to one of 256 levels using control registers. Main contrast is controlled by moving the gain of the 3 RGB channels. The each gain of the 3 RGB channels can be controlled independently. In RGB input mode, the clamp level used for the black level adjustment can be adjusted independently for the 3 channels to any of 256 levels by using sub-brightness. The CLP pin1 is connected to the hold capacitor of the clamp circuit for the sub-brightness. A hold capacitor of 0.1F is recommended. The OUT pins2 can output signal immediately before input to the ADC or the signal after switching between the two lines of input select switch. Either of them can be selected by control register. As for emitter follower output, since the internal bias current is small, be sure to connect an 820 resistor between the OUT pins2 and AGND in order to view the signal with a high frequency. A 75 driver cannot be supported. In addition, load capacitance should be 5pF or less. When the SYNC ON GREEN signal is monitored at the OUT pins2 after the two lines of select switch, the sync amplitude is a maximum of 0.3V, for a limiter is applied at the amplifier input stage. In YCbCr signal input mode, Y can be adjusted to any of 256 levels using the sub-brightness while Cb and Cr can be adjusted to any of 64 levels using the Cb or Cr offset. A detailed description of the above registers is given below. 1 CLP pins: Overall naming for R/Cr CLP (Pin 130), G/Y CLP (Pin 128), B/Cb CLP (Pin 129) 2 OUT pins: Overall naming for R/Cr OUT (Pin 3), G/Y OUT (Pin 143), and B/Cb OUT (Pin 1) * Analog input signal mode switching Analog input signal supports both RGB analog input signal and YCbCr analog input signal. This register switches the clamp level of the input clamp block and the amplifier output block in each mode. However, the G/Ych perform the same processing in both RGB input mode and YCbCr input mode. Register: YCbCr mode Analog input signal mode 0 RGB input 1 YCbCr input * Input channel switching Input supports 2-channel input, and the input can be selected by an internal switch. Register: RGB In Select Analog input signal channel switching 0 IN1 1 IN2 * Clamp pulse input polarity The clamp pulse input polarity can be selected by an internal switch. Register: CLP POL Clamp pulse polarity 0 NEGATIVE - 41 - 1 POSITIVE CXA3516R * Brightness clamp off function Clamp operation can be set to a mode where only the post-stage brightness clamp does not operate even if a clamp pulse is input to the CLPIN (Pin 113). At this time, all three channels of the CLP pins1 are set to high impedance simultaneously, and the signal black level can be varied in an analog manner by setting the voltages externally. However, the voltage value set here is not related to the VRT (Pin 17) and VRB (Pin 93) voltages or the OUT2 monitor signal output DC levels. Therefore the value should be set while monitoring the ADC data output or the data after that. Register: Brightness CLP Clamp operation 0 Clamp operation 1 Clamp off * Monitor signal output selection The two monitor signal outputs (OUT pins2) of the amplifier can be selected by an internal switch. One is amplifier output signal immediately before input to the ADC, and other is after switching between the two lines of select switch. Register: RGB Out select Monitor output switching 0 1 Amplifier output Switch output * Main contrast The RGB channel gains can be set collectively by an 8-bit DAC setting. Register: MAIN CONTRAST Amplifier gain (typ.) SUB CONTRAST = 128 0 0.78 *** *** 128 1.53 *** *** 255 2.24 * Rch sub contrast The Rch contrast (R amplifier gain) can be adjusted independently within the range of 21% relative to the main contrast by an 8-bit DAC setting. Register: SUB CONTRAST R Rch gain adjustment (typ.) 0 -21% *** *** 128 0% *** *** 255 +21% * Gch sub contrast The Gch contrast (G amplifier gain) can be adjusted independently within the range of 21% relative to the main contrast by an 8-bit DAC setting. Register: SUB CONTRAST G Gch gain adjustment (typ.) 0 -21% *** *** 128 0% *** *** 255 +21% * Bch sub contrast The Bch contrast (B amplifier gain) can be adjusted independently within the range of 21% relative to the main contrast by an 8-bit DAC setting. Register: SUB CONTRAST B Bch gain adjustment (typ.) 0 -21% *** *** - 42 - 128 0% *** *** 255 +21% CXA3516R * Rch sub brightness in RGB mode The Rch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Rch sub brightness can be varied within the range of 25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V). Register: SUB BRIGHTNESS R Level shift amount (typ.) Register: YCbCr mode Input signal mode 0 -61LSB 0 RGB *** *** 128 0LSB *** *** 255 +61LSB * Gch sub brightness in RGB mode The Gch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Gch sub brightness can be varied within the range of 25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V). Register: SUB BRIGHTNESS G Level shift amount (typ.) Register: YCbCr mode Input signal mode 0 -61LSB 0 RGB *** *** 128 0LSB *** *** 255 +61LSB * Bch sub brightness in RGB mode The Bch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Bch sub brightness can be varied within the range of 25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V). Register: SUB BRIGHTNESS B Level shift amount (typ.) Register: YCbCr mode Input signal mode 0 -61LSB 0 RGB *** *** 128 0LSB *** *** 255 +61LSB * Cbch black level shift in YCbCr mode The Cbch black level voltage can be set by a 6-bit DAC during YCbCr signal input. The Cbch black level voltage can be varied within the range of 16LSB centering on the ADC input dynamic range center ((VRT + VRB)/2). Register: Cb Offset Level shift amount (typ.) Register: YCbCr mode Input signal mode 0 112LSB 1 YCbCr *** *** 32 128LSB *** *** 63 144LSB * Crch black level shift in YCbCr mode The Crch black level voltage can be set by a 6-bit DAC during YCbCr signal input. The Crch black level voltage can be varied within the range of 16LSB centering on the ADC input dynamic range center ((VRT + VRB)/2). Register: Cr Offset Level shift amount (typ.) Register: YCbCr mode Input signal mode 0 112LSB 1 YCbCr - 43 - *** *** 32 128LSB *** *** 63 144LSB CXA3516R * Input signal connection method Input Pin No. Pin 124 Pin 126 Pin 133 Pin 136 Pin 139 Pin 141 Symbol G/YIN1 G/YIN2 B/CbIN1 B/CbIN2 R/CrIN1 R/CrIN2 Pin No. Output Symbol 68 to 75 GA0 to GA7 78, 81 to 85, 87, 88 GB0 to GB7 45 to 49, 51 to 53 56 to 58, 60 to 64 BA0 to BA7 BB0 to BB7 21, 22, 24 to 28, 31 RA0 to RA7 34 to 41 RB0 to RB7 1. When inputting both RGB and YCbCr, input according to the table above. 2. SYNCSEP is connected to G/YIN. 3. When inputting RGB and not using SYNCSEP, there is no difference between the three channels so the input order may be optional. 4. When inputting Y, Cb and Cr, be sure to input according to the table above. It is possible for only the R/Cr IN and B/Cb IN pins to be clamped to the center of the ADC input dynamic range. - 44 - CXA3516R SYNCSEP The SYNCSEP function can be used to separate and output the SYNC signal that is superimposed on the SYNC ON GREEN signal (including the SYNC ON Y signal). There are two major SYNCSEP circuits. One is the circuit for creating a SYNC signal to be input to the PLL, and the other is a circuit for outputting a SYNC signal from the SOGOUT (Pin 105) so that a clamp pulse can be created externally. These SYNCSEP circuits perform processing on entirely different channels. (See the block diagram for the SYNCSEP operational description.) * SYNCSEP circuit for the PLL SYNC signal In the case of the SYNC ON GREEN signal, the SYNC ON GREEN signal is AC coupled to the G/YIN1 (Pin 124) or the G/YIN2 (Pin 126) and the sync component is separated and used as a reference. An input capacitor of 0.1F is recommended. When a signal is input to this pin, the pedestal level is clamped by a clamp pulse input to the CLPIN (Pin 113). After this, the signal is split into a signal to the amplifier circuit and the signal to the SYNCSEP circuits, and the SYNC signal is sent through a two lines of input select switch (SW SOGP) and the SYNC signal is separated by the SYNCSEP circuits. At this time, it is possible to minimize the jitter of the SYNC signal sent to the PLL by using a control register to select the threshold level (VTH) and hysteresis level (VHYS) of the SYNCSEP circuit according to the type of noise on the superimposed SYNC signal. SOG SYNC SEP threshold (Versus pedestal level) Register: SYNC SEP VTH Threshold SOG SYNC SEP hysteresis Register: SYNC SEP VHYS Hysteresis 00 2mV 01 20mV 10 45mV 11 70mV 0000 75mV *** 9.3mV step 1111 215mV VTH VHYS SYNC signal Pedestal level The SYNC signal separated by the SYNCSEP circuits can be switched at the SW PLL circuit with an externally input SYNC signal (the SYNC signal input from the SYNCIN1 or SYNCIN2 pin) by using control registers (SYNCP/HSYNC). The selected signal is input to the PLL block. Selecting between the sync separated SYNC signal and the externally input SYNC signal Register: SYNCP/HSYNC IN SYNC signal type SYNC signal input pin 0 Sync separated signal G/YIN1 pin G/YIN2 pin 1 Externally input SYNC signal SYNCIN1 pin SYNCIN2 pin - 45 - CXA3516R * SYNCSEP circuits for the SYNC signal for the clamp pulse A SYNC ON GREEN signal is input to the SOGIN1 (Pin 132) or SOGIN2 (Pin 135). The AC coupled signal is internally sync tip clamped and the minimum level (bottom of sync) is turned into the internally-set DC level (approximately 2.8V). The sync tip clamped input signal is separated from the threshold of 165mV (at SYNC DUTY 5%) above from the bottom of the sync by the SYNCSEP circuit. After this, the signal is output at TTL level from the SOGOUT pin and used as a reference signal for generating a clamp pulse. Since no clamp pulse is required for the sync tip clamp, it is possible to output a SYNC signal from the SOGOUT pin even when there is no external clamp pulse present such as when power supply is turned on. An input capacitor of 0.1F is recommended. A control register can be used to select output either the SYNC signal separated out from the signal input from the SOGIN1 pin or the SOGIN2 pin by SW SOG O or the previously described PLL SYNC signal output from the SW PLL circuit. Output from the SOGOUT pin SYNCT1, SYNCT2/SYNCP1, SYNCP2/SYNCIN1, SYNCIN2 output selection SYNCT1, SYNCT2: The SYNC signal sync tip clamped and separated from the SOGIN1 and SOGIN2 pins SYNCP1, SYNCP2: The SYNC signal pedestal clamped and separated from the G/YIN1 and G/YIN2 pins SYNCIN1, SYNCIN2: The SYNC signal input from the SYNCIN1 and SYNCIN2 pins Register: SYNC OUT SW 0 1 Output from the SOGOUT pin SYNCT1, SYNCT2 SYNCP1, SYNCP2 or SYNCIN1, SYNCIN2 The SOGIN1, SOGIN2 and the previously described G/YIN1, G/YIN2 are interlocked as for the 2-ch selection (Register: RGB In Select). Input channel selection Register: RGB In Select G/YIN pin selection SOGIN pin selection 0 IN1 IN1 1 IN2 IN2 The polarity of signals output from the SOGOUT pin can be set by using registers. Register: SOGOUT POL SOGOUT output polarity 0 Negative 1 Positive * SYNC ON GREEN output enable When the SOGOUT pin is not used, it is possible to turn off the TTL output using a control register. But it cannot be set to high impedance. Register: SOG Enable SOGOUT output status 0 Off 1 On - 46 - CXA3516R PLL * SYNC signal input The SYNC (HSYNC) used by the PLL is input from the SYNC signal input pins. There are two sets of input pins, SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112), which are switched by the control register. SYNCIN1 input, SYNCIN2 input switching Register: HSYNC1/2 SYNC signal input pin 0 SYNCIN1 1 SYNCIN2 SYNC signals within the range from 10kHz to 130kHz can be input. The input supports both positive and negative polarity. SYNC signal input polarity Register: SYNC POL SYNC signal input polarity 0 Negative 1 Positive Set the register in accordance with the polarity of the externally input SYNC. When SYNC is positive polarity, set SYNC POL to "1". (Clock is generated in sync with the rising edge of SYNC.) When SYNC is negative polarity, set SYNC POL to "0". (Clock is generated in sync with the falling edge of SYNC.) When there is no SYNC input, the VCO oscillates at random and a random pulse is output from the CLK output. LPF A DIV 1, 2, 4 ,8 B SYNC signal PD CP VCO Programmable counter Point A: VCO oscillation frequency Point B: Clock frequency * Phase detector (PD) The phase detector compares the phase of the SYNC signal with that of the programmable counter output signal. The phase comparison is performed at the edge, and a phase difference between the compared signals is output as a pulse. There is no hysteresis function for the input pins of the SYNC signal (SYNCIN1 and SYNCIN2) input to the phase detector. If necessary external waveform shaping should be done as jitter results when a noisy signal is input. Set the control register, PD POL, to "1" as for the input polarity of the phase detector. * Hold function The hold function holds the VCO input voltage and generates oscillation itself without performing phase comparison. The VCO oscillation frequency is held during this period without performing phase comparison, by inputting the HOLD signal from the HOLD (Pin 106). HOLD signal polarity can be set by using the control register: HOLD POL. Register: HOLD POL HOLD signal input polarity 0 Held while HOLD signal is Low 1 Held while HOLD signal is High For details, see the hold timing diagram. - 47 - CXA3516R * Charge pump (CP) The charge pump sets charge pump current to flow for the amount of time corresponding to the pulse width output from the phase detector. The phase detector gain is determined by the charge pump current. The amount of current can be varied by using a control register. This IC is used to set the charge pump current value according to the VCO oscillation frequency as given below. [CP Setting Matrix] VCO oscillation frequency: 40MHz to 85MHz: 85MHz to 110MHz: 110MHz to 140MHz: 140MHz to 155MHz: 155MHz to 165MHz: CP setting values 200A 300A 400A 500A 600A The VCO oscillation frequency is that at the Point A in the diagram. Register: Charge Pump Bit2 Register: Charge Pump Bit1 Register: Charge Pump Bit0 Charge pump current 0 0 0 100A 0 0 1 200A 0 1 0 300A 0 1 1 400A 1 0 0 500A 1 0 1 600A 1 1 0 700A 1 1 1 800A * Loop filter (LPF) The control voltage input to the VCO is the pulse current output from the charge pump circuit that is smoothed by an integrating circuit (loop filter). The resistor and capacitor values of the integrating circuit are as follows. (For the circuit configuration, see the application circuit.) C1 = 0.33F C2 = 330pF R1 = 3.3k For the resistor and capacitors, use a metal film chip resistor with little temperature variation and ceramic chip capacitors. In particular, the 0.33F capacitor should be equivalent to high dielectric constant series capacitor type B or better. (Electrostatic capacitance change ratio 10%: T = -25 to +85C) In case of using any resistors or capacitors except those given above, it is not guaranteed. * VCO The VCO oscillation frequency range covers from 40MHz to 165MHz. - 48 - CXA3516R * VCO frequency dividers (DIV 1, 2, 4, 8) The oscillation frequency of the VCO can be divided to 1/1, 1/2, 1/4, or 1/8 according to a control register setting. Depending on the combination of the VCO oscillation frequency and VCO frequency divider, the Point B clock frequency covers an operating range of 5MHz to 165MHz. The matrix of the VCO frequency divider setting is as follows. [VCO Frequency Divider Setting Matrix] Clock frequency: DIV setting value 5MHz to 14MHz: 1/8 14MHz to 40MHz: 1/4 40MHz to 80MHz: 1/2 80MHz to 120MHz: 1/1 Register: DIV 1, 2, 4, 8 Bit1 Register: DIV 1, 2, 4, 8 Bit0 Counter frequency 0 0 1/1 0 1 1/2 1 0 1/4 1 1 1/8 * Programmable counter The clock frequency at Point B is divided and a programmable counter output signal is generated. The frequency division ratio can be set optionally by using a 12-bit control register. This is determined by using lower order 3 bits and upper order 9 bits in the following formula. Frequency division ratio = (m + 1) x 8 + n m: 9 bits (VCO DIV Bit 3 to 11) n: 3 bits (VCO DIV Bit 0 to 2) Register No. Register 0 Register 1 Register Name VCODIV1 VCODIV2 Data7 MSB m4 Data6 m3 Data5 m2 Data4 m1 Data3 m0 m8 Data2 n2 m7 Data1 n1 m6 Data0 LSB n0 m5 After the set value for the frequency division ratio is changed, that set value is loaded into the programmable counter when the output value of the programmable counter becomes "all 0". * Clock output When the input polarity of the SYNC signal is positive, the clock output is synchronized to the rising edge of the SYNC signal and is available as complementary signals CLK (Pin 99) and XCLK (Pin 98). The delay time of the clock output can be varied in the range of 1/32CLK to 64/32CLK by using a control register (see PLL timing diagram). Although the clock output can be turned off independently by using a control register, it cannot be set to high impedance. The operational frequency of the clock is up to 100MHz. Register: CLK Enable, XCLK Enable Clock output status 0 Off 1 On - 49 - CXA3516R * 1/2 clock output 1/2 clock signal is a signal that resets the clock by using a reset pulse created from an internal delay sync signal and divides the clock in half. The complementary signal is output from the 1/2CLK (Pin 101) and 1/2XCLK (Pin 100). (See the PLL timing diagram). Although the 1/2 clock output can also be independently turned off by the control register, it cannot be set to high impedance. Register: 1/2CLK Enable, 1/2XCLK Enable 1/2 Clock Output Status 0 Off 1 On * Delay sync output Two types of delay sync signal (DSYNC and DIVOUT) can be output from the DSYNC/DIVOUT (Pin 103). This is selected by switching a control register. The DSYNC signal is output as the input SYNC signal undergone timing control. The DIVOUT signal is output as the programmable counter output undergone timing control. Both can be used as reset signals for any connected IC such as a scaling IC. Delay sync output signal (DSYNC/DIVOUT (Pin 103)) Register: DSYNC By-pass Signal output from the DSYNC/DIVOUT pin 0 1 DIVOUT signal DSYNC signal * DSYNC signal A SYNC signal input that has been timing controlled by a clock generated by a PLL is output. Although only the forward edge is completely managed at this time with delay settings, etc., the back edge has an undefined width for one clock cycle because it latches and outputs the input SYNC signal. * DIVOUT signal A timing controlled programmable counter output signal is output. In addition to the COARSE DELAY that has been set by using the DSYNC signal, the delay time setting is output with a delay of 4 or 5 clocks. The pulse width is also managed by a clock. [Function Correspondence Table for the DSYNC Signal/DIVOUT Signal] Function COARSE DELAY FINE DELAY Pulse width DIVOUT DELAY Output polarity Output enable Output during HOLD DSYNC signal 3CLK to 6CLK 1/32CLK to 64/32CLK Fixed (depends on input SYNC signal width) -- On/Off On/Off On/Off DIVOUT signal 3CLK to 6CLK 1/32CLK to 64/32CLK 1, 2, 4, 8CLK 4, 5CLK On/Off On/Off On/Off Register COARSE DELAY FINE DELAY DIVOUT WIDTH DIVOUT DELAY DSYNC POL DSYNC Enable DSYNC Hold - 50 - CXA3516R * Delay time setting (Fine Delay/Coarse Delay) The delay sync output, clock output, and 1/2 clock output can make delay time setting (Fine Delay/Coarse Delay) for the input signal. The amount of delay time is from 3CLK Delay to 6CLK Delay for Coarse Delay and from 1/32CLK to 64/32CLK for Fine Delay. The delay time (Fine Delay/Coarse Delay) can be set by using the control registers shown below. Register: FINE DELAY Delay time Register: COARSE DELAY Delay time 000000 1/32CLK 00 3CLK 000001 2/32CLK 01 4CLK ********** ********** 10 5CLK 11 6CLK 111111 64/32CLK * DIVOUT signal output pulse width The pulse width of the DIVOUT signal output can be set to 1, 2, 4, 8 clock pulse widths by using a control register. Register: DIVOUT WIDTH DSYNC signal width 00 1CLK 01 2CLK 10 4CLK 11 8CLK * DIVOUT signal output delay time setting The DIVOUT signal is output with 4 or 5 clock delay based on the delay time (Fine Delay/ Coarse Delay) set as described above. The clock delay time can be set by using a control register. Register: DIVOUT DELAY Delay time 0 4CLK 1 5CLK * Delay sync output polarity The polarity of the delay sync signal output from the DSYNC/DIVOUT pin can be selected either negative or positive by using a control register. Register: DSYNC POL Delay sync output polarity 0 Negative 1 Positive * Delay sync output status Although it is possible to turn off the signal output from the DSYNC/DIVOUT pin by using a control register, it cannot be set to high impedance. Register: DSYNC Enable Delay sync output status 0 Off 1 On - 51 - CXA3516R * Delay sync output status during hold Register: The delay sync output during the hold period can be controlled with the DSYNC Hold register and the HOLD signal. Register: DSYNC Hold Delay sync output status 0 Using HOLD signal logic 1 DSYNC signal/DIVOUT signal The output status resulting from this setting differs based on status of the DSYNC By-pass register. HOLD signal logic (When HOLD POL register = 1) H L H L H L H L Register: DSYNC Hold 0 0 0 0 1 1 1 1 Register: DSYNC By-pass 0 0 1 1 0 0 1 1 Delay sync output L DIVOUT signal L DSYNC signal DIVOUT signal DIVOUT signal DSYNC signal DSYNC signal The values given in the above table are for when the DSYNC POL register is set to "1". The delay sync output status is reversed when DSYNC POL is set to "0". * XTLOAD signal (reset signal) This input pin forces to reset the divider function of the programmable counter. Since this signal is not normally used, leave it open or fix to high level. When it is used, this signal is in conjunction with the HOLD signal. See the note given later regarding the combined use of these signals. XTLOAD pin Programmable counter status L Forcible reset H Count - 52 - CXA3516R Register: The DSYNC Hold register and HOLD signal can be used to control the delay sync output during the hold period. The relationship between the delay sync output and the SYNC signal is shown below. (For each of CASE 1 to 3, the DSYNC POL register is "1". In addition, the DSYNC signal output and DIVOUT signal output can be switched by using the DSYNC By-pass register.) CASE 1 SYNC signal (SYNC POL = 1) HOLD signal (1) DSYNC Hold = 1 DSYNC signal DIVOUT signal (2) DSYNC Hold = 0 DSYNC signal DIVOUT signal - 53 - CXA3516R CASE 2 SYNC signal (SYNC POL = 1) HOLD signal (1) DSYNC Hold = 1 DSYNC signal DIVOUT signal (2) DSYNC Hold = 0 DSYNC signal DIVOUT signal - 54 - CXA3516R CASE 3 SYNC signal (SYNC POL = 1) HOLD signal (1) DSYNC Hold = 1 DSYNC signal DIVOUT signal (2) DSYNC Hold = 0 DSYNC signal DIVOUT signal - 55 - CXA3516R Notes on Using the HOLD Signal and XTLOAD Signal (Reset Signal) If the cycle of the SYNC signal is lost, the phase difference between the SYNC signal and the programmable counter output in the phase detector will increase, and it will cause PLL unlock. At this time, the HOLD signal is input to the HOLD (Pin 106), phase comparison is stopped while the signal is high level (when the HOLD POL register is set to "1"), and the clock can be stably oscillated by holding the VCO oscillation frequency. Note, however, the correspondence differs depending on whether the number of locations where the SYNC signal period changes (the 0.5H region in the diagram) is odd or even. LPF SYNC signal PD CP VCO DIV 1, 2, 4, 8 Clock output Programmable counter Case 1: When the 0.5H region is even (correspondence with HOLD signal only) SYNC signal (SYNC POL = 0) H Programmable counter output signal HOLD signal H 1 2 3 4 0.5H 0.5H 0.5H 0.5H H H When the number of the 0.5H period is even, it is possible to hold the period of the programmable counter output stable by applying the HOLD signal before the frequency changes. This corresponds to the vertical blanking period of the composite sync (computer signal). Case 2: When the 0.5H region is odd (correspondence with HOLD signal + XTLOAD signal (reset signal)) SYNC signal (SYNC POL = 0) H Programmable counter output signal HOLD signal 8CLK XTLOAD signal (reset signal) Tw (min) = 100ns "HSYNC" and "XTLOAD" are synchronized 1 2 3 0.5H 0.5H 0.5H H H H H When the number of the 0.5H period is odd, if only the HOLD signal is used, the phase difference between the SYNC signal and the programmable counter output signal will increase in the extra 0.5H region and the lock will be lost momentarily. In this case, the 0.5H region is held by the HOLD signal, and it is possible to use the XTLOAD signal (reset signal) at 1H backward to the official counter period by resetting/setting the counter value. Although there are no particular restrictions on the setup time and hold time of the XTLOAD signal (reset signal), the pulse width of the XTLOAD signal (reset signal) is restricted while the HOLD signal is high. (When the HOLD POL register is set to "1".) If the rising edge of the XTLOAD signal (reset signal) is delayed by 8CLK from the falling edge of the SYNC signal, counter output will be obtained by synchronizing with the falling edge of the next SYNC signal. See the diagram for details on timing. - 56 - CXA3516R * HOLD signal timing SYNC signal (when SYNC POL = 1) SYNC signal (when SYNC POL = 0) DIVOUT signal (when DSYNC POL = 0) Thh HOLD signal (when HOLD POL = 1) Ths Thold VCO oscillation frequency is held without performing phase comparison. Clock output Thh Ths The HOLD signal setup time (Ths) is the time from the rising edge of the HOLD signal to the falling edge of the DIVOUT signal. The HOLD signal hold time (Thh) is the time from the falling edge of the DIVOUT signal to the rising edge of the HOLD signal. See the above timing diagram for details on the relationship with SYNC POL. The frequency variation of CLK while held can be calculated as given below. V I +Q C -Q SW VCO Ileak SW I f C * V = Q = Ileak * Thold C: Loop filter capacitance V: Varying voltage due to leak current Ileak: Leak current of the internal amplifier Thold: Hold time V = Ileak * Thold/C f = V * KVCO = Ileak * Thold/C * KVCO For example, Assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33F, KVCO = 2 * 55 [MHz/V], V = 1 * 10-9 * 1 * 10-3/(0.1 * 10-6) = 3 * 10-6 [V] f = 1 * 10-9 * 1 * 10-3/(0.1 * 10-6) * 2 * 70 * 106 = 1050 [Hz] - 57 - CXA3516R * UNLOCK timing If the phase difference between the SYNC signal input and the programmable counter output signal to the phase detector (PD) increases, it becomes impossible for the VCO to maintain stable oscillation. This status is converted into the UNLOCK signal and output. It is possible to perform analog lock/unlock by connecting an external circuit to this pin. IC internal Vcc R3 50k 104 Signal from the phase detector UNLOCK detect S1 signal Q1 IC external I2 R1 R2 S2 signal I1 C1 UNLOCK signal Vcc R1 = 100 R2 = 100k C1 = 0.01F The UNLOCK output is an open collector. By connecting the external circuit shown above to this output pin, it is possible to adjust the sensitivity of the S2 signal by varying the constants R1, R2 and C1. (The constants R1, R2 and C1 above are reference values. The resistor R3 should be 50k and Q1 should be 2SC series. The operations of the three cases are described below. Case 1: When there is no phase difference (PLL locked status) The S1 signal is low and the S2 signal is high. The UNLOCK signal is low. H S1 signal L H S2 signal L H UNLOCK signal L Threshold level of the inverter Case 2: When there is a phase difference, the S1 signal will goes low and high as shown in the figure below. At this time, the falling edge slew rate of the S2 signal is determined by the current I1 flowing into this open collector. The falling edge slew rate of the S2 signal will therefore be delayed as resistor R1 increases. In addition, since the rising edge slew rate of the S2 signal is determined by the current I2, the rising edge slew rate of the S2 signal will become faster as the resistor R2 decreases. If the integrated S2 signal does not fall below the threshold level of the next inverter, the UNLOCK signal will remain low. This will therefore be judged as locked even if there is a phase difference. H S1 signal L H S2 signal L H UNLOCK signal L Threshold level of the inverter Case 3: However, even if the same phase difference as described above is assumed, the decreasing resistor R1 will increase the current I1 flowing into the open collector. The falling edge slew rate of the S2 signal will therefore become faster. In addition, if resistor R2 is increased, the rising edge slew rate of the S2 signal will become slower. If the integrated S2 signal is under the threshold level of the next inverter, the UNLOCK signal will go from low to high and the PLL will be judged as unlocked. H S1 signal L H S2 signal L H UNLOCK signal L Threshold level of the inverter - 58 - CXA3516R The CXA3516R's charge pump is a constant-current output type as shown below. VCC S1 To LPF S2 When a constant-current output charge pump circuit is used inside the PLL, the phase detector (PD) output acts as a current source, and the dimension of its transmittance KPD is A/rad. Also, when considering the VCO input as a voltage, the LPF transmittance dimension must be expressed in ohms ( = V/A). Therefore, the PLL transmittance when a constant-current output charge pump circuit is used is as follows. PD r 1/S r + - o N KPD (A/rad) LPF F (S) () VCO KVCO (rad/S/V) 0 counter 1/N /N 0 1/S The PLL closed loop transmittance is obtained by the following formula. o/N r = KPD * F (S) * KVCO * 1/N * 1/S 1 + KPD * F (S) * KVCO * 1/N * 1/S ...(1) Here, KPD, F(S) and KVCO are: KPD: Phase comparator gain (A/rad) F(S): Loop filter transmittance () KVCO: VCO gain (rad/s/V) 1 The reason for the 1/S inside the phase detector is as follows. t o (t)/N = o 0 (t)/Ndt + o (t = 0)/N: (a) o (t = 0) = 0 t o (t)/N = o 0 (t)/Ndt: (b) Performing Laplace conversion: 1 o (S)/N = s W0 (S)/N: (c) - 59 - CXA3516R The loop filter F(S) is described below. The loop filter smoothes the output pulse from the phase detector (PD) and inputs it as the DC component to the VCO. In addition to this, however, the loop filter also functions as an important element in determining the PLL response characteristics. Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3516R's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants. Current input type active filter C ii -A -Vo -1 Vo R The filter transmittance is as follows. Vo 1 + Vo = (R + ) * ii A SC 1 + SRC A * SC 1+A 1 + S SC = RC A 1+A The Bode diagram for formula (2) is as follows. Gain [dB] log scale F (S) = 1 = * log log 0 Phase [deg] Here, assuming A > 1, then: F (S) = 1 + S SC ........................(2) -45deg -90 Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL: KPD * KVCO * NC = S2 + *S+ KPD * KVCO NC o/N r KPD * KVCO * NC ...(3) KPD * KVCO *S+ NC = 2nS + n2 S2 + 2nS + n2 .................................................(4) n = KPD * KVCO NC 1 2 .................................................(5) = n .....................................................................(6) - 60 - CXA3516R Here, n and are as follows. n characteristic angular frequency: The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency: n. damping factor: This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is determined by the loop gain and the loop filter. A capacitor C2 is added to the actual loop filter. This added capacitor C2 is used to reduce the R noise, and a value of around 1/10 to 1/1000 of C1 should be selected as necessary. Current input type active filter with added capacitor C2 C2 C1 ii -A -Vo -1 Vo R The filter transmittance is as follows. F (S) = 1 + C1 * R * S S ((C1 + C2) + C1 * C2 * R * S) 1 + 1 * S S (C1 + C2) (1 + 2 * S) The Bode diagram for formula (3) is as follows. Gain [dB] log scale = ...................(3) 1 1 1 2 1 = C1 * R 2 = C1 * C2 * R C1 + C2 0 Phase [deg] log log -45deg Here, assuming C2 = C1/100, then: 2 = = = C1 * C1/100 * R C1 + C1/100 1 C1 * R 101 1 1 101 -90 - 61 - CXA3516R Next, the various parameters inside an actual CXA3516R are obtained. The CXA3516R's charge pump output block and the LPF circuit are as follows. C2 R1 C1 118 VCC 100A to 100A step 800A 100A to 100A step 800A S2 333 119 CXA3516R S1 To VCO 20k 100 First, KPD is as follows. KPD = 100/2 or 200/2 or 300/2 or 400/2 or 500/2 or 600/2 or 700/2 or 800/2 (A/rad) Typical KVCO characteristics curves for the CXA3516R's internal VCO are as follows. 200 VCO DIV = 1/1 VCO frequency [MHz] 150 VCO DIV = 1/2 100 VCO DIV = 1/4 50 VCO DIV = 1/8 2 3 VCO input voltage [V] 4 Therefore, KVCO is as follows. KVCO = 2 * 55 or 2 * 27.5 or 2 * 13.75 or 2 * 6.875 (rad/s/V) - 62 - CXA3516R n and calculated for various types of computer signals are shown below. Here, the various parameters are as follows. FSYNC: Input sync frequency, FCLK: Output clock frequency KPD x 2: Phase comparator gain x 2 (KPD x 2 = 100 or 200 or 300 or 400 or 500 or 600 or 700 or 800) KVCO/2: VCO gain (when VCO DIV = 1/1, KVCO/2 = 55) (when VCO DIV = 1/2, KVCO/2 = 55/2) (when VCO DIV = 1/4, KVCO/2 = 55/4) (when VCO DIV = 1/8, KVCO/2 = 55/8) N: Counter value, C1: Loop filter capacitance value, R1: Loop filter resistance value MODE Resolution FSYNC FCLK KPD x 2 kHz NTSC NTSC NTSC NTSC PAL PAL PAL PAL 480p 1080i 720p VGA MAC 15.73 15.73 15.73 15.73 15.63 15.63 15.63 15.63 31.47 33.75 45.00 640 x 480 31.47 640 x 480 35.00 MHz 12.27 18.41 24.55 27.00 14.69 22.03 29.38 27.00 72.00 74.25 74.25 21.05 25.18 30.24 31.50 36.00 40.00 49.51 50.00 56.25 57.28 65.00 75.01 78.75 80.00 94.50 78.75 A 300 200 300 300 200 300 400 300 500 500 500 200 300 400 400 500 600 300 300 400 400 400 500 600 600 300 600 300 400 600 600 C.Pump setting KVCO DIV N 1, 2, 4, 8 C1 /2 setting setting F 780 n VCO oscillation frequency MHz 1.54 98.18 1.45 73.64 1.54 98.18 1.47 108.00 1.62 58.75 1.62 88.13 1.62 117.50 1.46 108.00 2.32 144.01 2.37 148.50 2.74 148.50 1.71 84.19 2.15 100.70 2.39 120.96 2.44 126.00 2.46 144.02 2.65 160.01 2.65 99.01 2.67 100.01 3.07 112.49 2.93 114.55 2.71 129.99 3.05 150.01 3.36 157.49 3.34 160.00 3.28 94.50 2.96 157.49 2.96 108.00 3.42 135.01 4.15 156.96 3.70 162.00 R1 fn bit2 bit1 bit0 M/(SV) bit1 bit0 k kHzrad kHz 2.83 2.67 2.83 2.70 2.98 2.98 2.98 2.69 4.27 4.35 5.03 3.13 3.95 4.39 4.48 4.51 4.87 4.87 4.90 5.64 5.38 4.98 5.60 6.17 6.14 6.03 5.43 5.44 6.28 7.62 6.80 0.45 0.42 0.45 0.43 0.47 0.47 0.47 0.43 0.68 0.69 0.80 0.50 0.63 0.70 0.71 0.72 0.77 0.77 0.78 0.90 0.86 0.79 0.89 0.98 0.98 0.96 0.86 0.87 1.00 1.21 1.08 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 55/8 55/4 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/1 55/2 55/1 55/1 55/1 55/1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0.33 3.3 1170 0.33 3.3 1560 0.33 3.3 1716 0.33 3.3 940 0.33 3.3 1410 0.33 3.3 1880 0.33 3.3 1728 0.33 3.3 2288 0.33 3.3 2200 0.33 3.3 1650 0.33 3.3 848 800 864 832 0.33 3.3 0.33 3.3 0.33 3.3 0.33 3.3 PC-98 640 x 400 24.82 VESA 640 x 480 37.86 SVGA 800 x 600 35.16 SVGA 800 x 600 37.88 SVGA 800 x 600 46.88 SVGA 800 x 600 48.08 SVGA 800 x 600 53.67 MAC XGA XGA XGA XGA 832 x 624 49.72 1024 x 768 48.36 1024 x 768 56.48 1024 x 768 60.02 1024 x 768 68.68 1024 0.33 3.3 1056 0.33 3.3 1056 0.33 3.3 1040 0.33 3.3 1048 0.33 3.3 1152 0.33 3.3 1344 0.33 3.3 1328 0.33 3.3 1312 0.33 3.3 1328 0.33 3.3 1376 0.33 3.3 1696 0.33 3.3 1688 0.33 3.3 1688 0.33 3.3 1722 0.33 3.3 2160 0.33 3.3 MAC 1024 x 768 60.24 SXGA 1280 x 1024 46.43 SXGA 1280 x 1024 63.98 108.00 SXGA 1280 x 1024 79.98 135.01 SXGA 1280 x 1024 91.15 156.96 UXGA 1600 x 1200 75.00 162.00 * DIV setting matrix * CP setting matrix Output oscillation frequency: DIV setting value Internal VCO oscillation frequency: CP setting value 5MHz to 14MHz: 1/8 40MHz to 85MHz: 200A 14MHz to 40MHz: 1/4 85MHz to 110MHz: 300A 40MHz to 80MHz: 1/2 110MHz to 140MHz: 400A 80MHz to 165MHz: 1/1 140MHz to 155MHz: 500A - 63 - 155MHz to 165MHz: 600A CXA3516R CLK Jitter Evaluation Method The generated CLK is obtained by inputting Hsync to the CXA3516R. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger. trigger Digital oscilloscope ch1 Pulse generator Hsync signal CXA3516R Clock H Back sync porch Active video Front porch Computer signal 15 to 25% of Tsync Hsync signal Tsync = 1/fsync Clock Trigger Enlarge Enlarge Enlarge Enlarge Clock Tj p-p The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync. Therefore, when the observation point is changed, the CLK jitter at that point is observed. The figure below shows a typical example of the CLK jitter for the CXA3516R. The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has passed from the rising edge of Hsync. Jitter amount Tj p-p 0 1/4 * Tsync 2/4 * Tsync Observation points 3/4 * Tsync Tsync - 64 - CXA3516R A/D Converter * Analog input signal The RGB analog input signal and YCbCr analog input signal are converted to digital signals and output. Be sure to adjust the input dynamic range of the ADC in the pre-stage amplifier block by performing contrast and brightness settings for the analog signal input to the ADC. (See the item on the amplifier for details on the setting procedure.) * Sampling clock Although the sampling clock is created by a PLL (internal CLK), it is also possible to externally input a clock to the ADC (external CLK) directly for checking ADC operations. In this case, be sure to make the register settings below in order to input a PECL level clock from the CLKIN (Pin 110) and the XCLKIN (Pin 109). Register: VCO By-pass ADC clock 0 External CLK 1 Internal CLK Note, however, that even if an external CLK is input under the above settings, it is impossible to run the ADC at the input clock frequency unless the PLL's VCO frequency divider is set to 1/1. Running the ADC on an external CLK is done in order to check the operations of the ADC. Normally, it should be run on the internal CLK generated by the PLL. * Reference voltage The input dynamic range of the ADC is determined based on the reference voltage from the VRT (Pin 17) and the VRB (Pin 93). Since this reference voltage is created using an internal band gap voltage, there is no need for an external reference voltage circuit. The voltage at the VRT pin is set to a voltage approximately 0.4V lower than the voltage coming from the AVCCAD3 power pin. Also, the VRB pin is set to a voltage approximately 1.0V lower than that at the VRT pin. Capacitors of 1F or more should be connected between the AVCCAD3 power supply pins for these reference voltage pins (VRT pin and VRB pin). If the value of the capacitor is too low or no capacitor is attached, the reference voltage circuit will cause an oscillation that results in noise or malfunction because the ADC faithfully samples this oscillation. It is impossible to apply an external voltage to a reference voltage pin. Note that it is also impossible to use the voltage generated by a reference voltage pin as an external voltage source. * Operational mode The ADC output data of this IC supports five types of operational mode. Each operational mode is set by using a control register. Register: DATA OUT MODE D3 Straight Data out Mode DMUX Parallel Data out Mode DMUX Interleaved Data out Mode 4:2:2 Data out D2 Mode 4:2:2 Data out special Mode 0 0 0 0 1 D2 0 0 1 1 1 D1 0 1 0 1 1 For a description of each operational mode, see the next page. - 65 - CXA3516R * Description of the operational modes (Straight Data out Mode) An RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog input signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). The sampled analog input signal is output from the port A side of the data output with a 3-clock pipeline delay. Note that output for port B side is turned off at this time and cannot be set to high impedance. The ADC data output is output with a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operational frequency in Straight Data out Mode is 100MHz at the sampling clock frequency. Also, note, when operating in Straight Data out Mode, that the output on the port B side (RB0 to RB7, GB0 to GB7, and BB0 to BB7) is turned off and cannot be set to high impedance. All TTL output are set to high impedance only when this IC is put into power save mode. The following type of interface is possible when this IC is operated in Straight Data out Mode. CXA3516R CLK XCLK 1/2CLK 1/2XCLK RA0 to RA7 GA0 to GA7 BA0 to BA7 99 98 101 100 max. min. Td_8 2.2ns (min.) to 3.8ns (max.) Scaling IC th (min.) The hold time of the post-stage scaling IC using the interface shown above is, th (min.) = 2.2ns - 66 - CXA3516R (DMUX Parallel Data out Mode) The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each clock cycle, sampled data is divided into pins in port A side and port B side. The data output on the port A side possesses a 3-clock pipeline delay versus the sampling clock, while the data output on the port B side possesses a 2-clock pipeline delay. The output timing is the same for data output from both ports. Data is maintained for two cycles (2T) of the sampling clock. ADC data is output with a propagation delay (Td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2XCLK (Pin 100). An interface of the following type is possible when this IC is run in DMUX Parallel Data out Mode. CXA3516R CLK XCLK 1/2CLK 1/2XCLK RA0 to RA7 GA0 to GA7 BA0 to BA7 RB0 to RB7 GB0 to GB7 BB0 to BB7 99 98 101 100 max. min. ts Td_7 1.3ns (min.) to 2.2ns (max.) T Scaling IC th ts th With the interface shown above, the post-stage scaling IC acquire data by using the clock signal output from the 1/2CLK pin of the ADC. In case of this interface, the setup time of the post-stage scaling IC is, ts (min.) = T - 2.2ns While the hold time is, th (min.) = T + 1.3ns - 67 - CXA3516R (DMUX Interleaved Data out Mode) The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each clock cycle, sampled data is divided into pins in port A and port B. The data output on the port A side possesses a 2-clock pipeline delay versus the sampling clock, while the data output on the port B side also possesses a 2-clock pipeline delay. Although the data output from both ports is maintained for two cycles (2T) of the sampling clock, there is one cycle (T) difference between the output timing for port A side and port B side. Data output on port A side possesses a propagation delay (Td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2XCLK (Pin 100), while data output on port B side possesses a propagation delay (Td_1/2clk to data) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2CLK (Pin 101). An interface of the following type is possible when this IC is run in DMUX Interleaved Data out Mode. CXA3516R CLK XCLK 1/2CLK 1/2XCLK RA0 to RA7 GA0 to GA7 BA0 to BA7 max. min. RB0 to RB7 GB0 to GB7 BB0 to BB7 99 98 101 100 max. min. Td ts Td ts Td th T Scaling IC th Td_7 1.3ns (min.) to 2.2ns (max.) With the interface shown above, port A data is acquired into the post-stage scaling IC by using the clock signal output from the 1/2CLK pin of the ADC, while port B data is acquired by using the clock signal output from the 1/2XCLK pin. In case of this interface, the setup time of the post-stage scaling IC is, ts (min.) = T - 2.2ns While the hold time is, th (min.) = T + 1.3ns - 68 - CXA3516R (4:2:2 Data out D2 Mode) The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). In 4:2:2 Data out D2 Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to the data output ports GA0 to GA7. The Cb and Cr signals are all simultaneously A/D converted at a half sampling rate compared with the Y signal, then multiplexed within the IC, and output to the data output ports BA0 to BA7 in the order U (Cb) and V (Cr). When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the signal. See the operational description of SYNCSEP for details. Data output of ADC possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operating frequency in 4:2:2 Data out D2 Mode is 100MHz as the sampling clock frequency. Although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the IC operates in 4:2:2 Data out D2 Mode, they cannot be set to high impedance. All TTL output is set to high impedance when this IC is put into power save mode. An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode. CXA3516R CLK XCLK 99 98 Td_8 2.2ns (min.) to 3.8ns (max.) max. min. Scaling IC 1/2CLK 101 1/2XCLK 100 GA0 to GA7 BA0 to BA7 The hold time of the post-stage scaling IC using the interface shown above is, th (min.) = 2.2ns - 69 - CXA3516R (4:2:2 Data out special Mode) The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog input signal to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). In 4:2:2 Data out special Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to the data output ports GA0 to GA7. The Cb and Cr signals are A/D converted at every other sampling at a half sampling rate of the Y signal, then multiplexed within the IC, and output to the data output ports BA0 to BA7 in the order U (Cb) and V (Cr). When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the signal. See the operational description of SYNCSEP for details. ADC data output possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operating frequency in 4:2:2 Data out special Mode is 100MHz as the sampling clock frequency. In addition, although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the IC operates in 4:2:2 Data out Special Mode, they cannot be set to high impedance. All TTL output is set to high impedance when this IC is put into power save mode. An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode. CXA3516R CLK XCLK 1/2CLK 1/2XCLK 99 98 101 100 max. min. Td_8 2.2ns (min.) to 3.8ns (max.) Scaling IC GA0 to GA7 BA0 to BA7 The hold time of the post-stage scaling IC using the interface shown above is, th (min.) = 2.2ns - 70 - CXA3516R * EVEN/ODD function When a toggle signal created by dividing the Vsync signal in half is input to the EVEN/ODD (Pin 108), the ADC sampling clock is inverted every Vsync signal. This function can be used to configure a single frame screen from two fields by AD converting an RGB analog input signal that requires high speed and high resolution, such as a UXGA 60Hz (162MHz) or more signal, at half the frequency of the original ADC sampling rate. There are no particular control register settings when using the EVEN/ODD function. The sampling clock is inverted based on the polarity of the signal input to the EVEN/ODD pin. Be sure to input signal to the EVEN/ODD pin at TTL level. EVEN/ODD pin Operational mode L EVEN H ODD Example of Using the EVEN/ODD Function 1 a b c d e f g h i j k l 3 2 Analog input signal 1 5 6 4 EVEN field 3 5 a b c d e f g h i j k l 2 ODD field 4 6 Hsync Sampling CLK Vsync Toggle signal (EVEN/ODD pin) 1 a b c d e f g h i j k l 2 3 4 5 6 EVEN/ODD frame - 71 - CXA3516R TTL Output High Level Setting All the TTL output pins can be set to high level by the control register. All the TTL output pins are set simultaneously. The TTL output pins are as follows. RA7 to RA0, RB7 to RB0, GA7 to GA0, GB7 to GB0, BA7 to BA0, BB7 to BB0, SEROUT, SOGOUT, Delay Sync Output, 1/2CLK, 1/2XCLK, CLK and XCLK Register: TTLOUT CLP High level (typ.) 00 2.2V 01 2.45V 10 2.7V 11 2.95V The TTL output can be input directly to a 3V power supply IC without level conversion. Set high level in accordance with the supply voltage. Power Save 1) Power save for all functions All functions of the chip can be stopped to save power by the XPOWER SAVE (Pin 6). The control register is also set to power save mode at this time. XPOWER SAVE pin Operating status The pin input level is TTL level. 2) Power save every block by using the control register The blocks except the registers can also be set to power save mode by the control register. Selects according to using state. Register ADC Power Save AMP Power Save PLL Power Save SYNC SEP Power Save 0 Power on Power on Power on Power on 1 Power save Power save Power save Power save L Power save H Power on - 72 - CXA3516R TTL Output Mode during Power Save Mode All TTL output pins are set to high impedance when the IC is put into power save mode. Since this IC supports power on reset, AMP, ADC, PLL, and SYNCSEP are set to power save mode when power is turned on and all TTL output pins are set to high impedance. However, note that the TTL output pins don't change into high impedance, when control register are used to set each TTL output disable mode separately. Even though there are also modes in which data output ports are set to output off mode based on the ADC operational mode, it cannot be set to high impedance. ADC Data Output Modes XPOWER ADC Straight SAVE Power Save mode mode mode RA7 to 0 RB7 to 0 GA7 to 0 GB7 to 0 BA7 to 0 BB7 to 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DATA -- DATA -- DATA -- DMUX Parallel mode DATA DATA DATA DATA DATA DATA DMUX YUV 4:2:2 YUV 4:2:2 Interleaved D2 Special mode mode mode DATA -- -- DATA -- -- DATA DATA DATA DATA DATA -- DATA -- DATA -- DATA -- Other TTL Output Pin Modes XPOWER PLL CLK XCLK 1/2CLK SAVE Power Save Disable Disable Disable mode mode Hi-Z Hi-Z -- Signal Signal Hi-Z Hi-Z Signal -- Signal Hi-Z Hi-Z Signal Signal -- Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal 1/2XCLK Disable Signal Signal Signal -- Signal Signal Signal Signal DSYNC SOGOUT SEROUT UNLOCK Disable Disable Disable Disable Signal Signal Signal Signal -- Signal Signal Signal Signal Signal Signal Signal Signal -- Signal Signal Signal Signal Signal Signal Signal Signal -- Signal Signal Signal Signal Signal Signal Signal Signal -- CLK XCLK 1/2CLK 1/2XCLK DSYNC/ DIVOUT SOGOUT SEROUT UNLOCK A dash (-) indicates output off status that cannot be set to high impedance. - 73 - CXA3516R Supply Current The default value for the current consumption and the control register-based power save current (ICC5PS, ICC3PS), and power save current (ICC5XPS, ICC3XPS) when the XPOWER SAVE function is used, are indicated to each block as follows. (The current consumption values given here are the typical values for when the IC is run at a clock frequency of 80MSPS.) Supply Current Register PS current XPS current voltage consumption (typ.) consumption consumption 5V (D) 5V (A) 5V (A) 5V (D) 5V (A) 5V (D) 3.3V (A) 17.2mA 80.0mA 16.0mA 41.4mA 6.8mA 73.2mA 180mA 17.2mA 0.7mA 0mA 2.0mA 0.4mA 6.0mA 3.0mA 1.2mA 0.7mA 0mA 1.0mA 0.4mA 6.0mA 3.0mA Block Register Supply pin names DVCCREG AMP (SYNCSEP) AVCCAMP PLL AVCCVCO + AVCCIR DVCCPLL + DVCCPLLTTL AVCCADREF ADC DVCCAD + DVCCADTTL AVCCAD3 + DVCCAD3 AVCCAMP = AVCCAMPR + AVCCAMPG + AVCCAMPB - 74 - PLL Timing Chart (Td1 = 3CLK) 0 N+2 N+3 N+1 N N-1 N+6 N+7 N+5 N+4 1 2 3 4 5 6CLK Analog input Td_3 (typ. 7ns) N-2 SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) 1CLK CLK (Pin 99) Td_2 = 1/32 to 64/32CLK Td_1 = 3CLK Td_4 (typ. 1.0ns) DSYNC signal (Pin 103) (DSYNC By-pass = 1) - 75 - Td_5 = 4CLK 1, 2, 4, 8CLK Td_5 = 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns) N-4 N-3 N-2 N-1 N N+1 N+2 N+3 RESET (Internal Signal) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) 1, 2, 4, 8CLK 1/2CLK (Pin 101) (N = EVEN) 1/2CLK (Pin 101) (N = ODD) ADC Data Output (Straight Mode) N-5 CXA3516R PLL Timing Chart (Td1 = 4CLK) 0 N+2 N+3 N+1 N N-1 N+6 N+7 N+5 N+4 1 2 3 4 5 6CLK Analog input Td_3 (typ. 7ns) N-2 SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) 1CLK CLK (Pin 99) Td_2 = 1/32 to 64/32CLK Td_1 = 4CLK Td_4 (typ. 1.0ns) DSYNC signal (Pin 103) (DSYNC By-pass = 1) - 76 - Td_5 = 4CLK Td_5 = 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns) N-4 N-3 N-2 N-1 N N+1 N+2 N+3 RESET (Internal Signal) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) 1, 2, 4, 8CLK DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) 1, 2, 4, 8CLK 1/2CLK (Pin 101) (N = EVEN) 1/2CLK (Pin 101) (N = ODD) ADC Data Output (Straight Mode) N-5 CXA3516R PLL Timing Chart (Td1 = 5CLK) 0 N+2 N+3 N+1 N N-1 N+6 N+7 N+5 N+4 1 2 3 4 5 6CLK Analog input Td_3 (typ. 7ns) N-2 SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) 1CLK CLK (Pin 99) Td_2 = 1/32 to 64/32CLK Td_1 = 5CLK Td_4 (typ. 1.0ns) DSYNC signal (Pin 103) (DSYNC By-pass = 1) - 77 - Td_5 = 4CLK Td_5 = 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns) N-4 N-3 N-2 N-1 N N+1 N+2 N+3 RESET (Internal Signal) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) 1, 2, 4, 8CLK DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) 1, 2, 4, 8CLK 1/2CLK (Pin 101) (N = EVEN) 1/2CLK (Pin 101) (N = ODD) ADC Data Output (Straight Mode) CXA3516R N-5 PLL Timing Chart (Td1 = 6CLK) 0 N+2 N+3 N+1 N N-1 N+6 N+7 N+5 N+4 1 2 3 4 5 6CLK Analog input Td_3 (typ. 7ns) N-2 SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) 1CLK CLK (Pin 99) Td_2 = 1/32 to 64/32CLK Td_1 = 6CLK Td_4 (typ. 1.0ns) DSYNC signal (Pin 103) (DSYNC By-pass = 1) - 78 - Td_5 = 4CLK Td_5 = 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns) N-4 N-3 N-2 N-1 N N+1 N+2 N+3 RESET (Internal Signal) DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 0) 1, 2, 4, 8CLK DIVOUT signal (Pin 103) (DSYNC By-pass = 0, DIVOUT Delay = 1) 1, 2, 4, 8CLK 1/2CLK (Pin 101) (N = EVEN) 1/2CLK (Pin 101) (N = ODD) ADC Data Output (Straight Mode) N-5 CXA3516R CXA3516R ADC Timing Diagram CLK Clock XCLK 2.0V 0.8V Td_6 min. typ. max. 0.9ns to 1.2ns to 1.6ns min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns TR_CLK TF_CLK 1/2CLK 1/2 clock 1/2XCLK TR_CLK TF_CLK 2.0V 0.8V min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns Data 2.0V 0.8V Td_8 min. typ. max. 2.2ns to 2.8ns to 3.8ns min. 0.9ns 0.9ns typ. 1.2ns 1.2ns max. 2.0ns 2.0ns TR_DATA TF_DATA The timing diagram above supposes that one data cycle represents the same amount of time as one clock cycle concerning the three modes as follows: Straight Data out Mode, 4:2:2 Data out D2 Mode, and 4:2:2 Data out special Mode. - 79 - CXA3516R ADC Timing Diagram T CLK Clock XCLK 2.0V 0.8V Td_6 min. typ. max. 0.9ns to 1.2ns to 1.6ns min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns TR_CLK TF_CLK 1/2CLK 1/2 clock 1/2XCLK T - 2.2ns min. T + 1.3ns min. TR_CLK TF_CLK 2.0V 0.8V min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns Data 2.0V 0.8V Td_7 min. typ. max. 2.3ns to 2.6ns to 3.2ns min. 0.9ns 0.9ns typ. 1.2ns 1.2ns max. 2.0ns 2.0ns TR_DATA TF_DATA The timing diagram above supposes DMUX Parallel Data out Mode. It is possible for the post-stage scaling IC to acquire data by using a 1/2 clock. The output delay time in this mode is the same as that in DMUX Interleaved Data out Mode. - 80 - CXA3516R ADC Timing Diagram (Straight Data out Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N2 N1 N0 N3 N4 N5 N6 N7 N8 N9 N10 N2 N3 N4 N5 N6 N7 - 81 - CXA3516R ADC Timing Diagram (DMUX Parallel Data out Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N2 N1 N0 N3 N4 N5 N6 N7 N8 N9 N10 N2 N4 N6 N3 N5 N7 - 82 - CXA3516R ADC Timing Diagram (DMUX Interleaved Data out Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N2 N1 N0 N3 N4 N5 N6 N7 N8 N9 N10 N3 N5 N7 N2 N4 N6 - 83 - CXA3516R ADC Timing Diagram (4:2:2 Data out D2 Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) Y2 Y1 Y0 Y3 Y4 Y5 Y6 Y7 Cb9 Cb7 Cr9 Cr5 Cr7 Y8 Y9 Y10 GIN1 (124 pin) GIN2 (126 pin) Cb1 Cb3 Cb5 BIN1 (133 pin) BIN2 (136 pin) Cr1 Cr3 SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out GA7 to GA0 BA7 to BA0 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Cb3 (U3) Cr3 (V3) Cb5 (U5) Cr5 (V5) Cb7 (U7) Cr7 (V7) - 84 - CXA3516R ADC Timing Diagram (4:2:2 Data out special Mode) Analog input RIN1 (139 pin) RIN2 (141 pin) Y2 Y1 Y0 Y3 Y4 Y5 Y6 Y7 Cb9 Cb7 Y8 Y9 Y10 GIN1 (124 pin) GIN2 (126 pin) Cb1 Cb3 Cb5 Cr2 Cr10 Cr4 Cr6 Cr8 BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out GA7 to GA0 BA7 to BA0 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Cr2 (V3) Cb3 (U3) Cr4 (V4) Cb5 (U5) Cr6 (V6) Cb7 (U7) Cr8 (V8) - 85 - CXA3516R ADC Timing Diagram (Straight Data out Mode, EVEN/ODD) EVEN Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N18 N11 N4 N5 N7 N6 N14 N8 N9 N12 N13 N15 N16 N17 N19 N20 N21 N2 N3 N1 N0 N10 N4 N6 N8 N10 N12 N14 ODD Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N2 N3 N1 N0 N4 N5 N7 N6 N8 N9 N10 N11 N12 N13 N15 N14 N16 N17 N18 N19 N20 N21 N5 N7 N9 N11 N13 - 86 - CXA3516R ADC Timing Diagram (DMUX Parallel Data out Mode, EVEN/ODD) EVEN Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N18 N11 N4 N5 N7 N6 N14 N8 N9 N12 N13 N15 N16 N17 N19 N20 N21 N2 N3 N1 N0 N10 N4 N8 N12 N6 N10 N14 ODD Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N18 N11 N4 N5 N7 N6 N14 N8 N9 N12 N13 N15 N16 N17 N19 N20 N21 N2 N3 N1 N0 N10 N5 N9 N13 N7 N11 N15 - 87 - CXA3516R ADC Timing Diagram (DMUX Interleaved Data out Mode, EVEN/ODD) EVEN Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N18 N11 N4 N5 N7 N6 N14 N8 N9 N12 N13 N15 N16 N17 N19 N20 N21 N2 N3 N1 N0 N10 N6 N10 N14 N4 N8 N12 ODD Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) CLK (99 pin) XCLK (98 pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data out RA7 to RA0 GA7 to GA0 BA7 to BA0 RB7 to RB0 GB7 to GB0 BB7 to BB0 N2 N3 N1 N0 N4 N5 N7 N6 N8 N9 N10 N11 N12 N13 N15 N14 N16 N17 N18 N19 N20 N21 N7 N11 N15 N5 N9 N13 - 88 - CXA3516R Main Contrast Control Characteristics 2.5 30 Sub Contrast Control Characteristics 2.0 Gain adjustment ratio [%] 20 10 Gain [dB] 1.5 0 1.0 Sub contrast = 128 R, G, B OUT 0.5 -10 Main contrast = 128 R, G, B OUT -20 0 0 50 100 150 200 250 Main Contrast register -30 0 50 100 150 200 250 Sub Contrast register Brightness Level Control Characteristics 80 60 AD output conversion level (LSB) AD output conversion level (LSB) 40 20 0 -20 -40 -60 -80 0 50 100 150 200 250 Brightness register CbCr Clamp Level Control Characteristics 150 145 140 135 130 125 120 115 110 105 100 0 10 20 30 40 50 60 CbCr offset register SYNC SEP VTH Control Characteristics 250 80 70 200 60 150 50 40 30 20 50 10 0 0 2 4 6 8 10 12 14 VTH register 0 SYNC SEP VHYS Control Characteristics 100 VHYS [mV] VTH [mV] 0 1 VHYS register 2 3 - 89 - CXA3516R Frequency Response 9 7 6 5 Gain [dB] 3 1 -1 -3 -5 0.1 Main contrast = 128 Sub contrast = 128 R, G, B OUT Gain fluctuation ratio [%] 4 2 0 -2 -4 -6 -8 1 10 Frequency [MHz] 100 300 -10 -10 10 8 Gain Temperature Characteristics Main contrast = 128 Sub contrast = 128 R, G, B OUT 0 10 20 30 40 50 60 70 Ta - Ambient temperature [C] Gain Supply Voltage Characteristics 2.0 1.5 Gain fluctuation ratio [%] 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 4.75 Main contrast = 128 Sub contrast = 128 R, G, B OUT AD output fluctuation (LSB) Brightness Level Temperature Characteristics 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 Brightness = 128 -0.2 5 Supply voltage [V] 5.25 -0.3 -10 0 10 20 30 40 50 60 70 Ta - Ambient temperature [C] Brightness Supply Voltage Characteristics 1.5 CbCr Clamp Level Temperature Characteristics 0.6 AD output level fluctuation (LSB) 0.5 AD output level fluctuation (LSB) 1.0 0.4 0.2 0 0 -0.5 -0.2 CbCr offset register = 32 -0.4 -1.0 Brightness = 128 -1.5 4.75 5 Supply voltage [V] 5.25 -0.6 -10 0 10 20 30 40 50 60 70 Ta - Ambient temperature [C] - 90 - CXA3516R CbCr Clamp Level Supply Voltage Characteristics 0.6 250 KVCO Characteristics DIV = 1/1 DIV = 1/2 DIV = 1/4 DIV = 1/8 AD output level fluctuation (LSB) 0.4 Output frequency [MHz] 200 0.2 150 0 100 -0.2 CbCr offset register = 32 -0.4 50 -0.6 4.75 5 Supply voltage [V] 5.25 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCO control voltage [V] Fine Delay vs. Control 80 72 64 Fine delay [1/32CLK] 56 48 40 32 24 16 8 0 0 8 16 24 32 40 48 56 64 Fine delay register control [1/32CLK] Jitter Peak-Peak vs. Output Frequency 2.0 1.8 1.6 Jitter peak-peak [ns] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 Output frequency [MHz] NTSC, VGA, SVGA, XGA, SXGA, UXGA, DIV = 1/8, DIV = 1/4, DIV = 1/4, 1/2, DIV = 1/2, DIV = 1/1, DIV = 1/1, CP = 010, 100 CP = 010, 011 CP = 010, 100, 101 CP = 011, 100 CP = 010, 011, 100 CP = 101 - 91 - CXA3516R Current Consumption vs. Temperature Characteristics 200 Current Consumption vs. Supply Voltage Fluctuation 200 Current consumption [mA] 180 Current consumption [mA] 180 ICC5 ICC3 CLK = DC 160 -10 ICC5 ICC3 CLK = DC 160 3.0 4.75 0 25 50 75 3.3 5.0 Supply voltage [V] 3.6 5.25 VCC3 VCC5 Ta - Ambient temperature [C] Current Consumption vs. Frequency Response 260 Operational mode: DMUX parallel Data out Load capacitance: CL = 10pF 240 Current consumption [mA] 220 200 ICC5 ICC3 180 160 20 40 60 80 100 120 140 160 FCLK - Clock frequency [MHz] - 92 - Application Circuit (I2C (High) mode) VRB AGNDADREF 1 AVCCAD3 DVCCAD3 DVCCAD DVCCADTTL GB7 DGNDADTTL GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 GB0 DGNDAD3 DGNDADTTL DVCCADTTL GA7 GA6 72 71 70 GA2 GA1 GA0 DGNDADTTL DGNDAD3 DVCCADTTL BB7 BB6 BB5 BB4 BB3 GNDAD3 BB2 BB1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 BB0 DGNDADTTL DVCCADTTL BA7 BA6 BA5 DGNDAD3 BA4 BA3 BA2 BA1 BA0 DGNDADTTL DGNDAD3 DVCCADTTL RB7 RB6 RB5 RB4 RB3 69 68 67 66 65 64 63 62 61 60 59 58 57 GA3 GA4 EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 XCLKIN 109 DVCCPLLTTL GA5 CLKIN 110 This is an application circuit which controls this IC with I2C (High) mode and supports RGB2 channel input. ADC operational mode supports DMUX Parallel mode or DMUX Interleaved mode. (I2C bus slave address is 10011000.) SYNCIN1 111 SYNCIN2 112 CLPIN 113 DVCCPLL 114 DGNDPLL 115 100p AVCCVCO 116 AGNDVCO 117 RC1 118 C2 330p RC2 119 R1 3.3k C1 0.33 AVCCIR 120 100p 3k IREF 121 DPGND 122 AGNDIR 123 G1 0.1 G/YIN1 124 G2 75 AVCCAMPG 125 NC NC RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 DPGND AVCCAD3 VRT DVCCAD3 DGNDAD3 AGNDAD3 DGNDAD3 RA7 RB1 R/CrOUT SDA SCL B/CbOUT ADDRESS DVCCREG SEROUT DGNDREG XSENABLE 3WIRE/I2C RB2 DVCCADTTL AVCCADREF DGNDADTTL DVCCADTTL XPOWER SAVE 4.7k 4.7k 1 DGNDADTTL - 93 - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0.1 G/YIN2 126 75 AGNDAMPG 127 0.1 G/YCLP 128 0.1 B/CbCLP 129 0.1 R/CrCLP 130 0.1 DPGND 131 SOGIN1 132 B1 B/CbIN1 133 0.1 0.1 75 AVCCAMPB 134 SOGIN2 135 B2 0.1 B/CbIN2 136 75 AGNDAMPB 137 DPGND 138 R1 0.1 R/CrIN1 139 R2 75 AVCCAMPR 140 0.1 R/CrIN2 141 75 AGNDAMPR 142 G/YOUT 143 DACTESTOUT 144 1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. AVCC5V DVCC5V 3.3V CXA3516R DGND AGND Application Circuit (3-wire bus mode) This is an application circuit which controls this IC with 3-wire bus mode and operates ADC with 4:2:2 Data out D2 mode with respect to YcbCr analog input signal. AGNDADREF 1 AVCCAD3 DVCCAD DVCCADTTL GB7 DGNDADTTL GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 GB0 DGNDAD3 DGNDADTTL DVCCADTTL GA7 GA6 72 71 70 GA2 GA1 GA0 DGNDADTTL DGNDAD3 DVCCADTTL BB7 BB6 BB5 BB4 BB3 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 GNDAD3 BB2 BB1 BB0 DGNDADTTL DVCCADTTL BA7 BA6 BA5 DGNDAD3 BA4 BA3 BA2 BA1 BA0 DGNDADTTL DGNDAD3 DVCCADTTL RB7 RB6 RB5 RB4 RB3 69 68 67 66 65 64 63 62 61 60 GA3 GA4 RB1 RB2 VRB EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 5 NC NC SCL SDA SEROUT DVCCREG DGNDREG XSENABLE 6 7 8 R/CrOUT B/CbOUT ADDRESS 2 3 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 RA0 RA1 RA2 RA3 RA4 RA5 RA6 DPGND AVCCAD3 VRT DVCCAD3 3WIRE/I2C DGNDAD3 AGNDAD3 DGNDAD3 RA7 RB0 AVCCADREF XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVCCPLL DGNDPLL 100p AVCCVCO AGNDVCO RC1 C2 330p RC2 R1 3.3k C1 0.33 AVCCIR 100p 3k IREF DPGND AGNDIR Y 0.1 G/YIN1 75 AVCCAMPG DVCCADTTL DVCCADTTL DGNDADTTL XPOWER SAVE 820 820 4.7k 4.7k 1 DGNDADTTL - 94 - TP-B TP-R G/YIN2 AGNDAMPG 0.1 G/YCLP 0.1 B/CbCLP 0.1 R/CrCLP 0.1 DPGND SOGIN1 Cb 0.1 B/CbIN1 75 AVCCAMPB SOGIN2 B/CbIN2 AGNDAMPB DPGND Cr 0.1 R/CrIN1 75 AVCCAMPR R/CrIN2 AGNDAMPR 820 G/YOUT DACTESTOUT TP-G DVCCPLLTTL DVCCAD3 GA5 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. AVCC5V DVCC5V 3.3V CXA3516R DGND AGND CXA3516R Notes on Operation * On the PC board, prepare a solid ground pattern having as large an area as possible, and placing the IC in the center, divide this area into an analog region and digital region. * The loop filter area of the PLL block plays an important role in terms of performance. It is therefore located as close as possible to the IC pins and the periphery is guarded with AGND. Also, be sure to use capacitors and resistors for the loop filter that should be temperature compensated and do not change the values. * Be sure to use a metal film resistor for the resistor connected to IREF (Pin 121). * The wiring for SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112) should be as short as possible and each needs to be shielded by ground. * Use a 0.1F ceramic chip capacitor for the bypass capacitor attached between the power supply and ground. The capacitor should be attached to the pin as close as possible. * Use a 1F ceramic chip capacitor for the capacitor attached to the VRT (Pin 17) and the VRB (Pin 93) and connect to the AVCCAD3 (Pin 16 and Pin 94) as close as possible. * Equalize and shorten the lines of RGB analog input signals, if possible. Each line needs to be shielded by ground. (This is the same for the R/CrCLP, G/YCLP, and B/CbCLP pins.) * A 0.1F capacitor is recommended for attachment to the RGB analog input pins. The less the capacitance becomes, the more the sag by leak current becomes. The more the capacitance becomes, the more start up time takes in case of putting power souce into the IC. (This is the same for the R/CrCLP, G/YCLP, and B/CbCLP pins.) * Design boards so that the wiring for the R/CrIN, G/YIN, and B/CbIN and R/CrOUT, G/YOUT, B/CbOUT pins is as separated as possible. * Use a pattern width that takes characteristic impedance into account for signal wires terminated at 75. * There are no particular restrictions on the power-on sequence. * Although there are AVCCAD3 and DVCCAD3 as 3.3V power supply, use the same 3.3V analog power supply to each on the board. * AGNDAD3 and DGNDAD3 are the ground for AVCCAD3 and DVCCAD3, respectively. Use the same ground for AGNDAD3 and DGNDAD3. Although AGND is the ground recommended for AGNDAD3 and DGNDAD3, there are no problems in terms of operation even if connected to DGND. (The special evaluation board in the Application Circuit is connected to DGND.) * Although 5V power supply is divided into both analog and digital power supply lines, be sure to wire boards so that no potential difference arises between these power supplies. * Load capacitance of the data output wires causes the change for the worse of slew rate and noise. Be sure to use short layouts with the finest wires possible. * Put this IC into power save mode when making a connection between data output and another IC. (High impedance cannot be set when pins are disabled separately.) - 95 - CXA3516R CXA3516R Evaluation Board Overview The CXA3516R Evaluation Board is a special board designed for the easy evaluation of the CXA3516R developed for the LCD projector and monitor so that performance can be maximized. The DSUB 15-pin connector is used as the input connector that allows the direct input of a video signal from a PC. The input video signal is A/D converted by the CXA3516R and a pin for monitoring is designed onto the board so that output data can be checked directly. The 10-bit high speed D/A converters are built onto the board so that the performance of the IC can be easily checked. Picture quality can be easily evaluated by using a CRT monitor since the D/A-converted video signal is output from the DSUB 15-pin connector for output in addition to the DSYNC output of the CXA3516R. Features * Single +5V power supply (with built-in 3.3V regulator) * Allows two-line video signal input * Data output port is also used as output data monitoring pin * CXA3516R output is D/A converted and is easily monitored by a CRT * Supports 2 types of control registers (3-wire and I2C) Operating Conditions * Supply voltage: +5V (typ.) * Current consumption: 830mA (typ.) * Input signal: Separated sync video signal - 96 - CXA3516R EVB Block Diagram Power supply pins 5V CXA2016P Clamp pulse generation 0V CLPIN R, G, B analog input signal 0.1F Control signal SOGOUT Video In1 CON1 R, G, B analog input signal 0.1F CXA3516R Video signal 1 Hsync signal 1 Vsync signal 1 R, G, B digital output data Output data monitoring pins data output ports Video signal input pins - 97 - Vsync signal select R, G, B analog output signal 10F SW1 SW2 SW3 Power save 3WIRE/I2C I/O logic 3Wire CON5 I2C CON4 Control register pins Video In2 Video signal 2 Hsync signal 2 CON2 Vsync signal 2 DAC x3 CXA3197R Video OUT Video signal output pins Video signal output Hsync output Vsync output CON3 CXA3516R CXA3516R Using the CXA3516R Evaluation Board The CXA3516R Evaluation Board can be used to easily evaluate just by connecting a power supply, video signals, and control register signals. The procedure is described below. 1. Connect the power supply to the power connection pin. (GND/+5V) Do not apply power supply in this state. 2. Check the direction of SW1. SW1 is the power save control switch. The CXA3516R is put into power save mode when SW1 is set to the rear position (). Set SW1 to the forward () position when using the CXA3516R. SW1 is connected to the XPOWER SAVE pin. 3. Connect the special control register signal cable. Connect the cable to CON4 when using I2C control. Set SW2 and SW3 to the forward () position. While, connect the cable to CON5 when using 3-wire control. Set SW2 and SW3 to the rear () position. In addition, check that the short pin (I2C) is in the "00" position in case of using I2C control. 4. Input the RGB analog signals from the CON1 pin (Video In 1). XGA60 is recommended as the initial signal because the control program default value is set for the XGA60. XGA60: Vsync 60Hz Hsync: Video signal for 48kHz N = 1344 5. The RGB analog signal for simple picture quality evaluations is output from the CON3 pin (Video Out). Be sure to connect the CON3 pin to a CRT monitor that can process a signal of XGA60 or more. 6. Turn on the power. Check a current to be about 360mA flows through the 5V power supply. If there is much more current than this, immediately turn off the power and check that there are no misconnections. 7. Run the control program. Click on "re-load" at the bottom right of the control program screen, and check a current to be about 830mA flows through the 5V power supply. If everything works normally, an processed image for picture quality evaluation appears on the CRT monitor. Reconfirm the above items from the beginning if the processed image does not appear. - 98 - CXA3516R 3-wire Control Program Installation and Startup Method [Operating Environment] Windows95 or Windows98 [Program Installation and Startup] The installation program is configured from the following four files and stored in two floppy disks. setup.exe, A3506_1.cab, A3506_2.cab, and Setup.lst 1. Copy the four files from the floppy disk onto the PC. 2. Click setup.exe. The installer will start. Follow all on-screen instructions. 3. Once installation complete, a folder titled "Project1" will be created in the Program files folder. 4. The following control window will open when the A3506.exe file starts. Use this window to make board settings in response to the printer port address of the PC. Be sure to set the address for the PC from the pull-down menu port at the top-left of the control screen. There are two types of addresses: 378 and 3BC. - 99 - CXA3516R I2C Control Program Installation and Startup Method [Operating Environment] Windows95 or Windows98 [Program Installation and Startup] The installation program consists of the following four files and is stored in two floppy disks. setup.exe, A3506_1.cab, A3506_2.cab, Setup.lst 1. Copy these four files from the floppy disk onto the PC. 2. Click setup.exe. The installer will start. Follow all on-screen instructions. 3. Once installation complete, a folder titled "Project1" will be created in the Program files folder. 4. The following control window will open when the A3506.exe file starts. Use this window to make board settings in response to the printer port address of the PC. Be sure to set the address for the PC from the pull-down menu port at the top-left of the control screen. There are two types of addresses: 378 and 3BC. - 100 - CXA3516R Notes on Using CXA3516R EVB 1. RGB analog signals input from CON1 or CON2 are A/D converted. The digital signals are D/A converted. In addition, the analog signals are output in AC coupling. Therefore, the output are the RGB analog signals output from CON3. In this reason, when the RGB analog signals output from CON3 undergo picture quality evaluation by using a CRT monitor, note that on-screen evaluation cannot be confirmed about the functions of SUB BRIGHTNESS and Cb/Cr OFFSET. This is due to the fact that the DC component disappears because the RGB analog signals are output in AC coupled after output by the D/A converter, even if the DC offset is changed. 2. The current consumption for this board immediately after turning on the board's power is approximately 360mA. Board current is 830mA when the CXA3516R control register is started after this. When turning on power to the board, be sure to check the board current and make sure that connections are correct. 3. Although this board is equipped with a -5V power supply pin, it can operate by using a single 0/+5V power supply. Be sure to leave the -5V power supply pin open. Notes Regarding the Control Program 1. When the program is accurately installed on the PC, be sure to re-check items 2 and 3 of the operational procedures above when the IC does not move. 2. If the CXA3516R does not move even after item 1 above is checked, it is possible that the control signals of the control register are not output from the PC printer board. In this case, be sure to re-check the board settings listed for item 4 under "Program Installation and Startup". - 101 - CXA3516R CXA3516R Evaluation Board Parts List Parts No. IC1 IC2 IC3, 4, 5 IC6 IC7 IC8 IC9 CON1, 2, 3 CON4 CON5 SW1 SW2 SW3 L1, 2 R1, 2 R3, 4 R5 R6 R7 to 12 R13 to 15 R17, 18 R19 R20, 21 R22 R23 R24, 25, 27 R26, 29, 32 R28, 31, 34 R30, 33 R35 to 37 R38, 39 R40 to 44 R45 R47, 48 R49, 50 620 200 3.3k 3k 75 820 75 270 12k 33k 2.2k 1k 75 620 1k 24k 24k 10k 820 2k 3k Product name CXA3516R CXA2016S CXA3197R SN74LS04N SN74LS32N SN74LS08N LT1086CM-3.3 D02-N15SAG-13L9 53053-0510 53053-0610 G-12AP G-13AP G-22AP ZBF503D-00 Chip resistor Chip resistor Chip metal film resistor Lead metal film resistor Chip resistor Chip resistor Chip resistor Chip resistor Lead metal film resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor SONY SONY SONY Texas Instruments Texas Instruments Texas Instruments Linear Technology SANSHIN ELECTRONICS Molex Molex NIHON KAIHEIKI IND. NIHON KAIHEIKI IND. NIHON KAIHEIKI IND. TDK C1 to 4 C5 C6, 7 C8 to 10 C11, 12 C13, 14 C15 C16 C17 C18 to 34 C35 C36 to 44 C45 C47 C48, 49 C50 C51 C52 C53 C54 C55 to 70 C71 to 75 - 102 - 10 2.2 1 100 0.1 100p 0.1 330p 0.33 0.1 1 0.1 1 0.1 0.22 0.1 0.22 0.1 0.01 3300p 0.1 0.1 Tantalum capacitor Tantalum capacitor Tantalum capacitor Electrolytic capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Manufacturer CLAMP DSYNC VSYNC2 VSYNC1 SOGOUT 1/2CLK 1/2XCLK CLK XCLK AGND 3V Video Signal RGB Data RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA7 RA6 RA5 EVEN/ODD XTLOAD DGND UNLOCK DVcc C47 0.1 C45 1 C44 0.1 C43 0.1 C42 0.1 R3 200 R5 3.3k C12 0.1 C13 100p C16 330p C14 100p DVcc DGND AVcc AGND C11 0.1 R4 200 EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL DVccPLLTTL AGNDADREF AVccAD3 VRB DVccAD3 DVccAD DVccADTTL DGNDADTTL GB7 GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 DGNDAD3 GB0 DGNDADTTL DVccADTTL GA7 GA6 GA5 R1 620 AVcc R2 620 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 RA4 RA3 RA2 RA1 RA0 AGND C41 0.1 CON1 R7 75 C21 0.1 R8 75 IC1 CXA3516R AVcc C20 0.1 11 6 1 AVcc C17 0.33 C15 0.1 C19 0.1 AGND C18 0.1 R6 3k GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 C40 0.1 AGND AGND AGND GOUT R13 820 AGND ROUT BOUT C33 0.1 C34 0.1 C35 1 C37 0.1 10010 10 10010 11 10010 01 Slave address 10010 00 SW1 XPOWER SAVE S1 S2 S3 S4 SW2 3-Wire/I2C R14 820 R15 820 C36 0.1 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BB0 BB1 BB2 C38 0.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 B/CbOUT ADDRESS R/CrOUT NC NC XPOWER SAVE DGNDREG DVccREG SDA SCL XSENABLE SEROUT 3WIRE/I2C DPGND AVccADREF AVccAD3 VRT DVccAD3 DVccADTTL DGNDADTTL RA0 RA1 DGNDAD3 RA2 RA3 RA4 RA5 RA6 AGNDAD3 DGNDAD3 RA7 DVccADTTL DGNDADTTL RB0 RB1 RB2 CXA3516R DGND DVcc DVcc DGND DGND DVcc SDA SCL SENABLE SEROUT R35 24k R38 24k R39 24k R36 24k R37 24k AGND AVcc 3V DGND Register - 103 - C22 0.1 AGND C23 0.1 C24 0.1 C25 0.1 C26 0.1 AVcc C29 0.1 C27 0.1 C28 0.1 AGND C30 0.1 R10 75 C31 0.1 AGND AVcc AVcc C32 0.1 R9 75 R11 75 R12 75 15 10 5 Video IN1 AGND GA7 GA6 GA5 CON2 GA4 GA3 GA2 GA1 GA0 C39 0.1 11 6 1 15 10 5 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVccPLL DGNDPLL AVccVCO AGNDVCO RC1 RC2 AVccIR IREF DPGND AGNDIR G/YIN1 AVccAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP DPGND SOGIN1 B/CbIN1 AVvAMPB SOGIN2 B/CbIN2 AGNDAMPB DPGND R/CrIN1 AVccAMPR R/CrIN2 AGNDAMPR G/YOUT DAC TEST OUT Video IN2 GA4 GA3 GA2 GA1 GA0 DGNDADTTL DGNDAD3 DVccADTTL BB7 BB6 BB5 BB4 BB3 GNDAD3 BB2 BB1 BB0 DGNDADTTL DVccADTTL BA7 BA6 BA5 DGNDAD3 BA4 BA3 BA2 BA1 BA0 DGNDADTTL DGNDAD3 DVccADTTL RB7 RB6 RB5 RB4 RB3 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 BB7 BB6 BB5 BB4 BB3 R17 C5 75 2.2 IC2 C48 C49 1k R24 R25 DSYNC 1/2CLK 1/2XCLK CLK XCLK CLAMP C54 3300p C55 0.1 C50 C51 R19 R20 R21 R22 AGND AGND 1k 0.22 0.22 CXA2016S AVcc C6 1 DVcc C74 0.1 R47 2k CLK R48 2k CLKP/E CLKN/E R50 AGND 3k DGND XCLK C75 R49 0.1 3k R18 C7 75 1 SOGOUT RGB Data Video Signal 1 2 3 4 0.1 5 0.22 6 270 7 8 12k 9 12k 10 11 33k 22 VSIN AVcc 21 PVC VD 20 EVC Vssin 19 CSIN Vssout 18 R23 PHC HD 17 2.2k EHC PV 16 Videoin PH 15 C52 0.1 HDsel clpsel 14 ISC xclpout 13 ISJ clpout 12 C53 0.01 AGND VssREF DSYNC 1/2CLK 1/2XCLK CLK XCLK RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 GB0 GB1 GB2 GB3 GB4 GB5 GB6 GB7 GA0 GA1 GA2 GA3 GA4 GA5 GA6 GA7 BB0 BB1 BB2 BB3 BB4 BB5 BB6 BB7 BA0 BA1 BA2 BA3 12 11 10 9 8 7 6 5 4 3 2 1 12 11 10 9 8 7 6 5 4 3 2 1 DB4 DB5 DB6 DB7 DB8 DB9 DA0 DA1 DA2 DA3 DA4 DA5 DB4 DB5 DB6 DB7 DB8 DB9 DA0 DA1 DA2 DA3 DA4 DA5 DB4 DB5 DB6 DB7 DB8 DB9 DA0 DA1 DA2 DA3 DA4 DA5 12 11 10 9 8 7 6 5 4 3 2 1 BA4 BA5 BA6 BA7 DGND DGND DGND RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 IC3 CXA3197R DVcc DVcc C59 0.1 IC4 C63 0.1 CXA3197R IC5 CXA3197R C67 0.1 DVcc 13 14 15 16 1/2CLK 17 18 CLK/T 19 CLKP/E 20 CLKN/E 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 DGND2 C1 C2 C3 DVcc2 AVccO AOUTN AOUTP AGND2 VREF VSET AVcc2 DA6 DA7 DA8 DA9 DGND1 NC DVcc1 PS INV RPOLARITY VOCLP AGND2 DB3 DB2 DB1 DB0 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E 48 47 46 45 44 43 42 41 40 39 38 37 DB3 DB2 DB1 DB0 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DB3 DB2 DB1 DB0 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E VSYNC1 VSYNC2 DSYNC S5 S6 25 26 27 28 29 30 R26 75 C68 0.1 31 32 33 34 R27 1K R28 620 35 36 C58 0.1 25 26 27 28 29 30 R29 75 C69 0.1 31 32 33 34 R30 1K R31 620 35 36 C62 0.1 C56 0.1 C61 0.1 C57 0.1 C60 0.1 25 DGND2 26 C1 27 C2 28 C3 29 DVcc2 30 AVccO R32 75 C70 0.1 31 AOUTN 32 AOUTP 33 AGND2 34 VREF R33 1K R34 620 35 VSET 36 C66 0.1 AVcc2 Video IN1 Vsync Video IN2 Vsync - 104 - DGND DGND C9 100 DGND DGND2 C1 C2 C3 DVcc2 AVccO AOUTN AOUTP AGND2 VREF VSET AVcc2 DA6 DA7 DA8 DA9 DGND1 NC DVcc1 PS INV RPOLARITY VOCLP AGND2 13 14 15 16 1/2CLK 17 18 CLK/T 19 CLKP/E 20 CLKN/E 21 22 23 24 13 14 15 16 1/2CLK 17 18 CLK/T 19 CLKP/E 20 CLKN/E 21 22 23 24 DA6 DA7 DA8 DA9 DGND1 NC DVcc1 PS INV RPOLARITY VOCLP AGND2 48 47 46 45 44 43 42 41 40 39 38 37 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 C64 0.1 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 C65 0.1 S7 S8 S9 S10 C10 100 AVcc CON3 AGND 11 6 1 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 AVEE C8 100 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 15 10 5 Video OUT AGND BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 CXA3516R IC9 LT1086CM-3.3 GND Vout Vin AVcc 1 2 3 L1 V1 +5V C1 10 AGND C4 10 AVEE L2 DGND V3 -5V V2 0V C2 10 C3 10 DVcc 3V SEROUT SENABLE SCL SDA - 105 - SW6 3-Wire/I2C IC6A 3 4 IC6B 6 6 IC6C 8 IC6D 5 74AS04 9 74AS04 3 74AS04 2 IC7A 3 1 74AS32 Register R40 10k R41 10k R43 10k 2 74AS04 1 2 IC8A 1 74AS08 R42 10k R44 10k R45 820 DVcc SDA SCL 5 4 74AS08 IC8B 6 IC6E 11 10 74AS04 IC6F 13 12 74AS04 CON4 I 2C DGND 1 5 DGND SDA SCL SENABLE SEROUT DVcc CON5 3-WIRE 1 C71 0.1 DGND CXA3516R C72 0.1 C73 0.1 CXA3516R - 106 - CXA3516R - 107 - CXA3516R - 108 - CXA3516R - 109 - CXA3516R Package Outline Unit: mm 144PIN LQFP (PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 1.4 0.1 72 B A 144 37 1 0.5 36 b 0.08 M S S 0.1 S 0.1 0.05 b = 0.22 0.05 (21.0) 0 to 10 DETAIL A 0.5 0.15 DETAIL B : SOLDER 0.145 0.04 (0.125) DETAIL B : PALLADIUM PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 1.3 g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). - 110 - 0.125 0.04 (0.2) b = 0.20 0.03 Sony Corporation |
Price & Availability of CXA3516
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |