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64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
Integrated Device Technology, Inc.
IDT49C466 IDT49C466A
FEATURES:
* 64-bit wide Flow-thruEDCTM * Separate System and Memory Data Input/Output Buses * -- Error Detect Time: 10ns -- Error Correct Time: 15ns * Corrects all single bit errors; Detects all double bit errors and some multiple bit errors * Configurable 16-deep bus read/write FIFOs with flags * Simultaneous check bit generation and correction of memory data * Supports partial word writes on byte boundaries * Low noise output * Sophisticated error diagnostics and error logging * Parity generation on system data bus * 208-pin Plastic Quad Flatpack
DESCRIPTION:
The IDT49C466/A 64-bit Flow-thruEDC is a high-speed error detection and correction unit that ensures data integrity in memory systems. The flow-thru architecture, with separate system and memory data buses, is ideally suited for pipelined memory systems. Implementing a modified Hamming code, the IDT49C466/A corrects all single bit hard and soft errors, and detects all double bit errors. The read/write FIFOs can store up to sixteen words. FIFO full and empty flags indicate whether additional data can be written to or read from the EDC. Check bit generation for partial word writes on byte boundaries is supported on the IDT49C466/A. Diagnostic features include a check bit register, syndrome registers, a four bit error counter which logs up to 15 errors, and an error data register which stores the complete error data word. Parity can be generated and checked on the system bus by the IDT49C466/A.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
DIAGNOSTIC & STATUS REGISTERS
ERR MERR READ BUFFER 16 WORDS BY 64 MD LATCH OUT
CHECK-BIT COMPARATOR & SYNDROME GENERATOR & ERROR DETECTOR M U X ERROR CORRECT
MD CHECK-BIT GENERATOR
MD CHK-BIT LATCH
CBI0-7
M U X
MD LATCH IN
SD0-63
WRITE BACK PATH SD LATCH IN WRITE BUFFER 16 WORDS BY 72 PARITY GENERATE & PARITY CHECK M U X B Y T E M U X SD CHECK-BIT GENERATOR
MD0-63 SD LATCH OUT
SD CHK-BIT LATCH
CBSYN0-7
PARITY P0-7
2617 drw 01 The IDT logo is a registered trademark and Flow-thruEDC is a trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
11.7
DSC-2617/9
1
8 CBI 0-7 MUX
ERR ERROR DETECT SYNDROME GENERATOR 8 ChkBit Latch Mode Bit 2 8 8 8
MD
MERR
MDOLE
MCLK
0-7 8-15 16-23 24-27 28-29 30-37 ERR MERR
MD Check Bit Generator
RBEN
RS 0-1
MDILE
RBREN
MUX
RBSEL
RBEF
Control
MUX
Diagnostic Registers Chkbit Syndrome (on 1st error) Err Count Err Type Syndrome (on every error) Error data
SYNCLK
RBFF RBHF
Read Fifo
64 wide CLEAR from mode register
SOE ERROR CORRECT
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
MUX
RWBD (Bit 4, Mode Reg)
0
DEMUX
1 SCLK
MD Latch Out
Write Back Path
BYTE MUX
1
MD Latch In
MD0-63
SD 0-63
SD Latch In
MUX
SDILE
0
SD Latch Out
MOE SDOLE
1
SD0-15
Write Fifo
72 wide control
Check Bit Injection Mode
BE0-7
8
WBEN WBREN
MCLK RS0-1 RWBD (Bit 4, Mode Reg)
8
8 PARITY GEN PARITY CHECK Mode Bit 5 MD to SD Path SD to MD Path Diagnostic path
WBFF WBEF
MUX
11.7
MUX
MODE REGISTER
BE0-7
CBSEL 8
0
MEN
SD
ChkBit Latch
0
SCLK
SD Check-bit Generator
CBSYN 0-7
1
WBSEL
P0-7
8
PERR
4 POWER SUPPLY VCC 17 GND
COMMERCIAL TEMPERATURE RANGES
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49C466/A 64-Bit Flow-ThruEDCTM
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
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PIN CONFIGURATION
GND MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 CBSYN7 CBSYN6 CBSYN5 CBSYN4 GND CBSYN3 CBSYN2 CBSYN1 CBSYN0 VCC GND WBSEL CBSEL WBREN GND WBEN SYNCLK WBFF WBEF SD63 SD62 SD61 SD60 P7 BE7 GND SD59 SD58 SD57 SD56 SD55 SD54 SD53 SD52 P6 BE6 SD51 SD50 SD49 SD48 SD47 VCC
GND MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 SDOLE MOE MDILE MD31 GND MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 GND MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 VCC 1 208 157 156
PQ208-2
52 53
105 104
GND SD46 SD45 SD44 BE5 P5 SD43 SD42 SD41 SD40 SD39 SD38 SD37 SD36 BE4 GND P4 SD35 SD34 SD33 SD32 PERR MCLK MDOLE RS1 MEN GND RS_0 SDILE SCLK SOE SD31 SD30 SD29 SD28 BE3 P3 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 BE2 P2 SD19 SD18 SD17 SD16 GND
GND MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 ERR MERR CBI7 CBI6 CBI5 CBI4 CBI3 GND CBI2 CBI1 CBI0 RBEN RBREN RBSEL GND VCC RBHF RBEF RBFF SD0 SD1 SD2 SD3 GND P0 BE0 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 BE1 P1 SD12 SD13 SD14 SD15 GND
PQFP Top View
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PIN DESCRIPTION
Pin Name Data Buses SD0-63 I/O System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output Enable, SOE, is HIGH or Byte Enable, BE0-7, is LOW, data can be input. When System Output Enable, SOE, is LOW and Byte Enable, BE0-7, is HIGH, the SD bus output drivers are enabled. Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE HIGH) memory data is input for error detection and correction. Data is output on the Memory Data Bus, when MOE is LOW. Check Bit Inputs: interface to the check bit memory. Check Bit/Syndrome Output: When MOE is LOW the generated check bits are output. When CBSEL is HIGH and MOE is HIGH, the syndrome bits are output. The bus is tristated when MOE = 1 and CBSEL = 0. Parity for bytes 0 to 7: These pins are parity inputs when the corresponding Byte Enable (BE) is LOW or SOE is HIGH, and are used to generate the parity error signal (PERR). These pins are outputs when the corresponding Byte Enable (BE) is HIGH and SOE is LOW. System Output Enable: enables system data bus output drivers if the corresponding Byte Enable (BE0-7) is HIGH. Byte Enable: is used along with SOE, to enable the System Data outputs for a particular byte. For example, if BE1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to the memory data bus. This is used during partial word write operations and writing corrected data back to memory. Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH, syndrome is selected. Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH. Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH transition of MDOLE. When MDOLE is LOW, the MD output latch is transparent. System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch on the LOW-to-HIGH transition of SDOLE. The latch is transparent when SDOLE is LOW. System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition. When SDILE is HIGH, the SD input latch is transparent. Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch is selected. Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge. Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising edge. Reset and Select pins (read and write FIFO FIFOs) RS1 RS0 Function 0 0 Reset 16-deep FIFO or first 8-deep FIFO 0 1 Reset second 8-deep FIFO 1 0 Select 16-deep FIFO or first 8-deep FIFO 1 1 Select second 8-deep FIFO
2617 tbl 01
I/O
Description
MD0-63
I/O
CBI0-7 CBSYN0-7
I O
P0-7
I/O
Control Inputs
SOE
I I
BE0-7
MOE
I
MDILE
MDOLE
I I I I I I I I
SDOLE
SDILE WBSEL
WBEN WBREN
RS0-1
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PIN DESCRIPTION (Continued)
Pin Name RBSEL
RBEN
I/O I I I I I
Description Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output latch). When LOW, the MD output latch is selected. Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH transition of the memory clock. Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH transition of SCLK Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is enabled. When CBSEL is LOW, MOE controls the buffer. Mode Enable Input: when LOW, SD0-15 is loaded into the EDC mode register on the LOW-to-HIGH transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure 4. Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO when RBEN is LOW. Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH transition of MCLK. System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when RBREN is LOW. Data on the system data bus is written into the write FIFO when WBEN is LOW on the LOW-to-HIGH transition of SCLK. Clocks data into mode register when MEN is LOW. Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset, SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One of the syndrome registers has new data clocked in on every SYNCLK rising edge. Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF goes LOW. Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, WBFF goes HIGH. Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF goes LOW. Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The flag will return HIGH when less than eight (or four) data words are in the FIFO. Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFF goes HIGH. Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally. Multiple Error Flag: when MERR is LOW, a multiple data error is indicated. The MERR is not latched internally. Parity Error Flag: when LOW, indicates a parity error on the system data bus input. Power Supply Voltage. Ground.
2617 tbl 02
RBREN
CBSEL
MEN
Clock Inputs MCLK I
SCLK
I
SYNCLK
I
Status Outputs
WBEF
O O O O
WBFF RBEF
RBHF
RBFF ERR MERR
O O O O P P
PERR
Power Supply VCC GND
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DETAILED DESCRIPTION --
64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART
Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X 48 X X X X X X X X X X X 49 50 51 52 X X X X X X X 53 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X X X X X X X X X
2617 tbl 05
(1, 2)
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X X X X X X X X X
2617 tbl 03
0 X X X
1 X X X
2 X X
3 X
4 X
5 X
6 X
7
8 X X
9 X
10 X
11 X
12 X
13
14 X
15
X X X
X X X X X X
X X X X
X
X X X X
X X X
X X X
X
X
X
X
X
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X 16 17 X X 18 X X X 19 X X X X X X X 20 21 X X X X X X X X X X X X X X X X X X X X X X X 22 23 24 X X X 25 X X X X X 26 27 X X X X X X X X X X X X
2617 tbl 04
28
29
30 X
31
X
Participating Data Bits 32 X X X X X X X X X X X 33 34 35 36 X X X X X X X 37 38 X X X X X X X X X X X 39 X X X 40 41 42 X X X X X 43 44 X X X X X X X X X 45 X 46 47 X
Participating Data Bits 54 X X X X X X X X X X X X X X X X X 55 X X X 56 57 58 X X X X X 59 60 X X X X X X X X X X X 61 X 62 63 X
NOTES: 2617 tbl 06 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit CB0 is the Exclusive-OR function of the 64 data input bits marked with an X. 2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an "X" in the table. 11.7 6
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DETAILED DESCRIPTION --
64-BIT SYNDROME DECODE TO BIT-IN-ERROR
HEX S7 S6 Syndrome Bits HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * C0 C1 T C2 T T M C3 T T 17 T M 16 T C4 T T 18 T 19 20 T T 21 22 T 23 T T M C5 T T 8 T 9 10 T T 11 12 T 13 T T M T 14 M T 15 T T M M T T M T M M T C6 T T M T M M T T M 33 T M T T 32 T M 34 T 35 T T 36 37 T T 38 T 39 M T T M 56 T 57 T T 58 59 T T 60 T 61 M T 62 T T M T 63 M T T M M T M T T M C7 T T M T M M T T M 49 T M T T 48 T M 50 T 51 T T 52 53 T T 54 T 55 M T T M 40 T 41 T T 42 43 T T 44 T 45 M T 46 T T M T 47 M T T M M T M T T M T M M T M T T M M T T 1 T M 0 T M T T 2 T 3 4 T T 5 6 T 7 T T M M T T 24 T 25 26 T T 27 28 T 29 T T M T 30 M T 31 T T M M T T M T M M T S5 S4 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0
(1)
3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 A 1 0 1 0 B 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1
NOTES: 2617 tbl 07 1. The table indicates the decoding of the eight syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single data bit-in-error T = Two errors detected M = Three or more detected C# = The number of the single checkbits in error
IDT49C466 OPERATION
The EDC is involved in two types of operation -- memory reads and memory writes. With the IDT49C466, both these can be accomplished by utilizing either of two possible data paths -- one incorporating the FIFO and the other without the FIFO. These operations are treated separately below. Memory Write The involvement of the EDC in this type of operation is relatively minimal since it does not call for any error checking. It only generates the check bits associated with each 64-bit wide data word. The EDC can be in generate-detect or normal mode for this operation. When a write operation is performed, it must be ensured that the SD output buffer (enabled by SOE and BE0-7) is disabled so that no attempt is made to simultaneously transfer read data onto the System Data (SD) Bus. When the write FIFO (WFIFO) is bypassed (WBSEL LOW), data passes through the SD Latch In. To latch data, the SDILE signal should be pulled LOW. The special case of a
partial word write or byte merge is discussed later. Here it is assumed that all 64 bits are being written. Consequently, BE0-7 must all be LOW. The data is fed to the SD Checkbit generator where appropriate checkbits are generated. Both system data and the generated checkbits can be latched by pulling the SDOLE signal HIGH. Asserting MOE enables the MD output buffer and data is output to the Memory Data (MD) bus. CBSEL (=1) or MOE(=0) need to be asserted to enable the CBSYN output buffer and output checkbits on CBSYN0-7. When the write FIFO is selected (WBSEL = 1), instead of asserting SDILE, WBEN is asserted and data is clocked into the write FIFO on the rising edge of SCLK. WBFF is asserted when the WFIFO is full and this inhibits further write attempts (see section on "Clock Skew" and "R/W FIFO Operation at Boundaries") to the WFIFO. When WBREN is asserted, data can be clocked out of the write FIFO on the rising edge of MCLK. WBEF is asserted when the WFIFO is empty and this inhibits further read attempts (see section on "Clock Skew") from the WFIFO.
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BEn = 0 BEn = 1 MD LATCH OUT PATH B
64
=> Path A => Path B MD BUS
64
PATH A
64
BYTE MUX
SD LATCH OUT
64
SD LATCH IN
64
M U X
64
64
BE0-7
WRITE BUFFER M U X
Figure 1. Byte Merge
WBSEL
8
2617 drw 05
Memory Read During a memory read, data and the corresponding input checkbits are read from the MD bus and CBI0-7, respectively. The memory and checkbit data may both be latched as they come in (MD Latch In and MD Checkbit latch) by the MDILE signal. Memory data is sent to the MD checkbit generator (where checkbits corresponding to the input data are generated) and to the error correct circuitry. The generated checkbits are X-ORed with the input checkbits to produce the syndrome word. This is sent to the error correction circuitry which generates the corrected data (normal mode). The corrected data is output to the SD bus via either of two data paths. When RBSEL is LOW, data flows through MD Latch Out. Pulling MDOLE HIGH latches this data. The output buffer is enabled by asserting SOE (=0) and BE0-7 (=1). Corrected data can be written back to memory by enabling the MD output buffer. In order to ensure selection of the write back path (Path B in figure 1) at the byte mux, BEO-7 should be all 1's while WBSEL = 0. If WBSEL = 1, buffered BEO-7 from the output of the write FIFO controls the byte mux. If the read FIFO (RFIFO) is selected (RBSEL HIGH), data is clocked into the FIFO (Read_FIFO Write) when RBEN is LOW, on the rising edge of MCLK. RBFF is asserted when the RFIFO is full and this inhibits further write attempts to the RFIFO (see section on "Clock Skew" and "R/W FIFO operation at Boundaries"). Data is clocked out of the FIFO (Read_FIFO Read) when RBREN is LOW on the rising edge of SCLK. RBEF is asserted when the RFIFO is empty and this inhibits further read attempts (see section on "Clock Skew") from the RFIFO. Note: In case of multiple error SD should be ignored in correct mode
Clock Skew A skew between the read and write clocks, as specified by tskew, is recommended. This specification is not a stringent one, in the manner of setup and hold times, but is important in preempting latencies at FIFO boundaries. For example - When a word is written to an empty FIFO, there is a finite delay before the FIFO is recognized as no longer being empty and hence allowing a read from the same FIFO. Similarly when a word is read from a full FIFO, there is a delay before a write can successfully be attempted. The tskew specification accounts for these cases. During cycles other than on full/empty FIFO boundaries, the clock skew is not required and the device functions correctly even when the reads and writes occur simultaneously. If the tskew specification is ignored and SCLK and MCLK were permanently tied together, there is an extra cycle latency in the cases mentioned above. Clock skew violation is illustrated in Figure 13. FIFO Write Latency The first data written to either of the (read or write) FIFOs, after the FIFO is reset, suffers a single clock latency. Data that is set-up with respect to the first clock is ignored and the data that is set-up with respect to the second clock edge after the reset, is stored as the first data in the FIFO (Refer to Figures 9 and 10). The empty-flag is deasserted after this second clock edge and 15 more data words (in a 16 deep configuration) can be written to the FIFO after this. The latency can be reduced or eliminated by providing a "dummy" or "set-up" clock edge before the actual write to the FIFO. The dummy write clock can be provided any time after reset and before the next buffer write operation takes place. The latency described here (shown in Figures 10 and 13) occurs only after a FIFO reset. In other cases where the FIFO becomes empty there is no latency.
8
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R/W FIFO Operation At Boundaries In the 49C466 the write pointer is incremented on every FIFO write. Similarly the read pointer is incremented on every FIFO read. In most cases on a FIFO read, the last data read remains at the output of the FIFO, until the read pointer is further incremented. On the last (the write that fills the FIFO) FIFO write after the FIFO read, however, this last read data is overwritten by the 16th write following the empty condition and consequently the data at the FIFO output is liable to change. The situation is depicted in the diagram below.
overwritten and the FIFO output changes from AA to the data just written, namely QQ. This operation needs to be taken into account in the design of the system. In case of a burst operation where FIFO data is output at a much slower rate than the rate at which data is input and the full flag is expected to inhibit further writes, the user cannot expect the FIFO output to remain static through the 16th write of the burst. If this is a requisite to the design, the FIFO output should be latched. In the case of the write FIFO this can be accomplished on-chip by latching the FIFO
WP reset RP WP WRITE1 (data = AA) RP WP FIFO (empty) RP WP WRITE1 (data = BB) RP WRITE2 (data =CC) RP WP WRITE15 (data = PP) RP WP WRITE16 (data = QQ) FIFO (full) No READs (data = QQ) FIFO No READs (data = AA) FIFO WP FIFO No READs (data = AA) No READs (data = AA) READ1 (data = AA) FIFO FIFO (empty)
Figure 2. R/W FIFO Operation
The diagram in figure 2 progresses from the FIFO initialization(reset) through a sequence of write operations. After the first write, a read is executed which establishes the data at the FIFO output(AA). On the last write to the FIFO(the write that fills the FIFO), the location of the last read data is
output in the SD output latch. For the read FIFO, the FIFO output must be latched externally to accomplish the same thing, since there is no latch on-chip following the FIFO. If this cannot be done and the situation described above is expected to occur in normal operation, the write must be inhibited one cycle before the FIFO becomes full.
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Partial Word Write/Byte Merge MODE REGISTER CONFIGURATION Writing a word shorter than 64 bits to memory is treated 15 7 6 5 4 3 2 0 as a special case. The checkbits generated for a data word RWBD CLEAR EDCM0-2 UNUSED RMODE PSEL shorter than 64 bits and written to a particular memory location differ from the checkbits that would be generated by the entire EDCM2 EDCM1 EDCM0 OPERATION 64-bit data word at the same location. Hence, the byte merge ERROR-DATA OUTPUT MODE 0 0 0 operation requires reading of the contents of the memory 0 0 1 DIAGNOSTIC-OUTPUT MODE 0 1 0 GENERATE-DETECT MODE location to be written to, merging the byte/bytes being written 0 1 1 NORMAL MODE 1 0 0 (from SD side) with the other component bytes previously at CHECKBIT-INJECTION MODE that memory location (from MD side), generating a checkbit word for this composite word and writing both the composite RMODE OPERATION 0 NOP data word and the generated checkbits to memory. The BEn 1 READ MODE REGISTER ON SD BUS bits supplied by the user determine the bytes that come from SD and those that come from MD, as illustrated in Figure 1. RWBD OPERATION EDC Modes 0 DUAL FIFOS (8) 1 SINGLE FIFO (16) The IDT49C466 has 5 modes of operation. Refer to table below for a description of the modes. The Error Data Output mode is useful for memory initialCLEAR OPERATION CLEAR NOP 0 ization as described below. In Checkbit Injection mode, the CLEAR ALL DIAGNOSTIC REGISTERS 1 MD Checkbit Latch is loaded with data from the System Bus. This serves to verify the functioning of the EDC. Any discrepancy between the injected checkbits and generated checkbits PSEL OPERATION 0 EVEN PARITY should result in assertion of the ERR, MERR signals. 1 ODD PARITY These modes and certain other features such as clear, 2617drw 06 buffer configuration, etc., can be selected by appropriately loading the Mode Register. The Mode Register can be written to by asserting MEN. Then SD0-15 is clocked into the mode register on the rising edge of SCLK.
OPERATING MODE DESCRIPTION
Mode MODE 0 Description Error-Data Output Mode: This mode allows the uncorrected data captured from an error event by the Error-Data Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by setting the mode register "'clear"-bit. Diagnostic-Output Mode: In this mode, contents of latch and five internal registers are read by the system for diagnostic and error logging purposes. Internal data paths allow output from the CBI LATCH to be read directly by the system bus for diagnostic purposes. The contents of the internal diagnostic checkbit register, syndrome registers, error count register and error-type register are also output on the SD bus. Generate-Detect Mode: (Detect-Only) The EDC performs checkbit generation during a memory write, and performs error detection only during a memory read. Normal Mode: The EDC performs checkbit generation during memory writes and error detection and correction during memory reads. Checkbit-Injection Mode: In this mode, the checkbit latch is loaded with desired 8-bit data from the SD bus.This eight bit data passes through SD Latch in or write FIFO to the MD check bit latch. By inserting various checkbit values, correct functioning of the EDC can be verified "on-board". The rest of the operation is similar to regular memory reads. The EDC compares the injected checkbits against the internally generated checkbits. Any discrepancy in the injected checkbits and the internally generated checkbits will cause the ERR / MERR to go LOW.
2617 tbl 08
MODE 1
MODE 2 MODE 3 MODE 4
Memory Initialization Memory initialization involves clearing all memory data locations and writing the corresponding checkbits (checkbits corresponding to all zero data = $0C) to checkbit memory. This can be done using the 49C466 to first create an "all-zero-data" source. This is done by setting the CLEAR bit in the mode register. This clears all diagnostic registers. Then this data can be written back to memory in the Error-Data output (Mode 0) mode. In order to wrap the all-zero data back to the MD bus, BE07 should be high and WBSEL =0.
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MODE BIT 0
CLEAR
MUX
Diag. Regs. Error Data Regs. SYNCLK
MUX
64
BE0-7
MUX
WFIFO
BE0-7
WBSEL
Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode
DIAGNOSTIC OUTPUT DATA FORMAT
TO SD BUS
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Error Checkbit Error Syndrome Checkbit Syndrome Type (from checkbit latch) Count (on 1st error) (on 1st error only) (on every error) (on 1st error only)
* Bit #28 = 1 If "Error" condition Bit #29 = 1 If "Multiple bit Error" condition
FROM DIAGNOSTIC REGISTERS
2617 drw 07
Diagnostics The diagnostic ability of the IDT49C466 rests on a set of 6 registers that provide error logging information. These include the checkbit register, error count register, error type register, 2 syndrome registers and the error data register. Data is clocked into each of these registers by SYNCLK. The error data register, checkbit register, error type register and one of the syndrome registers are reloaded only in the case of the first error after a clear. The other syndrome register and the error count register are reloaded on every error condition SYNCLK edge. The contents of the Error Data register can be read only in Error Data Output mode. The contents of the other diagnostic registers as well as the checkbit latch can be read in Diagnostic Output mode. Parity The IDT49C466 provides a parity check and generation facility. On a memory read the EDC generates parity bits for each data byte and outputs the parity byte on the parity bus, P0-7. During a memory write, parity is checked by comparing the parity bits input on P0-7 and the parity bits generated from the input data word. A discrepancy between these two causes the PERR flag to be asserted. In the case of partial word writes, the PERR flag is based on the parity bits Px and data bytes input on SD bus.
11.7
DIAG. REGISTER CHECKBIT
LOADED BY SYNCLK
CONDITION
OUTPUT
ONLY ON 1st ERROR ONLY ON 1st ERROR
SD8-15
SYNDROME (On 1st ERR)
SYNCLK
SD16-23
ERR CNT
SYNCLK
ON EVERY ERROR (Up to 15 ERRORS) ONLY ON 1st ERROR ON EVERY ERROR
SD24-27
ERR TYPE
SYNCLK
SD28-29
SYNDROME (On every ERROR)
SYNCLK
SD30-37
11
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TBIAS TSTG IOUT Rating Power Supply Voltage Terminal Voltage with Respect to Ground Temperature Under Bias Storage Temperature DC Output Current Com'l. -0.5 to +7.0 -0.5 to VCC + 0.5 -55 to +125 -55 to +125 30 Unit V V
CAPACITANCE (TA = +25C, f = 1.0 MHz)
Symbol CIN COUT C C mA Parameter(1) Input Capacitance Output Capacitance
NOTE: 1. This parameter is sampled and not 100% tested.
2617 tbl 10
Conditions VIN = 0V VOUT = 0V PQFP PQFP
Typ. 5 7
Unit pF pF
NOTE: 2617 tbl 09 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Ratings for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOZ IOS VOH VOL VH Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Off State (Hi-Z) Output Current Short Circuit Current Output HIGH Voltage Output LOW Voltage VCC = Max. , VOUT= 0V VCC = Min., VIN = VIH or VIL VCC = Min. VIN = VIH or VIL Input Hysteresis on input control lines -- 200 -- mV
2617 tbl 11
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max., VIN = 2.7V VCC = Max., VIN = 0.5V VCC = Max.
(3)
Min. 2.0 -- -- --
Typ.(2) -- -- 0.1 -0.1 -0.1 0.1 -- 3.6 0.3
Max. -- 0.8 5.0 -5.0 -10 10 -150 -- 0.5
Unit V V A A A mA V V
VO = 0V VO = 3V IOH = -2mA IOL = 8mA
-- -- -20 2.4 --
NOTES: 1. For conditions shown as min. or max., use appropriate Vcc value. 2. Typical values are at VCC = 5.0V, +25C ambient temperature. 3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con't)
The following conditions apply unless otherwise specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%
Symbol ICCQC ICCQT ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Input Levels Dynamic Power Supply Current Test Conditions(1) VIN = VCC, or VIN = GND VCC = Max. VIN = 3.4V VCC = Max. VIN = VCC, or VIN = GND VCC = Max. f = 10MHz Correct Mode
NOTES: 1. For conditions shown as Min. or Max., use appropriate Vcc value. 2. Typical values are at VCC = 5.0V, +25C ambient temperature.
2617 tbl 12
Min. -- -- --
Typ.(2) 3.0 0.3 --
Max. 15 1 100
Unit mA mA/ Input mA
11.7
12
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
AC PARAMETERS PROPAGATION DELAY TIMES
Number Parameter From Input(1) GENERATE (WRITE) PARAMETERS Without Write FIFO: 1 2 3 4 5 6 7 8 9 tBC tBM tPPE tSC tSM tSPE tMC tMMD tWBSEL BEn BEn Pxin SDin SDin SDin MCLK (Lo-Hi) MCLK (Lo-Hi) WBSEL CBSYN (chkbit) MDOUT PERR CBSYN (chkbit) MDout
PERR
Description To Output
49C466 Max. Com'l.
49C466A (50MHz) Max. Com'l.
Unit
20 16 10 22 22 16 25 25 18
15 13 8 15 15 12 18 18 13
ns ns ns ns ns ns ns ns ns
With Write FIFO: CBSYN (chkbit) MDout MDout
DETECT (READ) PARAMETERS Without Read FIFO: 10 11 12 13 14 15 16 tWYC tME tMME tCE tCME tSSD tRBSEL SYNCLK (Lo-Hi) MDin MDin CBI CBI SCLK (Lo-Hi) RBSEL CBSYN (syndr)
ERR MERR ERR MERR
16 20 22 13 13 22 18
12 12 14 9 9 13 13
ns ns ns ns ns ns ns
With Read FIFO: SDout SDout
CORRECT (READ) PARAMETERS Without Read FIFO: 17 18 19 20 tCS tMP tMS tSP CBI MDin MDin SCLK (Lo-Hi) SDout Pxout SDout Pxout 20 22 22 22 16 18 16 15 ns ns ns ns
2617 tbl 13
With Read FIFO:
NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
11.7
13
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
PROPAGATION DELAY TIMES FROM LATCH ENABLES
Description Number 21 22 23 24 25 26 27 28 29 30 Parameter tMLE tMLME tMLP tMLS tMOLS tMOLP tSLC tSLM tSOLC tSOLM From Input(1) MDILE (Lo-Hi) MDILE (Lo-Hi) MDILE (Lo-Hi) MDILE (Lo-Hi)
MDOLE MDOLE
49C466 Max. Com'l. 16 18 24 22 18 18 20 20 12 15
49C466A (50MHz) Max. Com'l. 13 15 18 17 9 11 15 12 8 8 Unit ns ns ns ns ns ns ns ns ns ns
2617 tbl 14
To Output
ERR MERR
Px SDout SDout Px CBSYN (chkbit) MDout CBSYN (chkbit) MDout
(Hi-Lo) (Hi-Lo)
SDILE (Lo-Hi) SDILE (Lo-Hi)
SDOLE SDOLE
(Hi-Lo) (Hi-Lo)
NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
R/W FIFO TIMES
Number Parameter 31 32 33 34 35 39 tRSF tSKEW1 tSKEW2 tEF tFF tHFF From Input(1) RS1 (Hi-Lo) during SCLK LOW RCLK (Lo-Hi) (SCLK or MCLK) WCLK (Lo-Hi) (SCLK or MCLK) R/WCLK (Lo-Hi) (SCLK or MCLK) R/WCLK (Lo-Hi) (SCLK or MCLK) R/WCLK (Lo-Hi) (SCLK or MCLK)
NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
2617 tbl 15
Description To Output
EF
Min. -- 10 10 -- -- --
49C466 Com'l. Max. 16 -- -- 15 15 15
49C466A (50MHz) Com'l. Min. Max. -- 9 9 -- -- -- 16 -- -- 12 12 12
Unit ns ns ns ns ns ns
(Hi-Lo)/FF (Lo-Hi)
WCLK (Lo-Hi) (SCLK or MCLK) RCLK (Lo-Hi) (SCLK or MCLK)
EF
FF
HF
11.7
14
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
BYTE MERGE TIMES
Number 36 37 38 Parameter tSCM tMDM tRBM Description (1) From Input To Output SCLK (Lo-Hi)
MDOLE
49C466 Max. Com'l. 25 18 23
49C466A (50MHz) Max. Com'l. 18 14 15
Unit ns ns ns
2617 tbl 16
MDout MDout MDout
(Hi-Lo)
RBSEL
NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
ENABLE AND DISABLE TIMES
Description Number Parameter 40 41 42 43 44 45 46 47 48 49 50 51 tBESZx tBESxZ tBEPZx tBEPxZ tSEPZx tSEPxZ tCECZx tCECxZ tMEMZx tMEMxZ tSESZx tSESxZ
SOE MOE MOE SOE
49C466 Com'l. Min. * Hi-Z * Hi-Z * Hi-Z * Hi-Z * Hi-Z * Hi-Z -- -- -- -- -- -- -- -- -- -- -- -- Max. 22 22 15 15 14 14 12 10 22 18 16 20
49C466A (50MHz) Com'l. Min. -- -- -- -- -- -- -- -- -- -- -- -- Max. 12 12 10 8 10 8 10 8 10 9 10 9
2617 tbl 17
From Input(1) BEN = BEN = = = = = High Low High Low Low High Low High Low High Low High
To Output SDout Pout Pout CBSYN MDout SDout
Unit ns ns ns ns ns ns
NOTES: 1. (High-Z) indicates high impedence. 2. * indicates delay to both edges.
11.7
15
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
SET-UP AND HOLD TIMES
Description Number 52 53 54 55 56 57 58a 58b 59a 59b 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 93 94 Parameter tCMLS tCMLH tMMLS tMMLH tCMOLS tCMOLH tMMOLS tMMOLS tMMOLH tMMOLH tMMCS tMMCH tSSLS tSSLH tSSCS tSSCH tSSOLS tSSOLH tSCSD tMCSD tENS tENH tRSS tMODS tMODH tMENS tMENH tMSDS tMSDH tBSCS tBSCH From Input(1) CBI Set-up CBI Hold MDIN Set-up MDIN Hold CBI Set-up (Correct) CBI Hold (Correct) MDIN Set-up (Detect) MDIN Set-up (Correct) MDIN Hold (Detect) MDIN Hold (Correct) MDIN Set-up MDIN Hold SDIN Set-up SDIN Hold SDIN Set-up SDIN Hold SDIN Set-up SDIN Hold SCLK (Lo-Hi) MCLK (Lo-Hi) R/W FIFO Enable Set-up R/W FIFO Enable Hold RS1 (Lo-Hi) Mode Data Set-up Mode Data Hold Mode Enable Set-up Mode Enable Hold MDIN Set-up MDIN Hold BE Set-up BE Hold To Output before MDILE = after MDILE = before MDILE = after MDILE = before MDOLE = after MDOLE = before MDOLE = before MDOLE = after MDOLE = after MDOLE = before MCLK = after MCLK = before SDILE = after SDILE = before SCLK after SCLK before SDOLE = after SDOLE = before SDOLE = before SDOLE = before S/M CLK = after S/M CLK = R/WCLK = before SCLK = after SCLK = before SCLK = after SCLK = before SDOLE = after SDOLE = before SCLK = after SCLK = Hi-Lo Hi-Lo Hi-Lo Hi-Lo Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Hi-Lo Hi-Lo Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi Lo-Hi 49C466 Min. Com'l. 2 6 2 6 12 2 10 12 4 4 10 4 5 3 2 6 8 0 14 14 4 4 6 4 4 4 4 22 0 1 6 49C466A (50MHz) Min. Com'l. 1.5 1.5 1.5 1.5 8 0 5 12 0 0 10 0 1.5 1.5 1 2 6 0 12 10 2 2 2 2 2 2 2 20 0 1 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DIAGNOSTIC SET-UP AND HOLD TIMES 79 80 81 82 83 84 tCSCS tMSCS tMLSCS(2) tCSCH(2) tMSCH
(2)
CBI Set-up MDIN Set-up MDILE = Lo-Hi Set-up CBI Hold MDIN Hold MDILE = Lo-Hi Hold After SYNCLK= Lo-Hi before SYNCLK = Lo-Hi
4 10 10 6 6 6
2 8 8 2 2 2
ns ns ns ns ns ns
tMLSCH(2)
NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
2617 tbl 18
11.7
16
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
MINIMUM PULSE WIDTH
Description Number 86 87 88 89 90 91 92 Parameter From Input(1) tRS tMLE tMDOLE tSLE tCLK tSYNCLK tSDOLE Min. RS1 LOW time Min. MDILE HIGH time Min. MDOLE LOW time Min. SDILE HIGH time to reset buffers to strobe new data to strobe new data to strobe new data Condition -- MD, CBI = Valid -- SD = Valid EN signal LOW -- -- 49C466 Min. Com'l. 6 6 6 6 6 6 6 49C466A (50MHz) Min. Com'l. 5.0 5.0 5.0 5.0 6.0 5.0 5.0 Unit ns ns ns ns ns ns ns
2617 tbl 19
Min. S/MCLK HIGH time to clock in new data Min. SYNCLK HIGH time to clock in new data Min. SDOLE LOW time to clock in new data
11.7
17
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 1V/ns 1.5V 1.5V See Figure 15
2617 tbl 21
SD0-15
SDin (Mode)
tMODH tMODS SCLK tMENH tMENS
MEN
2617 drw 08
Figure 4. Mode Enable Timing
WBSEL
SOE
write
SCLK (WCLK) tSSCS tSSCH SD0-63 SDin
tENH
WBEN
tENS
tFF
WBFF
tFF tSKEW1 read
MCLK (RCLK)
WBREN
2617 drw 09
Figure 5. WFIFO Write Timing (Write Cycle)
11.7
18
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
MCLK (RCLK) ______ WBREN
read
tENS
tENH tEF
_____ WBEF WBSEL ______ SDOLE ____ MOE
t EF
t MCSD t
MEMxZ
t MMD t MEMZx
MD0-63 MDout D1
t CECZx
CBSYN0-7 write
t MC t SKEW2
Valid Checkbits out
SCLK (WCLK)
2617 drw 10
Figure 6. WFIFO Read and Checkbit Generate Timing (Write Cycle)
11.7
19
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
RBSEL
____ MOE
t MEMxZ
MD0-63 MDout MDin
t MMLS
CBI0-7
t MMLH
Checkbits in
t CMLS
MDILE
t CMLH
t MMCS
write MCLK (WCLK)
t MMCH
t ENH
_____ RBEN
t ENS tFF
_____ RBFF
t SKEW1
SCLK (RCLK)
read
2617 drw 11
Figure 7. RFIFO Write Timing (Read Cycle)
11.7
20
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
read SCLK (RCLK) tENH tENS
RBREN
tEF
RBEF
write MCLK (WCLK)
tEF
tSKEW2 RBSEL tSSD
SOE
tSESZX BE0-7 tBESZX SD0-63 tSEPZX tBEPZX P0-7 Parity out
2617 drw 12
SDout (corrected data)
Figure 8. RFIFO Read Timing (Read Cycle)
11.7
21
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
RS1
t RS
WCLK (SCLK / MCLK) __ EF __ FF
t RSS
dummy write
t RSF t RSF
Figure 9. FIFO (WFIFO/RFIFO) Reset Timing
DATA (SD/MD)
dataxx
data1
t SSCS
dummy write write
t SSCH
WCLK (SCLK/MCLK)
t ENS
BUFFER ENABLE _____ _____ (WBEN/ RBEN)
t RSF
FIFO RESET (RS1)
BUFFER EMPTY ____ _____ FLAG (WBEF/ RBEF)
t EF
2617 drw 14
Figure 10. FIFO (WFIFO/RFIFO) Write Latency Timing
11.7
22
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
BE0-7
Valid BE0-7
SOE
SD0-63
SDin Dy tSSCS tSSCH
SDILE
SDOLE
external tristate MD0-63 MDin Dx MDout Dxy
tMEMZX
MOE
tMEMXZ
tMMOEmin1 MDILE tMMOLS
MDOLE
tMMOLH
RBSEL
WBSEL
2617 drw 15
Figure 11. Partial Word Write/Byte Merge Timing NOTE: 1. tMMOE is not a propagation delay. For partial word write operations tMMOE MIN= tMDM.
11.7
23
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
tBM BE0-7 Valid BE0-7
SOE
tSESXZ
SD dummy write SCLK
Data xx tSSCS tSSCH write data read data
MCLK tENS
WBEN
tENH
WBREN
tENS tENH
tCSM = tMMD WBSEL tMMCS MD tMMCH Merged Data xx+yy
Data yy
RBEN
tENS
tENH
RBREN
tENS tENH
RBSEL
MOE
tMEMXZ
2617 drw 25
Figure 12. Partial Word Write/Byte Merge Timing using both RFIFO and WFIFO
11.7
24
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
SD0-63
invalid data dummy write
SDin 1
SDin 2
t SSCS
1
t SSCH
2
SCLK (WCLK)
t RSS
RS1
tRSF
_____ WBEF MCLK (RCLK) _____ WBREN
t EF
1 ignored (no skew)
2617 drw 20
Figure 13. Write FIFO Write Timing with Clock Skew Violation
MD0-63
MDin
t MSCS
CB0-7 CBin
t MSCH
t CSCS
MDILE
t CSCH t MLSCH t SYNCLK
2617 drw 21
t MLSCS
SYNCLK
Figure 14. Diagnostic Timing
11.7
25
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2617 drw 16
SWITCH POSITION
Test
7.0V
Switch
Open Drain Disable Low Enable Low All Other Tests
Closed Open
VOUT
500
2617 tbl 20 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2617 drw 17
PULSE WIDTH
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
tSU
tH
2617 drw 18
PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2617 drw 26
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 0V
2617 drw 27
DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V VOH VOL
tPLZ 3.5V 1.5V
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
11.7
26
IDT49C466/A Flow-thruEDCTM ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 49C466 Device Type X Speed XX Package X Process/ Temperature Range BLANK Commercial (0C to +70C)
PQF
Plastic Quad Flatpack
Blank A
Standard speed 50MHz speed
49C466
64-Bit Flow-thruTM EDC
2617 drw 19
11.7
27

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