View MAS9181B_108441.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DA9181.006 13 October, 1999
The MAS9181 comprises eight digital to analog 2 converters (DACs) each controlled by a two-wire I C bus. The DACs are individually programmed using an 8bit word to select an output from one of 256 voltage steps. The maximum output voltage of all DACs is set
* Rail to rail output stages * Octal 8-bit DACs on a single monolithic chip * Power supply range from +5 V to +12 V * -20C to +85C temperature range * 16-pin PDIL and SO package * Power-up reset
SDA SCL A0 A1 A2
I C Bus Slave Receiver
8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC
Reference Voltage Generator
8-BIT DAC 8-BIT DAC
VDD GND
p h s h r wq c e vShC a C X8 Pig 8P8h ECiyhc PCfwg E8qE8Eb wfcx U@Yv 86t p dd e u UVWUSQ PQ P8G ECECA @86 G TR D IH 9FDB 97 543010 ((# (&%#! ' )2 ' ) ' $" | (c) iWh PCdg iPd f fe
* Trimmer replacement * AGC/AFT or TVs and VCRs * Graphic equalizers * High resolution monitors
{
z myxwv
urts qp on k PWr C@mlEj
W Pi ECiC
by Vmax and the resolution is Vmax/256. At power-on all 2 outputs are set to their lowest value. The I C-bus slave receiver has 3 programmable address pins (2 for MAS9181 CS).
iEEPCi
8-BIT DAC
DAC7
8-BIT DAC
DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
1
DA9181.006 13 October, 1999
VDD
1 2 3 4 5 6 7 8 9
1 2 3 4 6 7
P I I/O I I I I G O O O O O O O O
Positive supply voltage Control input for DAC maximum output voltage I C bus serial data input/output I C bus serial data clock Programmable address bits for I C bus slave receiver Programmable address bits for I C bus slave receiver Programmable address bits for I C bus slave receiver Ground Analog voltage output Analog voltage output Analog voltage output Analog voltage output Analog voltage output Analog voltage output Analog voltage output Analog voltage output
2 2 2 2 2
Vmax SDA SCL A0 A1 A2 GND DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7
*1 MAS9181BN (PDIP16) *2 MAS9181CS (SO16)
NC 8 9 10 11 12 13 14 15 16
10 11 12 13 14 15 16
x

E ~ } } } W 88| Ed8C~ P|
~ } }~ } W PCPEW iEWES~ P|
PDIP 16 VDD 1 Vmax 2 SDA 3 SCL 4 A0 5 A1 6 A2 7 GND 8
MAS9181BN
16 DAC7 15 DAC6 14 DAC5 13 DAC4 12 DAC3 11 DAC2 10 DAC1 9 DAC0
SO16
MAS9181CS
VDD Vmax SDA SCL NC A0 A1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
2
DA9181.006 13 October, 1999
Supply Voltage Supply current
VDD IDD
-0.5 -10
I C-bus line voltage Input voltage Output voltage Maximum current on any pin total power dissipation Operating ambient temperature range Storage temperature range
2
V(3),V(4) Vin Vo Imax Ptot Tamb Tstg
-0.5 -0.5 -0.5
Supply Voltage Supply current Total power dissipation
VDD IDD Ptot No loads, Vmax=VDD=12V, All data=00OCT No loads, Vmax=VDD=12V, All data=00OCT
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
Input voltage range Input low voltage Input high voltage Input leakage current Power-up reset
VI VIL VIH IIL Vin = 0V or VDD
-0.5
3.0 -1 3.5 +1
$#75 43!1$ )( &6 |( 20 &
o
C
4.5
AE PA 3/41/4AAA CA1/4 A A 3/4
18 V 40 5.9 V V VDD+0.5 VDD+0.5 10 500 -20 -65 +85 +150
o o
mA mW C C
x # tH )
o y oy uo u yx oy u u u uu o o/ P o mooPnn i ii miee Ue e caeaaO YaUaUU U a U axxU U UUY U U OO x O OO O o O N NIO E O N IEEIE I I I IEEE dOWE P CWEESWE 8EPPdWqdECCE%UWE8EE
12 3.0 40
13.2 5.0 60
V mA mW
5.5 1.0
V V V A V
3
C
1/4 3/4 3/41/2x1/4
' & &!#" $ %$ ! x f #
! (c)
x* E (R) (c) | C PCPE% d@PdWCd
Q FD FE DBGEGPB 9G FE B89 4B @@Q H8C4)@)@)I)HB @D4CA@8 v !y rp q d 4Y U h V fX !U )Af Acb i WV h ge d a Y X !U TR WV S (c) | | u w v ut w x t s
(conditions)
DA9181.006 13 October, 1999
Input voltage range Input low voltage Input high voltage Input current low Input current high
VI VIL VIH IIL IIH
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
Pin 2 current
I2
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
DAC output (pin 9 to 16) Output voltage range Output impedance DAC output drive range Output capacitive load
Vo
Io = +/- 100 A Io = +/- 500 A
Zo Io Co
data = 7F Upper side saturation voltage= 0.2v Low side saturation voltage = 0.2v -1
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
Output voltage low
VOL
I3 = 3.0 mA
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
Differential nonlinearity Integral nonlinearity Zero code error
1 1 1
DNL INL ZCE PSRR TCo
Io = 0 (without load) Vmax = VDD-1.0 Io = 0 (without load) Vmax = VDD-1.0 data = 00
-1.5 10
Power supply rejection
Zero code temperature coefficient
-200
Note 1: Guaranteed by design but not production tested
# |H )
*#3/4 H* ) 1/21/4
I O#U EHO )x OU x UIO O
i !o#yy 4uuo )o o eo uiu o
)&968 764' 2 ' 2 53 )
1" ) )0( '$&% ' "
!#
!# * *
O O I O!#O O OO
/o o on !n o i fo #o
! 4 ! ! ! #f! ! ! ! !#) b (c) |
#" $!
i fd fe dgegh g fe 4 @@i HC4)@)@)I)H @d4CA@ on e i!i ! ~ ! (R) N!I I EI z w wv n u t rq o y x Hp !q s !p )n n m !bj lkk
(All voltages are with respect to GND; Tamb = -20 oC to 85 oC; VDD = 5V to 12V unless otherwise specified)
ae4a aa fa !a a HbU c a a a Y
} ~ }| | { (R) E E E EE E I E C e i e ee i i e e (c) AE A !A A HAA A AA |
0
VDD 1.0
V V V
3.0 -10 -15 1
A A
7
10
A
0.1 0.2 30
VDD-0.1 VDD-0.2
V V
1 2
mA nF
0.4
V
-1
1 1.5 30 5 200
LSB LSB mV mV/V V/ C
o
4
DA9181.006 13 October, 1999
Bit Transfer on the I C-bus
SDA
SCL Data line stable (data valid) Change of data allowed
Complete Data Transfer
SDA
SCL
S
Start condition
1-7
8
9
1-7
8
Address
R/W
Ack
Data
t
s r p! pq Ph Wd c Sa i gfe b
WU T SQ YXV R IB EDCBA PHG F77&@
The MAS9181 I C-bus interface is a receiver- only slave. Data is accepted from the I C - bus in the following format. S 0 1 0 0 A2 A1 A0 0 Address byte A I3 I2 I1 I0 SD SC SB SA Instruction byte A D7 D6 D5 D4 D3 D2 D1 D0 First data byte A P
2 2
S P A
Start condition Stop condition Acknowledgement
A2, A1, A0 I3, I2, I1, I0 SD, SC, SB, SA D7, D6, D5, D4, D3, D2, D2, D1, D0
programmable address bits instruction bits sub-address bits data bits
9
1-7
8
9
P
Ack Data Ack Stop condition
5
DA9181.006 13 October, 1999
Valid addresses are 40, 42, 44, 46, 48, 4A, 4C, 4E(hex), depending on the programming of bits A2, A1 and A0. With these addresses, up to eight MAS9181 ICs can be 2 operated independently from one I C-bus. No other addresses are acknowledged by the MAS9181. The
Valid instructions from 00 to 0F and F0 to FF (hex); MAS9181 will not respond to other instruction value, but will still generate an acknowledgement. Instructions 00 to0F cause auto-incrementing of the sub-address (bits SD to SA) when more than one data byte is sent within one transmission. With auto-incrementing, the first data byte is written into the DAC addessed by bits SD to SA and then the sub-address is automatically incremented by one position for the next databyte in the series. Auto-
Input SCL (pin 4) and input/output SDA (pin 3) conform 2 to I C-bus specifications. Pins 3 and 4 are protected against voltage pulses by internal zener diodes
Input Vmax (pin 2) provides a means of comprising the output voltage swing of the DACs. The maximum DAC output voltage is restricted to approximately Vmax while
m l i 7h g fe d S k ij ji
$ $
address inputs A0, A1 and A2 are programmed by connection to GND for An = 0 or to VDD for An = 1. If the inputs are left floating, An = 1 will result. For MAS9181CS, A2 is always 1. incrementing does not occur with instructions F0 to FF. The DAC addressed by the sub-address will always receive the data if more than one data byte is sent. Valid sub-addresses (bits SD to SA) are 0 to 7 (hex) relating numerically to DAC0 to DAC7. When the autoincrementing function is used, the sub-address will sequence through all possible values (0 to F, 0 to F, etc.). While the sub-address is between 8 and F no DAC outputs change.
w yxwv PH F77&u }&{ x Sv ~ | zy w u Wq p Sn tsr o
connected to the ground plane and therefore the normal bus line voltage shall not exceed 5.5V. the 8-bit resolution is maintained, therefore giving a finer voltage resolution of smaller output swings.
6
DA9181.006 13 October, 1999
H F7H H F7P FP
+12v VDD 100nF +5v GND DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 7 A2 A1 A0 SCL +12v SDA 100nF DAC1 DAC0 6 16 15 14 13 12 11 10 9
Micro Controller
5k
5k
Clock
5 4 3
Data
MAS9181
7
DA9181.006 13 October, 1999
1.52
2.93 4.95
5.33 MAX
0-0.13 RAD.
7.62 BSC
0.254
5.5
5 TYP.
2.36 2.64
10.11 10.49
0.25 RAD. MIN.
0.94 1.12
5 TYP. 5 TYP.
. 0.8 6 T Y P
10.01 10.64
PIN 1
ALL MEASUREMENTS IN mm
7.39 7.59
0.10 0.30
PHHF&
16 LEAD PDIP OUTLINE (300 MIL BODY)
6.10 7.11 18.93 21.33 5-7 SEATING PLANE 0.36 0.56 1.15 1.77 2.54 BSC 0.63 TYPICAL 1 PIN
16 LEAD SO OUTLINE (300 MIL BODY)
5TYP 1.27 5 TYP. TYP. 0.36 0.48
0.33 x 45
SEATING PLANE
8
DA9181.006 13 October, 1999
MAS9181BN
MAS9181CS
OCTAL 8-BIT TRIMMER-IC
OCTAL 8-BIT TRIMMER-IC
16 Pin PDIP 0.3"
16 Pin SO 0.3" 2 Address Pins
Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-02771 ESPOO, FINLAND http://www.mas-oy.com
Tel. (09) 80 521 Tel. Int. +358 9 80 521 Telefax +358 9 805 3213 E-mail: info@mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
* (R) &
9

AAC E &7PHIIPEPPEE&F!AE7 3/4AA A A E C A
H !H&7 F7H |
(R) $ $&$(R) $ $ (c) (c)
A AA 3/4AA 3/41/4 HPA P 71/2!P

▲Up To Search▲

Price & Availability of MAS9181B

	To Download MAS9181B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .