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19-2485; Rev 1; 10/02
Triple-Output TFT LCD Power Supply with Fault Protection
General Description
The MAX1889 provides the three regulated output voltages required for active matrix, thin-film transistor liquid crystal displays (TFT LCDs). It combines a high-performance step-up regulator with two linear-regulator controllers and multiple levels of protection circuitry for a complete power-supply system. The main DC-DC converter is a high-frequency (500kHz/1MHz), current-mode step-up regulator with an integrated N-channel power MOSFET that allows the use of ultra-small inductors and ceramic capacitors. With its high closed-loop bandwidth performance, the MAX1889 provides fast transient response to pulsed loads while operating with efficiencies over 85%. The positive and negative linear-regulator controllers postregulate charge-pump outputs for TFT gate-on and gate-off supplies. The MAX1889 has a unique input switch control that can replace the typical input fuse by disconnecting the load from the input supply when a fault is detected. The fault detector monitors all three regulated output voltages and can monitor current from the input supply as well. Additionally, the MAX1889 enters thermal shutdown when its overtemperature threshold is reached. The MAX1889 undervoltage lockout is set at 2.5V (max) to allow the input supply to droop under pulsed load conditions while avoiding any unexpected behavior when its input voltage dips momentarily. Also, the builtin soft-start and cycle-by-cycle current limiting prevent input surge currents during power-up. The MAX1889 is available in a 16-pin thin QFN package with a maximum thickness of 0.8mm for ultra-thin LCD panel design.
Features
o High-Performance Step-Up Regulator Fast Transient Response Current-Mode Control Architecture Built-In High-Efficiency N-Channel Power MOSFET Current-Limit Comparator >85% Efficiency Selectable Switching Frequency (500kHz/1MHz) Internal Soft-Start o Positive Linear-Regulator Controller o Negative Linear-Regulator Controller o Triple-Level Protection Against Smoke or Fire Input Switch Replaces Input Fuse Output Overload Detection with Timer Latch Thermal Shutdown o 2.7V to 5.5V Input Operating Range o o o o Ultra-Small External Components 1A Shutdown Current (max) 1mA Quiescent Current (max) Ultra-Thin 16-Pin QFN Package (0.8mm Maximum Thickness)
MAX1889
Ordering Information
PART MAX1889ETE MAX1889EGE* TEMP RANGE PIN-PACKAGE -40C to +85C -40C to +85C 16 Thin QFN (5mm 5mm) 16 QFN (5mm 5mm)
* Future product--Contact factory for availability.
Applications
LCD Monitors Car Navigation Displays
SHDN PGND GND REF 1 2 16 IN
Pin Configuration
OCN 13 12 TGND 11 LX 10 FREQ 9 5 FB 6 FBN 7 DRVN 8 DRVP FBP OCP 14
TOP VIEW
15
MAX1889
3 4
THIN QFN (5mm x 5mm)
________________________________________________________________ Maxim Integrated Products
GATE
Notebook Computer Displays
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
ABSOLUTE MAXIMUM RATINGS
IN, SHDN, OCN, OCP, FB, FBP, FBN, FREQ to GND ...............................-0.3V to +6V PGND to GND.....................................................................0.3V LX to PGND ............................................................-0.3V to +14V DRVP to GND .........................................................-0.3V to +30V REF, GATE, TGND to GND ..........................-0.3V to (VIN + 0.3V) DRVN to GND .....................................(VIN - 28V) to (VIN + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin QFN (derate 19.2mW/C above +70C) .........1538mW Operating Temperature Range MAX1889EGE ..................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 3V, SHDN = IN, CREF = 0.22F, PGND = GND, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER IN Supply Range IN Undervoltage Lockout (UVLO) Threshold IN Quiescent Current IN Shutdown Current REF Output Voltage Thermal Shutdown MAIN STEP-UP REGULATOR Main Output Voltage Range Operating Frequency Oscillator Maximum Duty Cycle FB Regulation Voltage FB Fault Trip Level Load Regulation Line Regulation FB Input Bias Current LX Switch On-Resistance LX Leakage Current LX Current Limit LX RMS Current Rating Soft-Start Period Soft-Start Step Size POSITIVE LINEAR-REGULATOR CONTROLLER FBP Regulation Voltage FBP Fault Trip Level FBP Input Bias Current FBP Effective Transconductance IFBP VFBP IDRVP = 0.2mA VFBP falling VFBP = 1.25V VDRVP = 10V, IDRVP = 0.1mA to 2mA 1.213 0.96 -50 75 1.25 1.0 1.288 1.04 +50 V V nA mS tSS IFB RLX(ON) ILX ILIM Not tested 4096 / fOSC VREF /32 VLX = 13V 1.6 VFB ILX = 200mA, slope = 0 (Note 2) VFB falling IMAIN = 0 to full load VIN = 2.7V to 5.5V VFB = 1.5V -100 250 0.01 2.1 VMAIN fOSC VFREQ = VIN VFREQ = 0V 80 1.229 0.95 VIN 0.85 1 500 85 1.242 1.0 -1.6 0.2 +100 450 20 2.8 1.4 90 1.254 1.05 13 1.15 V MHz kHz % V V % %/V nA m A A A s V VREF SYMBOL VIN VUVLO IIN 350mV typical hysteresis V SHDN = 0, VIN = 5V -2A < IREF < 50A 1.231 VIN rising VIN falling CONDITIONS MIN 2.7 2.55 2.2 2.7 2.35 0.1 1.250 160 TYP MAX 5.5 2.85 2.5 1.0 1.0 1.269 UNITS V V mA A V C
VFB = VFBP = 1.5V, VFBN = 0V (Note 1)
2
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Triple-Output TFT LCD Power Supply with Fault Protection
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, SHDN = IN, CREF = 0.22F, PGND = GND, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER FBP Line Regulation Bandwidth DRVP Sink Current DRVP Off-Leakage Current FBN Regulation Voltage FBN Fault Trip Level FBN Input Bias Current FBN Effective Transconductance FBN Line Regulation Bandwidth DRVN Sink Current DRVN Off-Leakage Current LOGIC SIGNAL (SHDN) Input Low Voltage Input High Voltage Input Current LOGIC SIGNAL (FREQ) Input Low Voltage Input High Voltage Input Current OVERCURRENT COMPARATOR Input Offset Voltage Input Bias Current OCN, OCP Input Common-Mode Range FAULT TIMER AND GATE DRIVER Fault Timer Period GATE Output Sink Current During Slew GATE Output Pulldown Resistance GATE Output Pullup Resistance tFAULT IGATE VFREQ = 0V, 32768/fOSC VFREQ = VIN, 65536/fOSC VGATE = 1.5V, during turn-on transition VGATE < 0.5V 6 64 64 12 18 200 200 ms A IOCN, IOCP VOCN = VOCP = VIN -5 -50 1.5 +5 +50 0.8 x VIN mV nA V IFREQ 0.15 x VIN typical hysteresis 0.7 x VIN 0.01 1 0.3 x VIN V V A I SHDN 100mV typical hysteresis, VIN = 2.7V to 5.5V VIN = 2.7V to 5.5V 1.6 0.01 1 0.4 V V A IDRVN IFBN VFBN IDRVP SYMBOL (Note 3) VFBP = 1.1V, VDRVP = 10V VFBP = 1.1V, VDRVP = 28V IDRVN = 0.2mA VFBN rising VFBN = 0V VDRVN = -10V, IDRVN = 0.1mA to 2mA IDRVN = 0.2mA, VIN = 2.7V to 5.5V (Note 2) VFBN = 200mV, VDRVN = -10V VFBP = -0.1V, VDRVN = -20V 200 5 0.1 10 95 325 -50 75 1 CONDITIONS IDRVP = 0.2mA, VIN = 2.7V to 5.5V 200 5 0.1 125 400 10 155 475 +50 MIN TYP 1 MAX UNITS mV kHz mA A mV mV nA mS mV kHz mA A
MAX1889
NEGATIVE LINEAR-REGULATOR CONTROLLER
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3
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
ELECTRICAL CHARACTERISTICS
(VIN = 3V, SHDN = IN, CREF = 0.22F, PGND = GND, TA = -40C to +85C.) (Note 4)
PARAMETER IN Supply Range IN ULVO Threshold IN Quiescent Current IN Shutdown Current REF Output Voltage MAIN STEP-UP REGULATOR Main Output Voltage Range Operating Frequency Oscillator Maximum Duty Cycle FB Regulation Voltage FB Fault Trip Level Line Regulation FB Input Bias Current LX Switch On-Resistance LX Current Limit FBP Regulation Voltage FBP Fault Trip Level FBP Input Bias Current FBP Effective Transconductance Bandwidth DRVP Sink Current FBN Regulation Voltage FBN Fault Trip Level FBN Input Bias Current FBN Effective Transconductance Bandwidth DRVN Sink Current LOGIC SIGNAL (SHDN) Input Low Voltage Input High Voltage Input Current ISHDN 100mV typical hysteresis 1.6 1 0.4 V V A IDRVN IFBN IDRVP VFBN IFBP IFB RLX(ON) ILIM VFBP IDRVP = 0.2mA VFBP falling VFBP = 1.25V VDRVP = 10V, IDRVP = 0.1mA to 2mA (Note 2) VFBP = 1.1V, VDRVP = 10V IDRVN = 0.2mA VFBN rising VFBN = 0V VDRVN = -10V, IDRVN = 0.1mA to 2mA (Note 2) VFBN = 200mV, VDRVN = -10V 1.6 1.213 0.96 -50 60 200 5 95 325 -50 60 200 5 155 475 +50 VFB ILX = 200mA, slope = 0 (Note 2) VFB falling VIN = 2.7V to 5.5V VFB = 1.5V -100 VMAIN fOSC VFREQ = VIN VIN 0.75 78 1.215 0.96 13 1.25 92 1.260 1.04 0.45 +100 450 2.8 1.288 1.04 +50 V MHz % V V %/V nA m A V V nA mS kHz mA mV mV nA mS kHz mA VREF SYMBOL VIN VUVLO IIN VIN rising VIN falling VFB = VFBP = 1.5V, VFBN = 0V (Note 1) V SHDN = 0, VIN = 5V -2A < IREF < 50A 1.231 CONDITIONS MIN 2.7 2.55 2.2 MAX 5.5 2.85 2.5 1.0 1.0 1.269 UNITS V V mA A V
POSITIVE LINEAR-REGULATOR CONTROLLER
NEGATIVE LINEAR-REGULATOR CONTROLLER
4
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Triple-Output TFT LCD Power Supply with Fault Protection
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3V, SHDN = IN, CREF = 0.22F, PGND = GND, TA = -40C to +85C.) (Note 4)
PARAMETER LOGIC SIGNAL (FREQ) Input Low Voltage Input High Voltage Input Current OVERCURRENT COMPARATOR Input Offset Voltage Input Bias Current OCN, OCP Input Common-Mode Range FAULT TIMER AND GATE DRIVER GATE Output Sink Current GATE Output Pulldown Resistance GATE Output Pullup Resistance IGATE VGATE = 1.5V, during turn-on transition VGATE < 0.5V 6 18 200 200 A IOCN, IOCP VOCN = VOCP = VIN -5 -50 1.5 +5 +50 0.8 x VIN mV nA V IFREQ 0.15 x VIN typical hysteresis 0.7 x VIN 1 0.3 x VIN V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1889
Note 1: Quiescent current does not include switching losses. Note 2: FB regulation voltage is tested with no slope compensation ramp. Slope compensation needs to be included when selecting resisitors for setting the output voltage (see Main Step-Up Regulator and Output Voltage Selection sections). Note 3: Guaranteed by design. Not production tested. Note 4: Specifications to -40C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA = +25C, unless otherwise noted.)
STEP-UP REGULATOR EFFICENCY vs. LOAD CURRENT (VMAIN = 9V)
MAX1889 toc01
STEP-UP REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (VMAIN = 9V)
MAX1889 toc02
STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT (VMAIN = 13V)
MAX1889 toc03
100
9.1 9.0 OUTPUT VOLTAGE (V) 8.9 8.8 8.7 8.6 8.5 VIN = 2.7V VIN = 3.3V VIN = 5.5V
100
90 EFFICIENCY (%)
90 EFFICIENCY (%)
80
A B C
80 A 70 B C A: VIN = 2.7V B: VIN = 3.3V C: VIN = 5.5V 1 10 100 1000
70
60
A: VIN = 2.7V B: VIN = 3.3V C: VIN = 5.5V 1 10 100 1000
60
50 LOAD CURRENT (mA)
50 1 10 100 1000 LOAD CURRENT (mA)
LOAD CURRENT (mA)
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5
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA = +25C, unless otherwise noted.)
STEP-UP REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (VMAIN = 13V)
MAX1889 toc04
STEP-UP REGULATOR SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX1889 toc05
STEP-UP REGULATOR LOAD-TRANSIENT RESPONSE (0 TO 200mA)
MAX1889 toc06
13.1 13.0 OUTPUT VOLTAGE (V) 12.9 12.8 12.7 VIN = 5.5V 12.6 12.5 1 10 100 VIN = 2.7V VIN = 3.3V
1100 1000 FREQUENCY (kHz) 900 800 700 600 VIN = 3.3V VMAIN = 9V IMAIN = 200mA
1A A 500mA 0
9V B 8.9V 200mA C 0
500 1000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10s/div A: INDUCTOR CURRENT, 500mA/div B: VMAIN = 9V, 100mV/div, AC-COUPLED C: IMAIN = 0 TO 200mA, 200mA/div LOAD CURRENT (mA) INPUT VOLTAGE (V)
STEP-UP REGULATOR LOAD-TRANSIENT RESPONSE (0 TO 1A, 2s PULSE)
MAX1889 toc07
STEP-UP REGULATOR SOFT-START (10mA LOAD) FROM SLOW-RISING INPUT SUPPLY
2A 1A
MAX1889 toc08
STEP-UP REGULATOR SOFT-START (200mA LOAD) FROM SLOW-RISING INPUT SUPPLY
5V 0 5V
MAX1889 toc09
A
A
5V 0 5V
A 0 B 9V C B 8.9V 8.8V 1A C 10s/div A: INDUCTOR CURRENT, 1A/div B: VMAIN = 9V, 100mV/div, AC-COUPLED C: IMAIN = 0 TO 1A, 1A/div 0 D 1ms/div A: VIN, 5V/div B: VGATE, 5V/div C: VC2, 5V/div D: VMAIN = 9V, 5V/div
0 5V
B
0 5V
C 0 10V 5V 0 D 1ms/div A: VIN, 5V/div B: VGATE, 5V/div C: VC2, 5V/div D: VMAIN = 9V, 5V/div 0 10V 5V 0
6
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Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA = +25C, unless otherwise noted.)
POWER-UP SEQUENCE FROM SLOW-RISING INPUT SUPPLY
MAX1889 toc10
STEP-UP REGULATOR SOFT-START (10mA LOAD) USING SHDN CONTROL
5V 0 5V 0 20V B A
MAX1889 toc11
STEP-UP REGULATOR SOFT-START (200mA LOAD) USING SHDN CONTROL
5V A 0 5V 0 5V B
MAX1889 toc12
5V 0 5V 0 5V
A B
C
C 10V 0 0 10V 5V D 1ms/div A: VSHDN, 5V/div B: VGATE, 5V/div C: VC2, 5V/div D: VMAIN = 9V, 5V/div 0
C 0 10V 5V D 1ms/div A: VSHDN, 5V/div B: VGATE, 5V/div C: VC2, 5V/div D: VMAIN = 9V, 5V/div 0
D 2ms/div A: VIN, 5V/div B: VMAIN = 9V, 5V/div C: VPL = 20V, 10V/div D: VNL = -7V, 10V/div
0 -10V
POWER-UP SEQUENCE USING SHDN CONTROL
MAX1889 toc13
STEP-UP REGULATOR NORMAL OPERATION (200mA LOAD)
5V 0 5V A
MAX1889 toc14
POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1889 toc15
26.2 10V OUTPUT VOLTAGE (V) 5V 0 9.05V 26.0 25.8 25.6 25.4 25.2 25.0 0.1
A
B
0 20V
C
10V 0
B
9V 1A
D 2ms/div A: VSHDN, 5V/div B: VMAIN = 9V, 5V/div C: VPL = 20V, 10V/div D: VNL = -7V, 10V/div
0 -10V
C
500mA 0 1s/div A: VLX, 5V/div B: VMAIN = 9V, 50mV/div, AC-COUPLED C: INDUCTOR CURRENT, 500mA/div
VIN = 3.3V IMAIN = 200mA 1 LOAD CURRENT (mA) 10
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7
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA = +25C, unless otherwise noted.)
POSITIVE CHARGE-PUMP INCREMENTAL EFFICIENCY vs. LOAD CURRENT
MAX1889 toc16
NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1889 toc17
NEGATIVE CHARGE-PUMP INCREMENTAL EFFICIENCY vs. LOAD CURRENT
95 90 EFFICIENCY (%) 85 80 75 70 65
MAX1889 toc18
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.1 1 LOAD CURRENT (mA) EFF = (VOUT IOUT) / (PIN(LOAD) - PIN(NOLOAD))
-8.2
100
-8.3 OUTPUT VOLTAGE (V)
-8.4
-8.5
-8.6 VIN = 3.3V IMAIN = 200mA -8.7 10 0.1 1 LOAD CURRENT (mA) 10
60 55 50 0.1
EFF = (VOUT IOUT) / (PIN(LOAD) - PIN(NOLOAD)) 1 LOAD CURRENT (mA) 10
POSITIVE LINEAR-REGULATOR LOAD REGULATION
MAX1889 toc19
POSITIVE LINEAR-REGULATOR LOAD-TRANSIENT RESPONSE
MAX1889 toc20
NEGATIVE LINEAR-REGULATOR LOAD REGULATION
MAX1889 toc21
0 OUTPUT VOLTAGE VARIATION (%)
0 OUTPUT VOLTAGE VARIATION (%)
-0.03
-0.08
-0.06
A
20V 19.95V
-0.16
-0.09 B 10mA 0 -0.15 0.1 1 LOAD CURRENT (mA) 10 2ms/div A: VPL = 20V, 50mV/div, AC-COUPLED B: IPL = 0 TO 10mA, 10mA/div
-0.24
-0.12
-0.32
-0.40 0.1 1 LOAD CURRENT (mA) 10
8
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Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, VMAIN = +9V, VPL = +20V, VNL = -7V, SHDN = FREQ = IN, PGND = GND, TA = +25C, unless otherwise noted.)
NEGATIVE LINEAR-REGULATOR LOAD-TRANSIENT RESPONSE
MAX1889 toc22
OVERCURRENT PROTECTION RESPONSE TO OVERLOAD DURING STARTUP
MAX1889 toc23
OVERCURRENT PROTECTION RESPONSE TO OVERLOAD DURING NORMAL OPERATION
5V 0 5V A B
MAX1889 toc24
5V 0 5V 0 20V
A -6.95V A B -7V
0
C 10V 0 B -10mA 400s/div A: VNL = -7V, 50mV/div, AC-COUPLED B: INL = 0 TO -10mA, 10mA/div D 20ms/div A: VGATE, 5V/div B: VMAIN, 5V/div; IMAIN = 1.5A C: VPL, 10V/div; IPL = 10mA D: VNL, 10V/div; INL = 10mA C 0 0 -10V 20ms/div A: VGATE, 5V/div B: VMAIN = 9V, 5V/div; IMAIN = 200mA TO 1.5A C: VPL = 20V, 10V/div; IPL = 10mA D: VNL = -7V, 10V/div; INL = 10mA D 10V 0 0 -10V
REFERENCE VOLTAGE vs. LOAD CURRENT
MAX1889 toc25
LX CURRENT LIMIT vs. INPUT VOLTAGE
MAX1889 toc26
1.250
2.4
REFERENCE VOLTAGE (V)
1.249
2.3 1.248 CURRENT LIMIT (A)
2.2
1.247
1.246
2.1
1.245 0 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (A)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V)
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9
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Pin Description
PIN 1 NAME SHDN FUNCTION Active-Low Shutdown Control Input. Pull SHDN below the 0.4V logic-low level to turn off all sections of the device and pull the GATE pin high. Pull SHDN above the 1.6V logic-high level to enable the device. Do not leave SHDN floating. Power Ground. PGND is the source of the N-channel power MOSFET. Connect PGND to the analog ground (GND) at the device's pins. Analog Ground. Connect GND to the power ground (PGND) at the device's pins. Internal Reference Bypass Terminal. Connect a 0.22F ceramic capacitor from REF to the analog ground (GND). External load capability is at least 50A. Main Step-Up Regulator Feedback Input. FB regulates to 1.25V nominal. Connect FB to the center of a resistive voltage-divider between the main output (VMAIN) and the analog ground (GND) to set the main step-up regulator output voltage. Place the resistive voltage-divider close to the pin. Negative Linear-Regulator Feedback Input. FBN regulates to 125mV nominal. Connect FBN to the center of a resistive voltage-divider between the negative output (VNEG) and the REF to set the negative linear-regulator output voltage. Place the resistive voltage-divider close to the pin. Negative Linear-Regulator Base Drive. Open drain of an internal P-channel MOSFET. Connect DRVN to the base of the external linear-regulator NPN pass transistor (see Pass Transistor Selection section). Positive Linear-Regulator Base Drive. Open drain of an internal N-channel MOSFET. Connect DRVP to the base of the external linear-regulator PNP pass transistor (see Pass Transistor Selection section). Positive Linear-Regulator Feedback Input. FBP regulates to 1.25V nominal. Connect FBP to the center of a resistive voltage-divider between the positive output (VPOS) and the analog ground (GND) to set the positive linear-regulator output voltage. Place the resistive voltage-divider close to the pin. Frequency Select Input. Pull FREQ above logic-high level (0.7 x VIN) to set the frequency to 1MHz and pull FREQ below logic-low level (0.3 x VIN) to set the frequency to 500kHz. Do not leave FREQ floating. Switching Node. Drain of the internal N-channel power MOSFET for the main step-up regulator. Internal connection. Connect this pin to ground. Overcurrent Comparator Inverting Input. OCN connects to the center tap of a resistive voltagedivider connected to the drain of the input protection P-channel MOSFET (see the Input Overcurrent Protection section). If unused, connect OCN to REF. Overcurrent Comparator Noninverting Input. OCP is connected to the center tap of a resistive voltage-divider that sets the input overcurrent threshold (see the Input Overcurrent Protection section). If unused, connect OCP to GND. Gate Driver Output to the External P-Channel MOSFET (see the Input Overcurrent Protection section). If unused, leave GATE open. Supply Input. The supply voltage powers all the control circuitry. The input voltage range is from 2.7V to 5.5V. Bypass with a 0.1F ceramic capacitor between IN and GND, as close to the pins as possible.
2 3 4
PGND GND REF
5
FB
6
FBN
7
DRVN
8
DRVP
9
FBP
10 11 12 13
FREQ LX TGND OCN
14
OCP
15
GATE
16
IN
10
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Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
VMAIN 9V
VIN 2.7V TO 5.5V
P1 C2 3.3F 6.3V C3 3.3F 6.3V
L1 4.7H R15 43.2k R16 150k 1% 1% 13 OCN 15 GATE 11 LX 5
LX D1 C4 4.7F 10V R17 1M R6 75k 1% FB C5 4.7F 10V C6 4.7F 10V
R2 51.1k 1% R1 10 C1 0.47F
C22 C23 1000pF 100pF
C16 0.01F
14 R3 150k 1% R5 1M R4 1M 1
OCP
R7 12.1k 1%
R18 10k C17 220pF
16
IN TGND
12
SHDN
REF
4 C7 0.22F
REF
10
FREQ
MAX1889
GND PGND
3 2 LX C11 0.1F C12 0.1F
LX C8 0.1F D2
R8 3k C24 2200pF C20 470pF
R11 3k
D3
D4
C9 0.15F
C13 0.15F
C14 0.1F
R19 15k Q1 R9 150k 1% R10 24.3k 1%
7
DRVN
DRVP
8
R20 51k R12 301k 1% R13 20k 1% Q2
VNL -7V C10 1F
6
FBN
FBP
9
VPL +20V C15 1F
C19 1000pF REF
C21 1000pF EXTERNAL LOGIC SIGNAL (ENABLE = LOW)
OPTIONAL R14 221k VMAIN OPTIONAL EXTERNAL LOGIC SIGNAL (ENABLE = LOW)
ANALOG GROUND (GND)
POWER GROUND (PGND)
Figure 1. Standard Application Circuit ______________________________________________________________________________________ 11
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
VIN
REF
SHDN
FREQ
IN
REFERENCE 1.25V REF EN REFOK
EN
GATE DRIVER
GATE
+ + 2.70V 2.35V
OCN OCP
OVERCURRENT COMPARATOR OSCILLATOR OSC SLOPE_COMP
+ -
UVLO COMPARATOR
EN
VMAIN ONP ONMN SEQUENCE AND FAULT DETECTOR LX FAULTM MAIN STEP-UP WITH SOFT-START FB PGND
EN THERMAL SHUTDOWN SSDONE
DRVP
+ VPL ANALOG GAIN BLOCK FBP
+ FAULT COMPARATOR
+ -
+ + MAX1889 + + 0.35V FBN 0.125V
-
ANALOG GAIN BLOCK
DRVN
VNL
FAULT COMPARATOR
REF
Figure 2. MAX1889 System Functional Diagram 12 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Table 1. Component List
DESIGNATION C2, C3 C4, C5, C6 D1 DESCRIPTION 3.3F, 6.3V X5R ceramic capacitors (0805) Taiyo Yuden JMK212BJ335MG 4.7F, 10V X7R ceramic capacitors (1210) Taiyo Yuden LMK352BJ475MF 1.0A, 30V Schottky diode (S-flat) Toshiba CRS02 200mA, 25V dual-series Schottky diodes (SOT23) Fairchild BAT54S 250mA, 75V switching diode (SOT23) Central Semiconductor CMPD914 6.8H, 1.3A inductor Coilcraft LPO2506IB-682 2.4A, 20V P-channel MOSFET (3-pin SuperSOT) Fairchild FDN304P 200mA, 40V NPN bipolar transistor (SOT23) Fairchild MMBT3904 200mA, 40V PNP bipolar transistor (SOT23) Fairchild MMBT3906
Detailed Description
The MAX1889 contains a high-performance, step-up switching regulator, two low-cost linear-regulator controllers, and multiple levels of protection circuitry. Figure 2 shows the system functional diagram of the device. The output voltage of the main step-up converter (VMAIN) can be set from VIN to 13V with an external resistive voltage-divider. The high switching frequency (500kH/1MHz) of the main step-up converter and current-mode control provide fast transient response and allow the use of lowprofile inductors and ceramic capacitors. The internal power MOSFET minimizes the external component count while achieving high efficiency by incorporating a lossless current-sensing technology. The switching node (LX) can generate both positive and negative voltage supplies by driving charge-pump stages of capacitors and diodes. The user can use as many charge-pump stages as needed to generate supply voltages of more than +30V and -15V. The positive and negative linear-regulator controllers postregulate the charge-pump supply voltages and allow users to program power-up sequencing as well. The unique input switch control of the MAX1889 senses the current drawn from the input power supply by monitoring the voltage drop across the input P-channel MOSFET and latches off if an overcurrent condition lasts for more than the fault timer period. In addition, all three outputs are monitored for fault conditions that last longer than the fault latch timer. If the junction temperature of the IC exceeds +160C, the device goes into a latched shutdown state.
D2, D3, D4
D5 L1
P1
Q1 Q2
Standard Application Circuit
The standard application circuit (Figure 1) of the MAX1889 generates +9V, +20V, and -7V outputs for TFT LCD displays. The input voltage is from 2.7V to 5.5V. Table 1 lists the recommended component options and Table 2 lists the component suppliers.
Main Step-Up Regulator
The main step-up regulator switches at 1MHz (or 500kHz) and employs a current-mode control architecture to maximize loop bandwidth to provide fast-transient response to pulsed loads found in source drivers for TFT LCD panels. Also, the high switching frequency allows the use of low-profile inductors and capacitors to minimize the thickness of LCD panel designs. The integrated high-efficiency MOSFET and the IC's built-in soft-start function reduce the number of external components required while controlling inrush current.
Table 2. Component Suppliers
SUPPLIER Coilcraft Fairchild Taiyo Yuden Toshiba PHONE 847-639-6400 408-822-2000 800-348-2496 949-455-2000 FAX 847-639-1469 408-822-2102 847-925-0899 949-859-3963 WEBSITE www.coilcraft.com www.fairchildsemi.com www.t-yuden.com www.toshiba.com
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Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Depending on the input-to-output voltage ratio, the regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (D) of the power MOSFET in each switching cycle. The duty cycle of the MOSFET is approximated by: V -V D MAIN IN VMAIN On the rising edge of the internal clock, the controller sets a flip-flop, which turns on the N-channel MOSFET (Figure 3). The input voltage is applied across the inductor. The inductor current ramps up linearly, storing energy in a magnetic field. Once the sum of the feedback voltage error-amplifier output, slope-compensation, and current-feedback signals trip the multi-input PWM comparator, the MOSFET turns off, and the flipflop resets. Since the inductor current is continuous, a transverse potential develops across the inductor that turns on the diode (D1). The voltage across the inductor becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp back down, transferring the energy to the output capacitor and the load. The MOSFET remains off for the rest of the clock cycle.
LX RESET DOMINANT OSC S PGND R ILIM COMPARATOR Q
+ + MAX1889
ILIM CURRENT SENSE
+ -
FAULT M
+ + -
SLOPE_COMP
FB
+ + -
REFOUT SOFT-START SSOK
REFIN
REF
CLK EN ONMN
SSDONE
Figure 3. Main Step-Up Regulator Functional Diagram 14 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Positive Linear-Regulator Controller
The positive linear regulator provides the positive high voltage for the TFT LCD gate drivers. The high voltage can be produced using a charge-pump circuit as shown in Figure 1. Use as many stages as necessary to obtain the required output voltage (see the Selecting the Number of Charge-Pump Stages section). The positive linear-regulator controller is an analog gain block with an open-drain N-channel output. It drives an external PNP pass transistor with a 3k base-to-emitter resistor to post-regulate the charge-pump output (Figure 1). The regulator controller is designed to be stable with an output capacitor of 0.1F or more. To enable the regulator using an external control signal, apply the logic-control input in series with a signal diode (Figure 1). Additional delay can be added with external circuitry. Note that the voltage rating of the DRVP output is 28V. If higher voltages are present, an external cascode NPN transistor should be used with the emitter connected to DRVP, the base to VMAIN, and the collector to the base of the PNP. put (Figure 1). The regulator controller is designed to be stable with an output capacitor of 0.1F or more. The negative linear regulator is enabled as soon as the main step-up regulator is enabled. To enable the regulator using an external control signal, apply the logic-control input through an open-drain output or an N-channel MOSFET (Figure 1). Additional delay can be added with external circuitry (see the Applications Information section). Note that the voltage rating of the DRVN output is VIN - 28V. If higher voltages are present, an external cascode PNP transistor should be used with the emitter connected to DRVN, the base to GND, and the collector to the base of the NPN.
Undervoltage Lockout (UVLO)
The UVLO comparator of the MAX1889 compares the input voltage at the IN pin with the UVLO threshold (2.7V rising, 2.35V falling, typ) to ensure that the input voltage is high enough for reliable operation. The 350mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO threshold, the controller enables the reference block. Once the reference is above 1.05V, an internal 12A current source pulls the GATE pin low and turns on an external P-channel MOSFET switch (P1, Figure 1) that connects the input supply to the regulator. When the input voltage falls below the UVLO threshold, the controller sets the fault latch and pulls GATE high with an internal 100 switch to turn off P1 quickly (Figure 4).
Negative Linear-Regulator Controller
The negative linear regulator provides the negative voltage required to supply gate drivers in TFT LCD panels. The negative voltage can be produced using a charge pump circuit as shown in Figure 1. Use as many stages as necessary to obtain the required output voltage (see the Selecting the Number of Charge-Pump Stages section). The negative linear-regulator controller is an analog gain block with an open-drain P-channel output. It drives an external NPN pass transistor with a 3k baseto-emitter resistor to postregulate the charge-pump out-
Reference Voltage (REF)
The reference output is nominally 1.25V, and can source at least 50A (see the Typical Operating Characteristics). Bypass REF with a 0.22F ceramic capacitor connected between REF and GND.
Oscillator Frequency (FREQ)
IN
The internal oscillator frequency is pin programmable. Connect FREQ to ground for 500kHz operation and to VIN for 1MHz operation. Note that the soft-start period scales with the oscillator frequency (see the Soft-Start section).
GATE
Shutdown (SHDN)
+
L CIN 0.625V
+ -
12A EN
A logic-low signal on the SHDN pin disables all device functions including the reference. When shut down, the supply current drops to 0.1A (typ) to maximize battery life. The output capacitance, feedback resistors, and load current determine the rate at which each output voltage decays. A logic-high signal on the SHDN pin activates the MAX1889 (see the Power-Up Sequencing section). Do not leave the pin floating. If unused, connect SHDN to IN. Toggling SHDN or cycling IN clears the fault latch.
Figure 4. External Input P-Channel MOSFET Switch Control ______________________________________________________________________________________ 15
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Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Power-Up Sequencing and Inrush Current Control
Once SHDN is high, the MAX1889 enables the UVLO circuitry and compares the input voltage with the UVLO rising threshold (2.7V, typ). If the input voltage exceeds the UVLO rising threshold, the reference is enabled. When the reference voltage ramps up above 1.05V (typ), the MAX1889 enables the oscillator and turns on the external P-channel MOSFET P1 (Figure 1) by pulling GATE low. GATE is pulled down with a 12A current source. Add a capacitor from the gate of P1 to its drain to slow down the turn-on rate of the MOSFET, and reduce inrush current. Once GATE reaches around 0.6V, an internal N-channel MOSFET turns on and pulls GATE to ground in order to maximize the enhancement of the external P-channel MOSFET. As P1 fully turns on, the main step-up regulator powers up with soft-start (see the Soft-Start section). The negative linear regulator is enabled at the same time as the main step-up regulator. The positive linear regulator is enabled after the soft-start routine is completed. The fault detection timer begins after the main step-up regulator has finished its soft-start period.
Input Overcurrent Protection
The high-side overcurrent comparator of the MAX1889 provides input overcurrent protection when it is used together with the external P-channel MOSFET switch P1 (Figure 1). Connect resistive voltage-dividers from the source and drain of P1 to GND to set the overcurrent threshold. The center taps of the dividers are connected to the overcurrent comparator inputs (OCN and OCP) See the Setting the Input Overcurrent Threshold section for information on calculating resistor values. An overcurrent event activates the fault-protection circuitry.
Fault Protection
Once the soft-start routine is completed, if the output of the main regulator or either linear regulator is below its respective fault-detection threshold, or the input overcurrent comparator pulls high, the MAX1889 activates the fault timer. If the fault condition still exists after the 64ms fault-timer duration, the MAX1889 sets the fault latch, which shuts down all the outputs except the reference, which remains active. After removing the fault condition, toggle SHDN (below 0.4V) or cycle the input voltage (below 2.2V) to clear the fault latch and reactivate the device.
Soft-Start
The soft-start of the main step-up regulator (Figure 3) is achieved by ramping up the reference voltage of the multi-input PWM comparator in 4096 oscillator clock cycles. The 4096 clock cycles correspond to 4.096ms for 1MHz operation and 8.192ms for 500kHz operation. The reference of the PWM comparator comes from a 5-bit DAC that generates 32 steps when the reference ramps up from 0V to its final value. This soft-start method allows a gradual increase of the output voltage to reduce the input surge current (see the startup waveforms in the Typical Operating Characteristics). The average input current is given as: V x COUT IIN _ AVG = MAIN VIN x t SS x where VMAIN is the main step-up regulator output voltage, VIN is the input voltage, COUT is the main step-up regulator output capacitor, is the efficiency of the step-up regulator, and t SS is the soft-start period (4.096ms for 1MHz operation and 8.192ms for 500kHz operation).
2
Thermal Shutdown
The thermal shutdown feature limits total power dissipation in the MAX1889. When the junction temperature (TJ) exceeds +160C, a thermal sensor sets the fault latch (Figure 2), which shuts down all the outputs except the reference, allowing the device to cool down. Once the device cools down by 15C, toggle SHDN (below 0.4V) or cycle the input voltage (below 2.2V) to clear the fault latch and reactivate the device.
Design Procedure
Main Step-Up Regulator
Output Voltage Selection Adjust the output voltage by connecting a resistive voltage-divider from the output (VMAIN) to GND with the center tap connected to FB (Figure 1). Select R7 in the 10k to 50k range. Calculate R6 with the following equations: R6 = R7 (VMAIN / VFB ) - 1 where
[
]
VFB = 1.242V - (D x 20mV) and D
VMAIN - VIN VMAIN
For example, at VIN = 3V, VMAIN = 9V, D 0.66, and VFB = 1.229V. VMAIN can range from VIN to 13V.
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Triple-Output TFT LCD Power Supply with Fault Protection
Inductor Selection The minimum inductance value, peak current rating, series resistance, and size are factors to consider when selecting the inductor. These factors influence the converter's efficiency, maximum output load capability, transient response time, and output voltage ripple. For most applications, values between 3.3H and 20H work best with the MAX1889's switching frequencies. The maximum load current, input voltage, output voltage, and switching frequency determine the inductor value. For a given load current, higher inductor value results in lower peak current and, thus, less output ripple, but degrades the transient response and possibly increases the size of the inductor. The equations provided here include a constant defined as LIR, which is the ratio of the peak-to-peak inductor current ripple to the average DC inductor current. For a good compromise between the size of the inductor, power loss, and output voltage ripple, select an LIR of 0.3 to 0.5. The inductance value is then given by: V IN(TYP) L= V MAIN
2
MAX1889
The power loss due to the inductor's series resistance (PLR) can be approximated by the following equation: I xV PLR = I(LAVG)2RL MAIN MAIN RL VIN where IL(AVG) is the average inductor current and RL is the inductor's series resistance. For best performance, select inductors with resistance less than the internal N-channel MOSFET's on-resistance (0.25 typ). To minimize radiated noise in sensitive applications, use a shielded inductor. Output Capacitor The output capacitor affects the circuit stability and output voltage ripple. A 10F ceramic capacitor works well in most applications. Depending on the output capacitor chosen, feedback compensation may be required or desirable to increase the loop-phase margin or increase the loop bandwidth for transient response (see the Feedback Compensation section). The total output voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the ohm ripple due to the capacitor's equivalent series resistance (ESR): VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) VRIPPLE(ESR) IPEAKRESR(COUT), and V I -V VRIPPLE(C) MAIN MAIN IN COUT VMAINfOSC where IPEAK is the peak inductor current (see the Inductor Selection section). For ceramic capacitors, the output voltage ripple is typically dominated by VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. Step-Up Regulator Compensation The loop stability of a current-mode step-up regulator can be analyzed using a small-signal model. In continuous conduction mode (CCM), the loop-gain transfer function consists of a dominant pole, a high-frequency pole, a right-half-plane (RHP) zero, and an ESR zero. In the case of ceramic output capacitors, the ESR zero is at a very high frequency.
2
V MAIN - VIN(TYP) 1 I MAIN(MAX)fOSC LIR
where is the efficiency, fOSC is the oscillator frequency (see the Electrical Characteristics), and IMAIN includes the primary load current and the input supply currents for the charge pumps. Considering the typical application circuit, the maximum average DC load current (IMAIN(MAX)) is 200mA with a 9V output. Based on the above equations, and assuming 85% efficiency and a switching frequency of 1MHz, the inductance value is 9.4H for an LIR of 0.3. The inductance value is 5.6H for an LIR of 0.5. The inductance in the standard application circuit is chosen to be 6.8H. The inductor's peak current rating should be higher than the peak inductor current throughout the normal operating range. The peak inductor current is given by: I LIR 1 MAIN(MAX)VMAIN IPEAK = 1 + VIN(MIN) 2 Under fault conditions, the inductor current can reach the internal LX current limit (see the Electrical Characteristics). However, soft saturation inductors and the controller's fast current-limit circuitry protect the device from failure during such a fault condition. The inductor's DC resistance can significantly affect efficiency due to conduction losses in the inductor.
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17
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Therefore, the dominant pole and the RHP zero determine the loop response of the step-up regulator. The frequency of the dominant pole is: fP _ DOMINANT = 1 2RLC zero-pole pair to the loop by connecting an RC network from the FB pin to the main output (lead compensation). The frequencies of the pole and zero for the lag compensation are: fP _ FB = 1 R1 x R2 2 R4 C1 R1 + R2 1 2R4 x C1
where RL is the load resistance and C is the output capacitor. The frequency of the RHP zero is:
2R L fZ _ RHP = 1- D
()
fZ _ FB =
2L
where D is the duty cycle, L is the inductance, and the DC gain is given by: R1 (1 - D) ADC = 20log x x RL R1 + R2 RCS where RCS is the internal current-sense resistor, and R1 and R2 are the feedback divider resistors in Figure 5. However, adding lead or lag compensation (Figure 5) can be useful to adjust the trade-off between stability and transient response. If greater phase margin is needed for stability, and lower bandwidth is acceptable, add a pole-zero pair by connecting an RC network from the FB pin to ground (lag compensation). Conversely, if higher bandwidth is required for faster transient response, and lower phase margin is acceptable, add a
The frequencies of the zero and pole for the lead compensation are: 1 fZ _ FF = 2 R2 + R 3 x C2
(
)
fP _ FF =
1 R1 x R2 2 R 3 + C2 R1 + R2
L VIN
D VMAIN R3 LX R2 C2 FB C RL D1
The compensation resistors R3 and R4 change the AC gain affecting the loop bandwidth and phase margin at crossover. Reducing the bandwidth too much (FB compensation) harms the transient response, while increasing it too much harms phase margin and stability. As a rule, start with R3 (or R4) approximately equal to half of R1 (or R2). In a typical application, the compensation capacitors C1 and C2 can be in the range between 100pF to 1000pF. Then, check the stability by monitoring the transient response waveform when a pulsed load is applied to the output. Using Compensation for Improved Soft-Start The digital soft-start of the main step-up regulator limits the average input current during startup. In order to smooth out each step of the digital soft-start, add a lowfrequency lead compensation network (Figure 5). The network effectively spreads out the switching pulses and lowers the peak inductor currents. The smoothing network is active only during soft-start when the output voltage rises. Positive changes in the output are instantaneously coupled to the FB pin through D1 and feed-forward capacitor C2. This arrangement generates a smoothly rising output voltage. When the output voltage reaches regulation, C2 charges up through R3 and D1 turns off. In most applications, the lead compensation is not needed and can be disabled by making R3 large. With R3 > R2, the pole and the zero in the compensation network are very close to one another and cancel out.
MAX1889
R1
R4 C1
GND PGND
Figure 5. External Compensation 18
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Triple-Output TFT LCD Power Supply with Fault Protection
Input Capacitor The input capacitor (CIN) reduces the current peaks drawn from the input supply and reduces noise injection into the device. Two 3.3F ceramic capacitors are used in the standard application circuit (Figure 1) because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance since the step-up regulator typically runs directly from the output of another regulated supply. Typically, CIN can be reduced below the values used in the standard applications circuit. Ensure a low noise supply at the IN pin by using adequate CIN. Alternatively, greater voltage variation can be tolerated on CIN if IN is decoupled from CIN using an RC lowpass filter (see R1, C1 in Figure 1). Rectifier Diode The MAX1889's high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. In general, a 1A Schottky diode complements the internal MOSFET well. Input P-Channel MOSFET Select the input P-channel MOSFET based on the current rating, voltage rating, gate threshold, and on-resistance. The MOSFET must be able to handle the peak input current (see the Inductor Selection section). The drain-to-source voltage rating of the input MOSFET should be higher than the maximum input voltage. Because the MOSFET conducts the full input current, the on-resistance should be low enough for higher efficiency. Use a low-threshold MOSFET to ensure that the switch is fully enhanced at lowest input voltages. Setting the Input Overcurrent Threshold The high-side comparator of the MAX1889 provides input overcurrent protection when used in conjunction with an external P-channel MOSFET P1. The accuracy of the overcurrent threshold is affected by many factors, including comparator offset, resistor tolerance, input voltage range, and variations in MOSFET R DS(ON) . The input overcurrent comparator is only intended to protect against catastrophic failures. This function is similar to an input fuse. To minimize the impact of the comparator's input offset on the current-sense accuracy, the sense voltage should be close to the upper limit of the common-mode range, which extends up to 80% of the input voltage. The resistive voltage-divider (R3/R4), combined with the on-state resistance of P1, sets the overcurrent threshold. The center of R3/R4 is connected to the inverting input (OCN) as shown in Figure 6.
MAX1889
If the comparator and resistors are ideal, the threshold is at the current where both inputs are equal: VIN x R2 R4 = VIN - IL(MAX) x RDS(MAX) x R1+ R2 R3 + R4
(
)
IL(MAX) is the average inductor current at maximum load condition and minimum input voltage, and given by: IL(MAX) = VOUT x VIN(MIN) x ILOAD(MAX)
where is the efficiency of the main step-up regulator. If the step-up regulator's minimum input voltage is 2.7V, output voltage is 9V and maximum load current is 0.3A. Assuming 80% efficiency, the maximum average inductor current is: 9V IL(MAX) = x 0.3A = 1.25A 0.8 x 2.7V R DS(MAX) is the maximum on-state drain-to-source resistance of P1. The maximum RDS(ON) at +25C can be found in the MOSFET data sheet, but that number does not include the temperature coefficient. Since the temperature coefficient for the resistance is 0.5%/C, RDS(MAX) can be calculated with the following equation: RDS(MAX) = RDS _ 25C x 1+ 0.005 x (TJ - 25)
[
]
where TJ is the actual MOSFET junction temperature in normal operation due to ambient temperature rise and self-heating caused by power dissipation. As an example, consider Fairchild FDN304P, which has a maximum RDS(ON) at room temperature of 70m.
RDS(ON) VIN
R1
R3 OCP
OCN OC COMP R2 R4
Figure 6. Setting the Overcurrent Threshold ______________________________________________________________________________________ 19
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
If the junction temperature is +100C, the maximum onstate resistance overtemperature is: RDS(MAX) = 70m x 1 + 0.005 x (100 - 25) = 100m For given R1 and R2 values, the ideal ratio of R3/R4 can be determined: R3 R1+ R2 VIN - IPEAK(MAX) x RDS(MAX) = x -1 R4 R2 VIN To consider the effect of resistor tolerance, comparator offset, and input voltage variation, the minimum threshold equation is:
VIN(MIN) x R2 x (1+ ) + 5mV = R4 x 1-
ITH _ TYP =
[
]
R2 x (R3 + R4) x 1 RDS(TYP) R4 x (R1 + R2) VIN(TYP)
The following example shows how to apply the above equations in the design. If 1% resistors are used, then = 0.01. To set VOCP to be around 75% of VIN, select R1 = 51.1k and R2 = 150k. Assume that the minimum input voltage is 2.7V and the typical input voltage is 3.3V, the average inductor current at maximum load is 1.25A, and the maximum RDS(ON) of P1 is 100m:
k= 1- 0.01 = 0.9802 1+ 0.01
( (VIN(MIN) - IL(MAX) x RDS(MAX) ) x R3 x (1+ ) + R4)x (1- )
where VIN(MIN) is the minimum expected value of the input voltage, is the tolerance of the resistors and the 5mV is the worst-case input offset voltage of the comparator. To simplify the equation, define a constant k as follows: k= 1- 1+
R1x (1- ) + R2 x (1 + )
R3 2.7V - 1.25A x 0.1 = 0.9802 x - 1 150k R4 + 0.005V 2.7V x 150k + 0.9802 x 51.1k = 0.2637
If R4 =150k, then R3 = 39.2k. The typical overcurrent threshold is: 150k x (39.2k + 150k) 3.3V x 1 0.047 150k x (51.1k + 150k)
ITH _ TYP =
= 4.15A
The minimum threshold equation becomes: VIN(MIN) x R2 + 5mV = k x R1+ R2
Charge Pumps
Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meets the output requirement. The number of positive charge-pump stages is given by: V + VDROPOUT - VMAIN NPOS = PL VMAIN - 2 x VD where NPOS is the number of positive charge-pump stages, V PL is the positive linear-regulator output, VMAIN is the main step-up regulator output, VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 2V.
(VIN(MIN) - IL(MAX) x RDS(MAX) ) x R3k+xkRx4R4
Solving for R3/R4 yields: R3 VIN(MIN) - IL(MAX) x RDS(MAX) - 1 =kx R2 R4 + 5mV VIN(MIN) x R2 + k x R1 The R3/R4 ratio guarantees the required minimum level for IL(MAX). The typical overcurrent threshold is given by:
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Triple-Output TFT LCD Power Supply with Fault Protection
The number of negative charge-pump stages is given by: NNEG = -VNL + VDOPOUT VMAIN - 2 x VD output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: COUT ILOAD 2fOSCVRIPPLE
MAX1889
where NNEG is the number of negative charge-pump stages, V NL is the negative linear-regulator output, VMAIN is the main step-up regulator output, VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 2V. The above equations are derived based on the assumption that the first stage of the positive charge pump is connected to VMAIN and the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to VIN or another available supply. If the first charge-pump stage is powered from V IN, then the above equations become: V + VDROPOUT - VIN NPOS = PL VMAIN - 2 x VD - VNL + VDROPOUT + VIN NNEG = VMAIN - 2 x VD Flying Capacitor Increasing the flying capacitor (CX) value increases the output current capability. Increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance limit the source impedance. A 0.1F ceramic capacitor works well in most low-current applications. The flying capacitor's voltage rating must exceed the following: VCX > N x VMAIN where N is the stage number in which the flying capacitor appears, and VMAIN is the main output voltage. For example, the two-stage positive charge pump in the typical application circuit (Figure 1) where VMAIN = 9V contains two flying capacitors. The flying capacitor in the first stage (C14) requires a voltage rating over 9V. The flying capacitor in the second stage (C13) requires a voltage rating over 18V. Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the
where VRIPPLE is the peak-to-peak value of the output ripple. Charge-Pump Rectifier Diodes Use Schottky diodes with a current rating equal to or greater than two times the average charge-pump input current.
Linear-Regulator Controllers
Output Voltage Selection Adjust the positive linear-regulator output voltage by connecting a resistive voltage-divider from VPL to GND with the center tap connected to FBP (Figure 1). Select R13 in the range of 10k to 30k. Calculate R12 with the following equation: R12 = R13 [(VPL / VFBP) - 1] where VFBP = 1.25V. Adjust the negative linear-regulator output voltage by connecting a resistive voltage-divider from VNL to REF with the center tap connected to FBN (Figure 1). Select R10 in the range of 10k to 30k. Calculate R9 with the following equation: R9 = R10 [(VFBN - VNL) / (VREF - VFBN)] where VFBN = 125mV, VREF = 1.25V. Note that REF is only guaranteed to source 50A. Using a resistor less than 20k for R10 results in higher bias current than REF can supply. Connecting another resistor (R14) from VMAIN to REF (Figure 1) can solve this problem because the main output can supply part of the resistor's (R10) bias current. Use the following equation to determine the value of R14: R14 = VMAIN - VREF VREF - VFBN - 40A R10
Drawing only 40A from REF leaves the remaining 10A for other purposes. Pass Transistor Selection The pass transistor must meet specifications for current gain (), input capacitance, collector-emitter saturation voltage, and power dissipation.
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21
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
The transistor's current gain limits the guaranteed maximum output current to: V ILOAD(MAX) = IDRV - BE MIN RBE where IDRV is the minimum base-drive current, and RBE is the pullup resistor connected between the transistor's base and emitter. Furthermore, the transistor's current gain increases the linear regulator's DC loop gain (see the Stability Requirements section), so excessive gain destabilizes the output. Therefore, transistors with current gain over 100 at the maximum output current are not recommended. The transistor's input capacitance and input resistance also create a second pole, which could be low enough to make the output unstable when heavily loaded. The transistor's saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports. Alternatively, the package's power dissipation could limit the usable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor's package and mounting must exceed the actual power dissipation in the device. The power dissipation equals the maximum load current times the maximum input-to-output voltage differential: P = ILOAD(MAX) (VLDOIN - VLDOOUT ) = ILOAD(MAX)VCE During startup, the LDO outputs are below their respective setpoints, and the base drive to the pass transistors is a maximum. The large drive currents can cause the charge-pump outputs to collapse. If the chargepump loading is objectionable, base resistors can be added between the drive outputs (DRVN and DRVP) and the pass transistors (Figure 7). These resistors limit the maximum drive current and prevent discharging the charge pump's output capacitors. Select the minimum base drive current to meet the maximum required LDO output current: IDRIVE(MIN) = ILDOOUT(MAX) MIN
The resistance required to guarantee this base current is: RBASE = VLDOIN(MAX) - VBE IDRIVE(MIN) MIN VLDOIN(MAX) - VBE ILDOOUT(MAX)
(
)
As a consequence of adding the base resistors, a voltage change at DRVN and DRVP accompanies changes in drive current. This voltage change can be coupled through parasitic capacitance to the LDO feedback pins. If the rate of voltage change is sufficiently large, it can cause instability.
VN C24 2200pF C20 470pF
VP
MAX1889
R19 15k Q1 R20 51k Q2
7
DRVN
DRVP
8
VNL
6
FBN
FBP
9
VPL
REF
Figure 7. Limiting LDO Drive Current During Startup 22 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
To avoid excessive voltage coupling, a small capacitor can be added in parallel with the base resistor. The resulting RC time constant should be between 5s to 50s. Stability Requirements The MAX1889 linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, the pass transistor, the base-emitter resistor, and the output capacitor determine the loop stability. If the output capacitor and pass transistor are not properly selected, the linear regulator can be unstable. The transconductance amplifier regulates the output voltage by controlling the pass transistor's base current. The total DC loop gain is approximately: 5.5 I BIAShFE V AV(LDO) = REF 1 + VT ILOAD where VT is 26mV at room temperature, and IBIAS is the current through the base-to-emitter resistor (RBE). This bias resistor is typically 3k, providing 0.23mA of current, biasing the LDO near its regulation voltage setpoint. The output capacitor and the load resistance create the dominant pole in the system. The pass transistor's input capacitance creates a second pole in the system. Additionally, the output capacitor's ESR generates a zero. To achieve stable operation, use the following equations to verify that the linear regulator is properly compensated: 1) First, determine the dominant pole set by the linear regulator's output capacitor and the load resistor: fPOLE(CLDO) = 1 2CLDORLOAD = ILOAD(MAX) 2CLDO VLDO 3) A third pole is set by the linear regulator's feedback resistance and the capacitance (including stray capacitance) between FB_ and GND (for the positive LDO) and FBN and GND (for the negative LDO) (Figure 8): fPOLE(FB)_ POS = fPOLE(FB)_ NEG = 1 2CFB (R12II R13) 1 2CFB (R9II R10)
4) If the second and third poles occur well after unitygain crossover, the linear regulator remains stable: fPOLE(CBE) > 2fPOLE(CLDO) AV(LDO) However, if the ESR zero occurs before the unity-gain crossover, cancel the zero with the feedback pole by changing circuit components such that: fPOLE(FB) 1 2COUTRESR
For most applications where ceramic capacitors are used, the ESR zero always occurs after the crossover. A capacitor connected between the output and the feedback node improves the transient response, reduces the noise coupled into the feedback loop, and maintains the correct regulation point (Figure 8). Output Capacitor Selection Typically, more output capacitance provides the best solution, since this also reduces the output voltage drop immediately after a load transient. Connect at least a 0.1F capacitor between the linear regulator's output and ground, as close to the external pass transistor as possible. Depending on the selected pass transistor, larger capacitor values may be required for stability (see the Stability Requirements section). Furthermore, the output capacitor's ESR affects stability. Use output capacitors with an ESR less than 200m to ensure stability and optimum transient response. Once the minimum capacitor value for stability is determined, verify that the linear regulator's output does not contain excessive noise. Although adequate for stability, small capacitor values can provide too much bandwidth, making the linear regulator sensitive to noise. Larger capacitor values reduce the bandwidth, thereby reducing the regulator's noise sensitivity. If noise on the ground reference causes the design to be marginally stable for the negative linear regulator, bypass the negative output back to its reference voltage. This technique reduces the differential noise on the output.
23
The unity gain crossover of the linear regulator is: fCROSSOVER = AV(LDO) fPOLE(CLDO) 2) Next, determine the second pole set by the baseto-emitter capacitance (including the transistor's input capacitance), the transistor's input resistance, and the base-to-emitter pullup resistor: fPOLE(CBE) = 1 2CBE (RBE II RIN ) RI + VThFE = BE LOAD 2CBERBE VThFE
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Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Applications Information
PC Board Layout
Careful PC board layout is extremely important for proper operation. Use the following guidelines for good PC board layout: 1) Minimize the area of high-current loops by placing the input capacitors, inductor, output diode, and output capacitors less than 0.2in (5mm) from the LX and PGND pins. Connect these components with traces as wide as possible. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. 2) Create islands for the analog ground (GND), power ground (PGND), and linear regulator ground. Starconnect them to the backside pad of the device. The REF bypass capacitor and both feedback dividers should be connected to the analog ground island (GND). The step-up regulator's input and output capacitors, and the charge-pump components should be a wide power ground plane. The power ground plane should be connected to the power ground pin (PGND) with a wide trace. Maximizing the width of the power ground traces improves efficiency and reduces output voltage ripple and noise spikes. All the other ground connections, such as the IN pin bypass capacitor and the linear regulator output capacitors, should be star-connected to the backside of the device with wide traces. Make no other connections between these separate ground planes. 3) Place IN pin and REF pin bypass capacitors as close to the device as possible. 4) Place all feedback voltage-divider resistors as close to their respective feedback pins as possible. The divider's center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up switching noise. Care should be taken to avoid running any feedback trace near LX or the switching nodes in the charge pumps. 5) Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 6) Minimize the size of LX node while keeping it wide and short. Keep the LX node away from feedback nodes (FB, FBP, and FBN) and analog ground. Use DC traces as shield if necessary. Refer to the MAX1889 evaluation kit for an example of proper board layout.
R8 3k VN
R11 3k VP
MAX1889
Q1
7 R9 150k 1%
DRVN
DRVP
8 R12 301k 1%
Q2
VNL C19 1000pF
6
FBN
FBP
9
VPL R13 20k 1% C21 1000pF
R10 24.3k 1%
REF
Figure 8. LDO Compensation 24 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection
Additional Application Circuits
Operation with Output Voltage >13V The maximum output voltage of the step-up regulator is 13V, which is limited by the absolute maximum rating of the internal power MOSFET. To achieve higher output voltage, an external N-channel MOSFET can be cascoded with the internal FET (Figure 9). Since the gate of the external FET is biased from the input supply, use a logic-level FET to ensure that the FET is fully enhanced at the minimum input voltage. The current rating of the FET needs to be higher than the internal current limit. Changing Power-Up Sequence The power-up sequencing of the linear regulators can be controlled using external delays. Figure 10 shows an application where the negative linear-regulator output powers up with a certain delay after the positive linear regulator reaches regulation. The resistors R1, R2, and the capacitor C form an RC network that provides the power-up delay. The time constant of this RC network is: = R1x R2 R1+ R2 C
VN VP
MAX1889
VIN
VMAIN 15V
LX FB STEP-UP REGULATOR
PGND
MAX1889
Select the ratio of R1 and R2 so that: VN or: V =- N R2 VPL With this R1/R2 ratio, the power-up delay can be calculated as: R1 V PL R1+ R2 D = ln V - 0.125V D where VD is the forward voltage drop of the diode and 0.125V is the FBN regulation point. As a design example, assume the positive linear-regulator output VPL is +20V, the negative charge-pump output VN is -9V, and the required power-up delay time tD is 4ms: R1 The ratio of R1 and R2 should9be: = R2 20 R1 R2 R1+ R2 + VPL R1 R1 + R2 =0
Figure 9. Operation with Output Voltage >13V Using Cascoded MOSFET
The required RC time constant is: 4ms = 1.68ms = 9 20 20 + 9 ln 0.7 - 0.125 Choose C = 0.1F, then R1//R2 = 16.8k. Use standard resistor values: R1 = 56k and R2 = 24k. Disabling Input MOSFET Switch If the input protection MOSFET is not needed, disable the input overcurrent comparator by connecting the OCP pin to ground, the OCN pin to VIN. Leave the GATE pin floating (Figure 11). Generating Gamma Reference Voltage The reference voltage for the Gamma correction resistor string can be produced using the linear-regulator controller. If the voltage difference between the main boost voltage (VMAIN) and the Gamma reference voltage is 400mV or greater, the emitter of the PNP pass transistor should be connected to VMAIN.
______________________________________________________________________________________
25
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
VP
VN
VIN LX FB STEP-UP REGULATOR
VMAIN +9V
VN
PGND DRVN FBN NEGATIVE REGULATOR
MAX1889
VP
VNL -7V
DRVP R1 VN R2 VPL C GND REF REF POSITIVE REGULATOR FBP
VPL +20V
Figure 10. Controlling Power-Up Sequence with External Delay
If the voltage difference is less than 400mV, then the emitter of the PNP should be connected to a high supply voltage. The V P output has two charge-pump stages added to VMAIN. The emitter of the PNP can be connected to the output of the first stage as shown in Figure 12. For higher efficiency, the first charge-pump stage can be connected to VIN rather than VMAIN, as this reduces the power loss.
Chip Information
TRANSISTOR COUNT: 2396 PROCESS: BiCMOS
26
______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
VP
VN
VIN 3.3V OR 5V LX GATE IN OCP SWITCH CONTROL STEP-UP REGULATOR FB
VMAIN 9V
PGND
OCN
MAX1889
REF REF GND
Figure 11. Disabling Input Protection MOSFET Switch
______________________________________________________________________________________
27
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
VP
VN
VIN LX FB STEP-UP REGULATOR
VMAIN +9V
VN
PGND DRVN
VNL -7V
FBN
NEGATIVE REGULATOR
MAX1889
DRVP REF REF GND POSITIVE REGULATOR FBP VGAMMA +8.9V
Figure 12. Generating Gamma Reference Voltage
28
______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L QFN.EPS
MAX1889
______________________________________________________________________________________
29
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
30
______________________________________________________________________________________
Triple-Output TFT LCD Power Supply with Fault Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1889
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
1 2
______________________________________________________________________________________
QFN THIN.EPS
31
Triple-Output TFT LCD Power Supply with Fault Protection MAX1889
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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