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19-1844; Rev 1; 4/01
+3V/+5V, Low-Power, 8-Bit Octal DACs with Rail-to-Rail Output Buffers
General Description
The MAX5258/MAX5259 are +3V/+5V single-supply, digital serial-input, voltage-output, 8-bit octal digital-toanalog converters (DACs). Internal precision buffers swing Rail-to-Rail (R) , and the reference input range extends from ground to the positive supply. The +5V (MAX5258) and the +3V (MAX5259) feature a 10A (max) shutdown mode. The serial interface is double-buffered. A 16-bit input shift register is followed by eight 8-bit input registers and eight 8-bit DAC registers. The 16-bit serial word consists of two "don't care" bits, three address bits, three control bits, and eight data bits. The input and DAC registers can both be updated independently or simultaneously with a single software command. The asynchronous control input (LDAC) provides simultaneous updating of all eight DAC registers. The interface is compatible with SPITM, QSPITM (CPOL = CPHA = 0 or CPOL = CPHA = 1), and MICROWIRETM. A buffered digital data output allows daisy-chaining of serial devices. The MAX5258/MAX5259 are available in a 16-pin QSOP package. o Low Supply Current: 1.3mA o Low-Power Shutdown Mode 0.54mA (MAX5259) 0.80mA (MAX5258) o 1LSB DNL (max) o 1LSB INL (max) o Ground to VDD Reference Input Range o Output Buffer Amplifiers Swing Rail-to-Rail o 10MHz Serial Interface, SPI, QSPI (CPOL = CPHA = 0 or CPOL = CPHA = 1), and MICROWIRECompatible o Double-Buffered Registers for Synchronous Updating o Serial Data Output for Daisy-Chaining o Ultra-Small 16-Pin QSOP Package
Features
o +2.7V to +5.5V Single-Supply Operation
MAX5258/MAX5259
________________________Applications
Digital Gain and Offset Adjustment Programmable Attenuators Programmable Current Sources Portable Instruments
PART
Ordering Information
SUPPLY TEMP. RANGE PIN-PACKAGE VOLTAGE (V) 16 QSOP 16 QSOP +5.0 +3.0
MAX5258EEE -40oC to +85oC MAX5259EEE -40oC to +85oC
Pin Configuration
TOP VIEW
OUTB 1 OUTA 2 GND 3 VDD 4 REF 5 LDAC 6 16 OUTC 15 OUTD 14 DOUT
MAX5258 MAX5259
13 DIN 12 SCLK 11 CS 10 OUTH 9 OUTG
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
OUTE 7 OUTF 8
QSOP 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V DIN, DOUT, CS, SCLK, LDAC to GND.....................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin Plastic QSOP (derate 8.3mW/C about +70C)...667mW Operating Temperature Range ..........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX5258)
(VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Zero-Code Error Zero-Code Error Supply Rejection Zero-Code Temperature Coefficient Full-Scale Error Full-Scale Error Supply Rejection Full-Scale Temperature Coefficient REFERENCE INPUTS Input Voltage Range Input Resistance Input Capacitance DAC OUTPUTS Output Voltage Swing Output Voltage Range DIGITAL INPUTS Input High Voltage Input Low Voltage VIH VIL 0.7 VDD 0.3 VDD V V RL = 10k to GND RL = 10k to GND 0 0 VDD 0.3 VREF V V 0 161 230 20 VDD 300 V k pF INL DNL ZCE Guaranteed monotonic (all codes) Code = 0A hex Code = 0A hex Code = 0A hex Code = FF hex Code = FF hex Code = FF hex 8 0.1 0.05 2.5 0.02 10 1 0.25 10 30 1 1 1 20 1 Bits LSB LSB mV LSB V/oC mV LSB V/oC SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (MAX5258) (continued)
(VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.)
PARAMETER Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time Digital Feedthrough Digital-to-Analog Glitch Impulse Signal-to-Noise Plus Distortion Ratio Code = FF hex To 1/2 LSB, from code 0A to code FF hex (Note 2) Code = 00 hex Code = 80 to code = 7F hex VREF = 4Vp-p at 1kHz centered at 2.5V code = FF hex SINAD VREF = 4Vp-p at 10kHz centered at 2.5V code = FF hex VREF = 0.1Vp-p centered at VDD/2, -3dB bandwidth 55 700 16 VDD IDD ISHDN 4.5 1.4 0.45 5.5 2.6 10 kHz V V mA A 0.55 10 0.15 30 68 dB V/s s nV-s nV-s VOH VOL ISOURCE = 0.2mA ISINK = 1.6mA VDD 0.5 0.4 V V SYMBOL IIN CIN VIN = 0 to VDD (Note 3) 10 CONDITIONS MIN TYP MAX 1.0 UNITS A pF
MAX5258/MAX5259
Multiplying Bandwidth Wideband Amplifier Noise POWER REQUIREMENTS Power-Supply Voltage Supply Current Shutdown Supply Current
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3
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
ELECTRICAL CHARACTERISTICS (MAX5259)
(VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V, and TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Non Linearity (Note 1) Differential Non Linearity (Note 1) Zero-Code Error Zero-Code Error Supply Rejection Zero-Code Temperature Coefficient Full-Scale Error Full-Scale Error Supply Rejection Full-Scale Temperature Coefficient REFERENCE INPUTS Input Voltage Range Input Resistance Input Capacitance DAC OUTPUTS Output Voltage Swing Output Voltage Range DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time Code = FF hex To 1/2 LSB, from code 0A to code FF hex (Note 2) 0.55 7 V/s s VOH VOL ISOURCE = 0.2mA ISINK = 1.6mA VDD - 0.5 0.4 V V VIH VIL IIN CIN VIN = 0 to VDD (Note 3) 10 0.7 x VDD 0.3 x VDD 1.0 V V A pF RL = 10kto GND RL = 10k to GND 0 0 VDD - 0.3 VREF V V 0 161 218 20 VDD 300 V k pF INL DNL ZCE Guaranteed monotonic (all codes) Code = 0A hex Code = 0A hex. Code = 0A hex Code = FF hex Code = FF hex Code = FF hex 8 0.1 0.1 2.5 0.15 10 0.7 0.2 10 30 1 1 1 20 1 Bits LSB LSB mV LSB V/oC mV LSB V/oC SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (MAX5259) (continued)
(VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V, and TA = +25C.)
PARAMETER Digital Feedthrough Digital-to-Analog Glitch Impulse Signal-to-Noise Plus Distortion Ratio SYMBOL Code = 00 hex Code = 80 to code = 7F hex VREF = 2.5Vp-p at 1kHz centered at 1.5V code = FF hex SINAD VREF = 2.5Vp-pat 10kHz centered at 1.5V code = FF hex VREF = 0.1Vp-p centered at VDD/2, -3dB bandwidth 54 700 60 VDD IDD ISHDN 2.7 1.3 0.24 3.6 2.6 10 kHz V V mA A CONDITIONS MIN TYP 0.1 20 65 dB MAX UNITS nV-s nV-S
MAX5258/MAX5259
Multiplying Bandwidth Wideband Amplifier Noise POWER REQUIREMENTS Power-Supply Voltage Supply Current Shutdown Supply Current
TIMING CHARACTERISTICS (MAX5258)
(VREF = +4.096V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25C.)
PARAMETER VDD Rise-to-CS Fall-Setup Time LDAC Pulse Width Low CS Rise-to-LDAC Fall-Setup Time (Note 4) CS Pulse Width High SCLK Clock Frequency (Note 5) SCLK Pulse Width High SCLK Pulse Width Low CS Fall-to-SCLK Rise-Setup Time SCLK Rise-to-CS Rise-Hold Time DIN to SCLK Rise-to-Setup Time DIN to SCLK Rise-to-Hold Time SCLK Rise-to-DOUT Valid Propagation Delay (Note 6) SCLK Fall-to-DOUT Valid Propagation Delay (Note 7) CS Rise-to-SCLK Rise-Setup Time SYMBOL tVDCS tLDAC tCLL tCSW fCLK tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS1 40 40 40 40 0 40 0 200 210 40 40 90 10 CONDITIONS MIN TYP 5 20 MAX UNITS s ns ns ns MHz ns ns ns ns ns ns ns ns ns
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
TIMING CHARACTERISTICS (MAX5259)
(VREF = +2.5V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25C.)
PARAMETER VDD Rise-to-CS Fall-Setup Time LDAC Pulse Width Low CS Rise-to-LDAC Fall-Setup Time (Note 4) CS Pulse Width High SCLK Clock Frequency (Note 5) SCLK Pulse Width High SCLK Pulse Width Low CS Fall-to-SCLK Rise-Setup Time SCLK Rise-to-CS Rise-Hold Time DIN to SCLK Rise-to-Setup Time DIN to SCLK Rise-to-Hold Time SCLK Rise-to-DOUT Valid Propagation Delay (Note 6) SCLK Fall-to-DOUT Valid Propagation Delay (Note 7) CS Rise-to-SCLK Rise-Setup Time SYMBOL tVDCS tLDAC tCLL tCSW fCLK tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS1 40 40 40 40 0 40 0 200 210 40 40 90 10 CONDITIONS MIN TYP 5 20 MAX UNITS s ns ns ns MHz ns ns ns ns ns ns ns ns ns
Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.) Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of VOUT. Note 3: Guaranteed by design, not production tested. Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for tLDAC or longer after CS goes high. Note 5: When DOUT is not used. If DOUT is used, fCLK (max) is 4MHz due to SCLK to DOUT propagation delay. Note 6: Serial data is clocked-out at SCLK's rising edge (measured from 50% of the clock edge to 20% or 80% of VDD). Note 7: Serial data is clocked-out at SCLK's falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).
6
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX5258/MAX5259
DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
MAX5258/9 toc01
DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
DAC FULL-SCALE OUTPUT VOLTAGE (mV) DAC ZERO-CODE OUTPUT VOLTAGE (mV) VDD = +5V 1.25 1.00 0.75 0.50 0.25 0
MAX5258/9 toc02
DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
VDD = +3V 3.0
MAX5258/9 toc03
800 DAC ZERO-CODE OUTPUT VOLTAGE (mV) VDD = +3V 700 600 500 400 300 200 100 0 0 1 2 3 4 5 DAC OUTPUT SINK CURRENT (mA)
1.50
3.5
2.5
2.0
1.5
1.0 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 DAC OUTPUT SINK CURRENT (mA) DAC OUTPUT SOURCE CURRENT (mA)
DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX5258/9 toc04
SUPPLY CURRENT vs. TEMPERATURE
MAX5258/9 toc05
SUPPLY CURRENT vs. TEMPERATURE
MAX5258/9 toc06
5.5 DAC FULL-SCALE OUTPUT VOLTAGE (V) 5.0 4.5 4.0 3.5 3.0 2.5 VDD = +5V 2.0 0 1 2 3 4 5 6 7 8 DAC OUTPUT SOURCE CURRENT (mA)
1.6 1.4 SUPPLY CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 -40 -15 10 35 60 ALL DAC CODES = OO HEX VDD = +3.0V VREF = +2.5V ALL DAC CODES = FF HEX
1.8 1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 ALL DAC CODES = OO HEX 0.8 0.6 0.4 VDD = +5.0V VREF = +4.5V -40 -15 10 35 60 ALL DAC CODES = FF HEX
85
85
TEMPERATURE (C)
TEMPERATURE (C)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5258/9 toc07
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5258/9 toc08
SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +3V)
1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 ALL DAC CODES = OO HEX ALL DAC CODES = FF HEX
MAX5258/9 toc09
0.50 0.45 SUPPLY CURRENT (A) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -40 -15 10 35 60 VDD = +3V VREF = +2.5V
0.7 0.6 SUPPLY CURRENT (A) 0.5 0.4 0.3 0.2 0.1 VDD = +5V VREF = +4.5V -40 -15 10 35 60
1.8
0.4 0.2 85 0 0.5 1.0 1.5 2.0 2.5 3.0
85
TEMPERATURE (C)
TEMPERATURE (C)
REFERENCE VOLTAGE (V)
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +5V)
MAX5258/9 toc10
THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE
MAX5258/9 toc11
THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY
-25 -30 THD + NOISE (dB) -35 -40 -45 -50 -55 VREF = 0.5Vp-p VREF = 1Vp-p VREF = 2Vp-p 10 100 1k FREQUENCY (Hz) 10k 100k VREF = SINE-WAVE VDD = +3V CENTERED AT +1.5V DAC CODE = FF HEX 500kHz LOWPASS FILTER
MAX5258/9 toc12
MAX5258/9 toc15
1.8 1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 5 REFERENCE VOLTAGE (V) ALL DAC CODES = OO HEX ALL DAC CODES = FF HEX
0 -10 -20 THD + NOISE (dB) -30 -40 -50 -60 VREF = 1kHz -70 -80 0 0.5 1.0 1.5 VREF = SINE-WAVE VDD = +3V CENTERED AT +1.5V DAC CODE = FF HEX 80kHz LOWPASS FILTER
-20
VREF = 20kHz
-60 -65 2.0 -70
REFERENCE AMPLITUDE (Vp-p)
REFERENCE INPUT FREQUENCY RESPONSE
MAX5258/9 toc13
REFERENCE FEEDTHROUGH vs. FREQUENCY
-55 RELATIVE OUTPUT (dB) -60 -65 -70 -75 -80 -85 -90 OUTA VREF = 3Vp-p SINE-WAVE DAC CODE = OO HEX VDD = +3V
MAX5258/9 toc14
WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE)
5 0 -5 RELATIVE OUTPUT (dB) -10 -15 -20 -25 -30 -35 -40 -45 1 10 100 1k 10k 100k 1M VREF = 0.1Vp-p SINE-WAVE CENTERED AT 2.5V DAC CODE = FF HEX VDD = +3V
-50
3V CS 0
50mV/div
10M
100
1k
10k
100k
1M
10M VDD = +3V VREF = +2.5V
FREQUENCY (Hz)
FREQUENCY (Hz)
1s/div DAC CODE = 7F TO 80 HEX NO-LOAD
WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE)
MAX5258/9 toc16
WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE)
MAX5258/9 toc17
3V CS 0 CS
3V 0
OUTA
50mV/div OUTA
50mV/div
VDD = +3V VREF = +2.5V
1s/div DAC CODE = 80 TO 7F HEX NO-LOAD
VDD = +5V VREF = +4.5V
1s/div DAC CODE = 7F TO 80 HEX NO-LOAD
8
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE)
MAX5258/9 toc18
MAX5258/MAX5259
CLOCK FEEDTHROUGH
MAX5258/9 toc19
3V CS 0 SCLK
3V 0
OUTA
50mV/div
OUTA
1mV/div
VDD = +5V VREF = +4.5V
1s/div DAC CODE = 80 TO 7F HEX NO-LOAD
1s/div DAC CODE = 00 HEX VDD = +3V VREF = +2.5V NO-LOAD SCLK = 333 kHz
POSITIVE SETTLING TIME
MAX5258/9 toc20
POSITIVE SETTLING TIME
MAX5258/9 toc21
3V CS 0 CS
3V 0
1.0V/div OUTA OUTA
2.0V/div
VDD = +3V VREF = +2.5V
2s/div DAC CODE = 00 TO FF HEX NO-LOAD
VDD = +5V VREF = +4.5V
4s/div DAC CODE = 00 TO FF HEX NO-LOAD
NEGATIVE SETTLING TIME
MAX5258/9 toc22
NEGATIVE SETTLING TIME
MAX5258/9 toc23
3V CS 0 CS
3V 0
OUTA
1.0V/div
OUTA
2.0V/div
VDD = +3V VREF = +2.5V
4s/div DAC CODE = FF TO 00 HEX NO-LOAD
VDD = +5V VREF = +4.5V
4s/div DAC CODE = FF TO 00 HEX NO-LOAD
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME OUTB OUTA GND VDD REF LDAC OUTE OUTF OUTG OUTH CS SCLK DIN DOUT OUTD OUTC FUNCTION DAC B Voltage Output DAC A Voltage Output Ground Power Supply Reference Voltage Input Load DAC Input. Driving this asynchronous input low transfers the contents of each input register to its respective DAC registers. DAC E Voltage Output DAC F Voltage Output DAC G Voltage Output DAC H Voltage Output Chip Select Input. Data is shifted in and out when CS is low. Programming commands are executed when CS returns high. Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling edge (default) or rising edge (A2 = 1; see Table 1). Serial Data Input. Data is clocked in on the rising edge of SCLK. Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the falling edge (mode 0) or rising edge (mode 1) of SCLK (Table 1). DAC D Voltage Output DAC C Voltage Output
Detailed Description
Serial Interface
At power-on, the serial interface and all DACs are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's falling edge. The MAX5258/MAX5259 communicate with microprocessors (Ps) through a synchronous, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in two 4-bit and one 8-bit (byte) packets, or one 16-bit word. The first two bits are ignored. A 4-wire interface adds a line for LDAC, allowing asynchronous updating. Data is transmitted and received simultaneously. Figure 2 shows the detailed serial-interface timing. Note that the clock should be low if it is stopped between updates. DOUT does not go into a high-impedance state if the clock idles or CS is high. Serial data is clocked into the data registers in MSB-first format, with the address and configuration information preceding the actual DAC data. Data is clocked in on SCLK's rising edge while CS is low. Data at DOUT is
10
clocked out 16 clock cycles later, either at SCLK's falling edge (default or mode 0) or rising edge (mode 1). CS must be low to enable the device. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX5258/MAX5259's internal shift register on the rising edge of the external serial clock. Always clock in the full 16 bits. Serial Input Data Format and Control Codes The 16-bit serial input format, shown in Figure 3, comprises two "don't care" bits, three DAC address bits (A2, A1, A0), three control bits (C2, C1, C0), and eight data bits (D7...D0). The 6-bit address/control code configures the DAC as shown in Table 1.
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
INSTRUCTION EXECUTED
CS
SCLK
DIN X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DACA X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DACA
DOUT MODE 1 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DATA FROM PREVIOUS DATA INPUT X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DATA FROM PREVIOUS DATA INPUT
DOUT MODE 0 (DEFAULT) X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 1. 3-Wire Interface Timing
CS tCSW tCSS tCL SCLK tDS tDH DIN tD02 tD01 DOUT tCLL tLDAC LDAC tCH tCP tCSH tCS1
Figure 2. Detailed Serial-Interface Timing Diagram
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD* A2 X X X 0 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X A1 X X X X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A0 X X X X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X C2 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 C0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 D7......D0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data XXXXXXXX X X X X X X H H H H H H H H H H H H H H H H H No operation (NOP); shift data in shift registers. Clears all input and DAC registers and sets all DAC outputs to zero. Software shutdown. Output buffers can be individually shut down with zeros in the corresponding data bits. DOUT Phase Mode 0. DOUT transitions on the falling edge of SCLK. DOUT Phase Mode 1. DOUT transitions on the rising edge of SCLK. Loads all DACs with the same data Load input register A. All DAC outputs unchanged. Load input register B. All DAC outputs unchanged. Load input register C. All DAC outputs unchanged. Load input register D. All DAC outputs unchanged. Load input register E. All DAC outputs unchanged. Load input register F. All DAC outputs unchanged. Load input register G. All DAC outputs unchanged. Load input register H. All DAC outputs unchanged. Load input register A. Update OUTA. All other DAC outputs unchanged. Load input register B. Update OUTB. All other DAC outputs unchanged. Load input register C. Update OUTC. All other DAC outputs unchanged. Load input register D. Update OUTD. All other DAC outputs unchanged. Load input register E. Update OUTE. All other DAC outputs unchanged. Load input register F. Update OUTF. All other DAC outputs unchanged. Load input register G. Update OUTG. All other DAC outputs unchanged. Load input register H. Update OUTH. All other DAC outputs unchanged. Software LDAC command. Updates all DACs from their respective input registers. LDAC FUNCTION
* The first two bits are "don't care."
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers
No Operation (NOP)
A2 A1 Don't Care A0 C2 0 C1 0 C0 0 D7 D6 D5 D4 D3 Don't Care D2 D1 D0
MAX5258/MAX5259
(LDAC = X) The no-operation (NOP) command allows data to be shifted through the MAX5258/MAX5259 shift register without affecting the input or DAC registers. This is useful in daisy-chaining (see the Daisy-Chaining Devices section). For this command, the data bits are "Don't Cares." As an example, three MAX5258s are daisy-chained (A, B, and C), and devices A and C need to be updated. The 48-bit-wide command would consist of one 16-bit word for device C, followed by an NOP instruction for device B and a third 16-bit word with data for device A. At the rising edge of CS, device B will not change state. Clear
A2 A1 Don't Care A0 C2 0 C1 0 C0 1 D7 D6 D5 D4 D3 D2 D1 D0
Don't Care
(LDAC = X) The clear command clears all input and DAC registers and sets all DAC outputs to zero. This command brings the DAC out of shutdown. Software Shutdown
A2 A1 Don't Care A0 C2 0 C1 1 C0 0 D7 D6 D5 D4 D3 D2 D1 D0
8-Bit Data
(LDAC = X) Shuts down all output buffer amplifiers and voltage references. Output buffers can be individually disabled with the corresponding zeros in the data bits (D7-D0). If all data bits are zero, only the power-on reset circuit is active, and the device draws 10A (max). There are four ways to bring the device out of shutdown: POR, CLEAR, LOAD SAME DATA, LOAD INPUT, AND DAC REGISTERS. Set DOUT Phase--SCLK Falling (Mode 0, Default)
A2 0 A1 X A0 X C2 0 C1 1 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0
(LDAC = X) This command sets DOUT to transition at the falling edge of SCLK. The same command also updates all DAC registers with the contents of their respective input registers, identical to the LDAC command. This is the default mode on power-up. Set DOUT Phase--SCLK Rising (Mode 1)
A2 1 A1 X A0 X C2 0 C1 1 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0
(LDAC = X) Mode 1 sets the serial output DOUT to transition at the rising edge of SCLK. Once this command is issued, DOUT's phase is latched and will not change except on power-up or if the specific command to set the phase to falling edge is issued. This command also loads all DAC registers with the contents of their respective input registers, and is identical to the LDAC command.
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
Load All DACs with Shift-Register Data
A2 A1 Don't Care A0 C2 1 C1 0 C0 0 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0
(LDAC = X) All eight DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLEAR if code 00 (hex) is programmed, which clears all DACs. This command brings the device out of shutdown.
Load Input Register, DAC Registers Unchanged (Single Update Operation)
A2 A1 Address A0 C2 1 C1 0 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0
(LDAC = X) When performing a single update operation, A2-A0 selects the respective input register. At the rising edge of CS, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs.
Load Input and DAC Registers
A2 A1 Address A0 C2 1 C1 1 C0 0 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0
(LDAC = X) This command directly loads current shift-register data in the selected input and DAC registers at the rising edge of CS. A2-A0 set the DAC address. For example, to load all eight DAC registers simultaneously with individual settings, eight commands are required. First perform seven single input register update operations (C2 = 1, C1 = 0, C0 = 1) for DACs A, B, C, D, E, F, and G (C2 = 1, C1 = 0, C0 = 1). The final command loads input register H and updates all eight DAC registers from their respective input registers. This command brings the device out of shutdown.
Software "LDAC" Command
A2 A1 Address A0 C2 1 C1 1 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0
(LDAC = X) All DAC registers are updated with the contents of their respective input registers at the rising edge of CS. This is a synchronous software command that performs the same function as the asynchronous LDAC.
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers
LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 4). This command is level sensitive, and it allows asynchronous hardware control of the DAC outputs. With LDAC low, all eight DAC registers are transparent, and any time an input register is updated, the DAC output immediately follows. Serial Data Output DOUT is the internal shift-register's output. DOUT can be programmed to clock out data on the falling edge of SCLK (mode 0) or the rising edge (mode 1). In mode 0, output data lags input data by 16.5 clock cycles, maintaining compatibility with MICROWIRE and SPI. In mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to mode 0 timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when CS is high. Interfacing to the Microprocessor The MAX5258/MAX5259 are MICROWIRE (Figure 5) and SPI/QSPI (Figure 6) compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored. The MAX5258/MAX5259 can interface with Intel's 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted. Universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. See the Clock Feedthrough photo in the Typical Operating Characteristics section. The clock idle state is low. Daisy-Chaining Devices Any number of MAX5258/MAX5259s can be daisychained by connecting DOUT of one device to DIN of the following device in the chain with all devices in mode zero. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A 3-wire interface updates daisy-chained or individual MAX5258/MAX5259s simultaneously by bringing CS high (Figure 7).
MAX5258/MAX5259
THIS IS THE FIRST BIT SHIFTED IN MSB DOUT LSB DIN
X X A2 A1 A0 C2 C1 C0 D7 D6 . . . D1 D0 CONTROL AND ADDRESS BITS 8-BIT DAC DATA
Figure 3. Serial Input Format
column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 8 shows a simplified diagram of one of the eight DACs. Reference Input The voltage at REF sets the full-scale output voltage for all eight DACs. The 230k typical input impedance at REF is code independent. The output voltage for any DAC can be represented by a digitally programmable voltage source as follows: VOUT = (NB VREF) / 256, where NB is the numerical value of the DAC's binary input code. Output Buffer Amplifiers All MAX5258/MAX5259 voltage outputs are internally buffered by precision unity-gain followers that slew at about 0.55V/s. The outputs can swing from GND to VDD. With a 0 to VREF (or VREF to 0) output transition, the amplifier outputs will typically settle to 1/2LSB in 10s when loaded with 10k in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive (10k) or capacitive (100pF) loads.
Applications Information
DAC Linearity and Voltage Offset
The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply, the output remains at GND (Figure 9). When linearity is determined using the endpoint method, it is measured between code 10 (0A hex) and full-scale code (FF hex) after offset and gain error are calibrated out. With a single-supply, negative offset causes the output not to change with an input code transition near zero (Figure 9). Thus, the lowest code that produces a positive output is the lower endpoint.
Analog Section
DAC Operation The MAX5258/MAX5259 use a matrix decoding architecture for the DACs, which saves power in the overall system. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and
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15
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
DIN SCLK LDAC CS1 CS2 CS3 CS CS CS TO OTHER SERIAL DEVICES
MAX5258/ LDAC MAX5259
SCLK DIN
MAX5258/ LDAC MAX5259
SCLK DIN
MAX5258/
LDAC MAX5259 SCLK DIN
Figure 4. Multiple MAX5258's Sharing One DIN Line. (Simultaneously Update by Strobing LDAC, or Specifically Update by Enabling an Individual CS)
SCLK
SK SO
MAX5258/ DIN MAX5259
MICROWIRE PORT
MAX5258/ MAX5259
DIN SCLK
MOSI SPI/QSPI
PORT
SCK I/O CPOL = 0, CPHA = 0
CS
I/O
CS
Figure 5. Connections for MICROWIRE
Figure 6. Connections for SPI/QSPI
MAX5258/
SCLK DIN CS SCLK MAX5259 DIN CS DEVICE A DOUT
MAX5258/
SCLK MAX5259 DIN CS DEVICE B DOUT
MAX5258/
SCLK MAX5259 DIN CS DEVICE C DOUT TO OTHER SERIAL DEVICES
MAX5258/
SCLK DIN CS SCLK MAX5259 DIN CS
Figure 7. Daisy-Chained or Individual MAX5258s Simultaneously Updated by Bringing CS High (Only Three Wires Are Required)
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
REF R0 R1 R15
D7 D6 D5 D4 MSB DECODER R16 OUTPUT VOLTAGE R255
O NEGATIVE OFFSET LSB DECODER D3 D2 D1 D0
DAC CODE
DAC A
Figure 8. DAC Simplified Circuit Diagram
Figure 9. Effect of Negative Offset (Single Supply)
SYSTEM GND
ratings. Do not apply signals to the digital inputs before the device is fully powered-up.
OUTB OUTA GND VDD REF LDAC
OUTC OUTD DOUT DIN
Power-Supply Bypassing and Ground Management
Bypass VDD with a 0.1F capacitor, located as close to VDD and GND as possible. Careful PC board layout minimizes crosstalk among DAC outputs and digital inputs. Figure 10 shows suggested circuit board layout to minimize crosstalk.
Unipolar-Output, Two-Quadrant Multiplication
In unipolar operation, the output voltages and the reference input are the same polarity. Figure 11 shows the MAX5258/MAX5259 unipolar configuration, and Table 2 shows the unipolar code.
Figure 10. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View)
Power Sequencing
The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum
______________________________________________________________________________________ 17
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
REFERENCE INPUT REF +3V
Table 2. Unipolar Code Table
DAC CONTENTS MSB
OUT A
VDD
ANALOG OUTPUT +VREF(255/256) +VREF(129/256) +VREF(128/256) = +VREF/2 +VREF(127/256) +VREF(1/256) 0
LSB 1111 0001 0000 1111 0001 0000
1111 1000 1000 0111 0000
DAC A
OUT B DAC B
0000
Note: 1LSB = (VREF) (28) = +VREF (1 / 256)
OUT C
____________________Chip Information
TRANSISTOR COUNT: 13625 PROCESS: BiCMOS
DAC C
OUT D DAC D
OUT E DAC E
OUT F DAC F
OUT G DAC G
OUT H DAC H
MAX5258/ MAX5259
Figure 11. Unipolar Output Circuit
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+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
Functional Diagram
DOUT LDAC VDD REF
DECODE CONTROL INPUT REGISTER A DAC REGISTER A
OUT A DAC A
OUT B INPUT REGISTER B DAC REGISTER B DAC B
OUT C INPUT REGISTER C DAC REGISTER C DAC C
OUT D 16-BIT SHIFT REGISTER INPUT REGISTER D DAC REGISTER D DAC D
OUT E INPUT REGISTER E DAC REGISTER E DAC E
OUT F INPUT REGISTER F DAC REGISTER F DAC F
OUT G INPUT REGISTER G DAC REGISTER G DAC G
OUT H SR CONTROL INPUT REGISTER H DAC REGISTER H DAC H
MAX5258/ MAX5259 CS DIN SCLK GND
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19
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259
Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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