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TC55V400AFT-55,-70
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION
The TC55V400AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 mA standby current (at VDD = 3 V, Ta = 25C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of -40 to 85C, the TC55V400AFT can be used in environments exhibiting extreme temperature conditions. The TC55V400AFT is available in normal and reverse pinout plastic 48-pin thin-small-outline package (TSOP).
FEATURES
* * * * * * * Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum):
3.6 V 3.0 V 7 mA 5 mA
*
Access Times (maximum):
TC55V400AFT -55 Access Time
CE1 Access Time
-70 70 ns 70 ns 70 ns 35 ns
55 ns 55 ns 55 ns 30 ns
CE2 Access Time
OE Access Time
*
Package: TSOP48-P-1214-0.50 (AFT) (Weight: 0.38 g typ)
PIN ASSIGNMENT (TOP VIEW)
48 PIN TSOP
PIN NAMES
A0~A17 1 48
CE1 , CE2
Address Inputs Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Power Ground No Connection
R/W
OE
LB , UB
I/O1~I/O16 24 (Normal) 25 VDD GND NC
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1 A15 17 A17 33 I/O3
2 A14 18 A7 34 I/O11
3 A13 19 A6 35 I/O4
4 A12 20 A5 36 I/O12
5 A11 21 A4 37 VDD
6 A10 22 A3 38 I/O5
7 A9 23 A2 39
8 A8 24 A1 40
9 NC 25 A0 41
10 NC 26
CE1
11 R/W 27 GND 43
12 CE2 28
OE
13 NC 29 I/O1 45
14
UB
15
LB
16 NC 32 I/O10 48 A16
30 I/O9 46
31 I/O2 47 NC
42
44
I/O13 I/O6
I/O14 I/O7
I/O15 I/O8
I/O16 GND
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BLOCK DIAGRAM
CE
A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A17
ROW ADDRESS BUFFER
ROW ADDRESS REGISTER
ROW ADDRESS DECODER
MEMORY CELL ARRAY 2,048 128 16 (4,194,304)
VDD GND
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
SENSE AMP DATA OUTPUT BUFFER CE
A0 A1 A2 A3 A14 A15 A16
DATA INPUT BUFFER
COLUMN ADDRESS DECODER COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER
CLOCK GENERATOR
R/W
OE UB LB CE1
CE
CE2
OPERATING MODE
MODE Read
CE1
CE2 H
OE
R/W H
LB
UB
I/O1~I/O8 Output High-Z Output Input High-Z Input High-Z High-Z
DATA OUTPUT BUFFER I/O9~I/O16 Output Output High-Z Input Input High-Z High-Z High-Z
DATA INPUT BUFFER
POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS
L L L H L L Write L L L H * H H H * L * H * * * L H * * * H L Output Deselect Standby * = don't care H = logic high L = logic low * H * *
L L H L L H * H * *
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MAXIMUM RATINGS
SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~4.6 -0.3*~4.6 -0.5~VDD + 0.5 0.6 260 -55~150 -40~85 UNIT V V V W C C C
*: -3.0 V when measured at a pulse width of 50ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C)
SYMBOL VDD VIH VIL VDH *: PARAMETER MIN Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage -3.0 V when measured at a pulse width of 50 ns 2.3 2.2 -0.3* 1.5 2.3 V~3.6 V TYP 3.0 3/4 3/4 3/4 MAX 3.6 VDD + 0.3 VDD 0.22 3.6 V V V V UNIT
DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 2.3 to 3.6 V)
SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = VDD - 0.5 V VOL = 0.4 V
CE1 = VIH or CE2 = VIL or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE1 = VIL and CE2 = VIH and R/W = VIH and IOUT = 0 mA, Other Input = VIH/VIL
TEST CONDITION
MIN 3/4 -0.5 2.1 3/4 55 ns 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
TYP 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.05 3/4 3/4
MAX 1.0 3/4 3/4 1.0 70 60 10 65 55 5 2 0.6 6 0.7 7 0.5 1 5
UNIT mA mA mA mA
lDDO1 Operating Current lDDO2
VDD = t 3 V 10% cycle
70 ns 1 ms 55 ns 70 ns 1 ms
mA
CE1 = 0.2 V and VDD = CE2 = VDD - 0.2 V and t R/W = VDD - 0.2 V, IOUT = 0 mA, 3 V 10% cycle Other Input = VDD - 0.2 V/0.2 V CE = VIH or CE2 = VIL
mA
IDDS1
mA
VDD = 3 V 10% IDDS2 (Note) Standby Current
CE1 = VDD - 0.2 V or CE2 = 0.2 V VDD = 1.5 V~3.6 V
Ta = 25C Ta = -40~85C Ta = 25C Ta = -40~85C Ta = 25C Ta = -40~40C Ta = -40~85C
VDD = 3.3 V 0.3 V VDD = 3.0 V
mA
Note:
In standby mode with CE1 VDD - 0.2 V, these limits are assured for the condition CE2 VDD - 0.2 V or CE2 0.2 V.
CAPACITANCE (Ta = 25C, f = 1 MHz)
SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF
This parameter is periodically sampled and is not 100% tested.
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AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = -40 to 85C, VDD = 2.7 to 3.6 V) READ CYCLE
TC55V400AFT SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time 55 3/4 3/4 3/4 3/4 3/4 5 0 0 3/4 3/4 3/4 10 -55 MAX 3/4 55 55 55 30 30 3/4 3/4 3/4 25 25 25 3/4 MIN 70 3/4 3/4 3/4 3/4 3/4 5 0 0 3/4 3/4 3/4 10 -70 MAX 3/4 70 70 70 35 35 3/4 3/4 3/4 30 30 30 3/4 ns UNIT
WRITE CYCLE
TC55V400AFT SYMBOL PARAMETER MIN tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 55 45 50 45 0 0 3/4 0 25 0 -55 MAX 3/4 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 MIN 70 50 60 50 0 0 3/4 0 30 0 -70 MAX 3/4 3/4 3/4 3/4 3/4 3/4 30 3/4 3/4 3/4 ns UNIT
AC TEST CONDITIONS
PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 30 pF + 1 TTL Gate 0.4 V, 2.4 V VDD 0.5 VDD 0.5 5 ns
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AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = -40 to 85C, VDD = 2.3 to 3.6 V) READ CYCLE
TC55V400AFT SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time 70 3/4 3/4 3/4 3/4 3/4 5 0 0 3/4 3/4 3/4 10 -55 MAX 3/4 70 70 70 35 35 3/4 3/4 3/4 30 30 30 3/4 MIN 85 3/4 3/4 3/4 3/4 3/4 5 0 0 3/4 3/4 3/4 10 -70 MAX 3/4 85 85 85 45 45 3/4 3/4 3/4 35 35 35 3/4 ns UNIT
WRITE CYCLE
TC55V400AFT SYMBOL PARAMETER MIN tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 70 50 60 50 0 0 3/4 0 30 0 -55 MAX 3/4 3/4 3/4 3/4 3/4 3/4 30 3/4 3/4 3/4 MIN 85 55 70 55 0 0 3/4 0 35 0 -70 MAX 3/4 3/4 3/4 3/4 3/4 3/4 35 3/4 3/4 3/4 ns UNIT
AC TEST CONDITIONS
PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD 0.5 VDD 0.5 5 ns
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TIMING DIAGRAMS
READ CYCLE
(See Note 1)
tRC Address tACC tCO1
CE1
tOH
tCO2 CE2 tOE
OE
tOD
tBA
UB , LB
tODO
tBE tOEE DOUT Hi-Z tCOE INDETERMINATE
tBD VALID DATA OUT Hi-Z
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
tWC Address tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tODW DOUT (See Note 2) Hi-Z tDS DIN (See Note 5)
tOEW (See Note 3) tDH (See Note 5)
VALID DATA IN
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WRITE CYCLE 2 ( CE1 CONTROLLED)
(See Note 4)
tWC Address tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tBE DOUT Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN
(See Note 5)
VALID DATA IN
WRITE CYCLE 3 (CE2 CONTROLLED)
(See Note 4)
tWC Address tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tBE DOUT Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN
(See Note 5)
VALID DATA IN
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WRITE CYCLE 4 ( UB, LB CONTROLLED)
(See Note 4)
tWC Address tAS R/W tCW
CE1
tWP
tWR
tCW CE2 tBW
UB , LB
tBE DOUT Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN
(See Note 5)
VALID DATA IN
Note: (1) (2) (3) (4) (5)
R/W remains HIGH for the read cycle. If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
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DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C)
SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.0 V IDDS2 Standby Current Ta = -40~40C Ta = -40~85C MIN 1.5 3/4 3/4 3/4 0 tRC
(See Note)
TYP 3/4 3/4 3/4 3/4 3/4 3/4
MAX 3.6 1 5 7 3/4 3/4
UNIT V
mA
VDH = 3.6 V Ta = -40~85C tCDR tR Note: Chip Deselect to Data Retention Mode Time Recovery Time Read cycle time
ns ns
CE1 CONTROLLED DATA RETENTION MODE
VDD
(See Note 1)
VDD 2.7 V
DATA RETENTION MODE
(See Note 2) VIH
CE1
(See Note 2) VDD - 0.2 V tR
tCDR
GND
CE2 CONTROLLED DATA RETENTION MODE
VDD
(See Note 3)
VDD 2.7 V CE2 VIH VIL GND
DATA RETENTION MODE
tCDR 0.2 V
tR
Note: (1) (2) (3)
In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 0.2 V or CE2 VDD - 0.2 V. When CE1 is operating at the VIH level, the operating current is given by IDDS1 during the transition of VDD from 2.7 to 2.3V. In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 0.2 V.
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PACKAGE DIMENSIONS
Weight: 0.38 g (typ)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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