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CXA1854AR
Decoder/Driver/Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description The CXA1854AR is an IC designed exclusively to drive color LCD panels LCX009AK/AKB/LCX005BK/ BKB. This IC greatly reduces the number of circuits and parts required to drive LCD panels by incorporating RGB decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip. Features * Color LCD panels LCX009AK/AKB/LCX005BK/BKB driver * Both NTSC/PAL compatible * Supports composite inputs, Y/C inputs and Y/color difference inputs * Band-pass filter, trap and delay line * Sharpness function * 2-point compensation circuits * R, B output delay time adjustment circuit (supports both right and left inversion) * Polarity reversed circuit / line inverted mode * Supports external RGB input * Supports line inversion * Supports AC drive for LCD panel during no signal Applications * Color LCD viewfinders * Liquid crystal projectors * Industrial monitors Structure Bipolar CMOS IC 64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC1 - GND 6 * Supply voltage VCC2 - GND 14 * Supply voltage VDD - VSS 6 * Analog input pin voltage VINA -0.3 to VCC1
V V V V
* Digital input pin voltage VIND -0.3 to VDD + 0.3 V * Operating temperature range Topr -15 to +70 C * Storage temperature range Tstg -40 to +150 C * Allowable power dissipation PD (Ta 70C) 400 mW Operating conditions * Supply voltage VCC1 - GND * Supply voltage VCC2 - GND * Supply voltage LCX009 mode VDD - VSS LCX005 mode VDD - VSS
4.6 to 5.3 11.0 to 13.0 4.5 to 5.5 2.7 to 5.5
V V V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95X01A73
CXA1854AR
Block Diagram
BLKLIM
G OUT
R OUT
B OUT
TEST8
FB G
TEST7
VCC1
TEST6
VCC2
FB R
FB B
GND2
REG
RGT
48 REG. REGV B-YIN 49
47 +5V
46
45 +12V
44
43
42
41
40
39
38 GND2
37
36
35
34
33 +5V
1 VCC2 2
buf
buf
buf V-SYNC SEP 32 TEST5
R-YIN 50
CLAMP
INT/EXT PAL ID
VDD
V-POS RESET GEN DEMOD POL SW V-CTL COUNTER V-POS COUNTER
31 VD
COUT 51
PAL SW RESET XCLR
30 HD EQP BGP CLP BLK 29 HCK1
HUE/RST 52
LPF COLOR 53 APC MATRIX ACC DET R-BRT 55 COLOR CONT GAMMA KILLER RGB BRIGHT SUB CONTRAST S/H FILT CAL EXT SW CONTRAST RGB GAIN SUB BRIGHT
V-CTL DECODER
H-CTL DECODER DECODER PLL COUNTER
28 HCK2 AUX-V COUNTER H-POS COUNTER DECODER & H-TIMING PULSE GEN
XVXO 54
VXO
HUE
PS
27 HST1
26 TEST4
B-BRT 56
RGB-GAIN 57
FRP SH1 SH2 SH3 SH4
FIELD & LINE CTL PAL PULSE ELIM & MODE SEL
25 CLR
24 EN
GAMMA2 58
23 VCK1
GAMMA1 59 BPF BRIGHT 60 AGG DET CONTRAST 61 ACC AMP CIN 62
PIC CONT HALF-H KILLER AGC DL 2 H-SYNC DET H-SKEW DET MASTER SUB CK CK TEST S/R 1/7
YC/YRB/COMP SPAL/DPAL/NTSC
22 VCK2 PULSE GEN V-TIMING
21 VST1
20 TEST3
19 SLCK
R-GAIN 63
TRAP
DL 1
18 TEST0 PLL PHASE COMP
B-GAIN 64
SYNC SEP
17 TEST1
H. FILTER
CLAMP GND1
MODE SELECT
VSS 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
SYNCIN
GND1
EXT-B
RPD
AGCTC
AGCADJ
MODE2
MODE1
-2-
TEST2
PICT
EXT-G
EXT-R
CKO
YIN
VSS
CKI
CXA1854AR
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol SYNC IN Y IN AGCADJ AGCTC PICT GND1 MODE1 MODE2 EXT-R EXT-G EXT-B RPD VSS CKI CKO TEST2 TEST1 TEST0 SLCK TEST3 VST1 VCK2 VCK1 EN CLR TEST4 HST1 HCK2 HCK1 HD VD TEST5 I O I I I I O O O O O O O O O O O O I I I I I I O I/O I I I O I Sync input Y signal input AGC level adjustment AGC time constant
(H: Pull up, M: Intermediate setting, L: Pull down) Description Input pin for open status
Y signal frequency characteristics adjustment Analog 5V GND Switches between NTSC (H), DPAL (M) and SPAL (L) Switches between composite (H), Y/color difference (M) and YC input (L) External digital input R (input conditions noted separately) External digital input G (input conditions noted separately) External digital input B (input conditions noted separately) Phase comparator output Digital GND Oscillation cell input Oscillation cell output Test Test Test Switches between LCX005BK (H) and LCX009AK (L) Leave this pin open. V start pulse 1 output V clock pulse 2 output V clock pulse 1 output EN pulse output CLR pulse output Leave this pin open. H start pulse 1 output H clock pulse 2 output H clock pulse 1 output HD pulse output VD pulse output Leave this pin open. L L L L L M M
DPAL supports demodulation methods which use an external delay line during demodulation; SPAL supports methods which internally process chroma demodulation.
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CXA1854AR
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol VDD RGT TEST6 TEST7 TEST8 GND2 R OUT FB R G OUT FB G B OUT FB B VCC2 BLKLIM VCC1 REG B-YIN R-YIN COUT HUE/RST COLOR XVXO R-BRT B-BRT RGB-GAIN GAMMA2 GAMMA1 BRIGHT CONTRAST CIN R-GAIN B-GAIN
I/O Digital 5V power supply I I I I
Description
Input pin for open status
Switches between Normal scan (H) and Reverse scan (L) Leave this pin open. Leave this pin open. Leave this pin open. Analog 12V GND
H H H H
O I O I O I
R output R signal DC voltage feedback input G output G signal DC voltage feedback input B output B signal DC voltage feedback input Analog 12V power supply
I
Black peak limiter level adjustment Analog 5V power supply
O I I O I I I I I I I I I I I I I
Constant voltage capacitor connection B-Y demodulator input (or B-Y/color difference signal input) R-Y demodulator input (or R-Y/color difference signal input) Chroma signal output (for PAL 1HDL) Hue adjustment/system reset Color adjustment VXO crystal oscillator connection R brightness adjustment B brightness adjustment RGB gain adjustment 2 adjustment 1 adjustment Brightness adjustment Contrast adjustment Chroma signal input R gain adjustment B gain adjustment
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CXA1854AR
Analog Block Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description
VCC1
200
1
SYNC IN
1 50p
Sync input. Normally inputs the Y signal. The standard signal input level is 0.5Vp-p (up to 100% white level from the sync chip).
GND1
VCC1
2
YIN
3.2V
2 1k
Y signal input. The standard signal input level is 0.5Vp-p (up to 100% white level from the sync chip). Input at low impedance (75 or less).
50A
GND1
VCC1
40k
3
AGCADJ
VCC1/2
3 2k 2.5V GND1
AGC gain adjustment pin.
VCC1 50A 1k
4
AGCTC
4 20k
AGC detection filter connection.
GND1
VCC1 1k 47k
5
PICT
VCC1/2
5 50A GND1 2.5V
Adjusts frequency characteristics of luminance signal. Increasing the voltage emphasizes contours.
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CXA1854AR
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description External digital signal input. There are two threshold values: Vth1 (approximately 1.2V) and Vth2 (approximately 2.2V). When one of the EXTRGB signals exceeds Vth1, all of the RGB outputs go to black level (black side clip level); when an input exceeds Vth2, only the corresponding output goes to white level (white side limiter level).
9
EXT-R
VCC1 9
200
10
EXT-G
10 11
GND1
11
EXT-B
39
R OUT
VCC2
41
G OUT
VCC2 2
39 41 43
50 50
RGB primary color signal output.
43
B OUT
GND2
40
FB R
VCC2
40
42
FB G
2k
42 44
Smoothing capacitor connection for the feedback circuit of RGB output DC level control. Use a low-leakage capacitor because of high impedance.
44
FB B
GND2
VCC1 50k 2k
46
BLKLIM
46
Sets the RGB output amplitude (black-black) clip level.
GND1
VCC1
48
REG
4.2V
48 60k 40k GND1 40k
Smoothing capacitor connection for the internally generated constant voltage source circuit. Connect a capacitor of 1F or more.
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CXA1854AR
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description Color difference demodulation circuit inputs during DPAL mode. Leave this pin open for NTSC. Color difference signal is input respectively when Y/color difference input. (Standard input is 0.15Vp-p.) At this time, the bias is 3.5V.
VCC1
49
B-YIN
49 50 200 50A 2k GND1
50
R-YIN
VCC1
51
COUT
2.3V
51 50A
Color adjusted chroma signal is output. When taking the chroma signal, connect to GND with a load resistor (approximately 5k).
GND1
VCC1 6k 100k
52
HUE/RST
3.2V
52 12k 3.2V GND1 50A 5p
Color phase adjustment pin during NTSC. Use for detective axis adjustment of the R-Y/B-Y axes during SPAL. Also doubles as the reset pin. The system is reset when this pin is connected to GND.
VCC1
100k
53
COLOR
3.2V
53 25k 3.2V GND1 50A 5p
Color adjustment.
VCC1 2k 500
54
XVXO
3.5V
54
Crystal oscillator connection.
GND1
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CXA1854AR
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
55
RBRT VCC1/2
VCC1
47k 55 56 3k 2.5V GND1
Fine adjustment for R and B signal brightness.
56
BBRT
VCC1
57
RGB-GAIN
VCC1/2
47k 57 3k 2.5V GND1
Adjusts RGB output amplitude gain.
VCC1
58
GAMMA2
VCC1/2
47k 58 3k 2.5V GND1
Adjusts voltage gain change point 2.
VCC1
59
GAMMA1
VCC1/2
47k 59 3k 2.5V GND1
Adjusts voltage gain change point 1.
VCC1
60
BRIGHT
VCC1/2
47k 60 4k 2.5V GND1
RGB output brightness adjustment. It does not influence the compensation curve.
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CXA1854AR
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
61
CONTRAST
VCC1/2
47k 61 4k 2.5V GND1
Contrast adjustment.
VCC1 20k
62
CIN
500 62 100A GND1
15p
50A
Video signal input when using composite input. Chroma signal input when using Y/C input. Leave this pin open when Y/color difference input.
VCC1
63
R-GAIN VCC1/2
47k 63 64 3k 2.5V GND1
Fine adjustment for R and B signal contrast.
64
B-GAIN
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CXA1854AR
Setting Conditions for Measuring Electrical Characteristics When measuring the DC characteristics, the TG block must be horizontally synchronized by performing Setting 2. Setting 2 must also be performed when measuring the AC characteristics. When measuring items with bands greater than 2MHz such as the Y frequency response or sharpness characteristics, settings 1 and 3 must also be performed and measurements made with the sample-and-hold circuit set to through status. Setting 1. System reset After turning on the power, set SW52 to ON and start up V52 from GND in order to activate the timing controller system reset. (See Fig. 1-1.) Setting 2. Horizontal AFC adjustment Input SIG6 (VL = 0mV) to (A) and adjust VR12 so that WL and WH of the TP12 output waveform are the same. (See Fig. 1-2.) Setting 3. S/H off Input the signals shown in Fig. 1-3 to Pins 16, 17, 18 and 19 in order to set the sample-and-hold circuit to through status.
VDD (VCC1)
SIG6 WS
TP12 V52 (RESET) WL TR TR > 10s WH WL = WH
Fig. 1-1. System reset
Fig. 1-2. Horizontal AFC adjustment
VDD Pin 19 GND VDD Pin 18 GND VDD Pin 17 GND VDD Pin 16 GND
Fig. 1-3. S/H off input pattern - 10 -
CXA1854AR
Electrical Characteristics - DC Characteristics (1) Unless otherwise specified, Setting 2 and the following setting conditions are required. VCC1 = 5.0V, VCC2 = 12.0V, GND1 = GND2 = GND, VDD = 5.0V, VSS = GND V3, V5, V46, V55, V56, V57, V58, V59, V60, V61, V63, V64 = 2.5V V52, V53 = 3.2V SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A. Item Symbol Conditions Min. Typ. Max. Unit
Power supply characteristics ICC11 Input SIG5 to (A) and SIG3 (0dB) to (B). Measure the ICC1 current value. COMP input mode Input SIG5 to (A) and SIG3 (0dB) to (B). Set SW8 to C. Measure the ICC1 current value. Y/C input mode Input SIG5 to (A) and SIG5 to (F) and (G). Set SW8 to B. Measure the ICC1 current value. Y/color difference input mode Input SIG5 to (A) and SIG3 (0dB) to (B). Measure the ICC2 current value. Input SIG5 to (A) and SIG3 (0dB) to (B). Measure the IDD current value. LCX009 mode Input SIG5 to (A) and SIG3 (0dB) to (B). Set SW19 to B. Measure the IDD current value. LCX005 mode Input SIG5 to (A) and SIG3 (0dB) to (B). Set SW19 to B. Measure the IDD current value. 35 44 53 mA
Current consumption VCC1
ICC12
34
42.5
51
mA
ICC13
32
40
48
mA
Current consumption VCC2
ICC2
3
5.5
8
mA
IDD1
7
10.5
14
mA
Current consumption VDD
IDD2
5
8
10.5
mA
IDD3
VDD = 3.0V LCX005 mode
2
3
4.5
mA
- 11 -
CXA1854AR
Item
Symbol
Conditions
Input pin with pull-up resistor1 VIN = VSS Input pin with pull-down resistor2 VIN = VDD
Min. Typ. Max. Unit
Digital block I/O characteristics VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VOL11 VOL12 IOL = 2mA3 IOL = 500A3 IOH = -3mA 0.5VDD VDD = 5.0V VDD = 3.0V -240 -100 -144 40 24 VDD -0.8 VDD -1.0 0.5 V 0.6 0.3 V V -60 100 60 -40 A -24 240 A 144 Input current 1 II1
Input current 2 High level output voltage Output pins except CKO and RPD Low level output voltage Output pins except CKO and RPD High level output voltage CKO pin Low level output voltage CKO pin High level output voltage RPD pin Low level output voltage RPD pin Output off leak current RPD pin
II2
VOH1
IOH = -2mA3
V
VOH2
VOL2
IOL = 3mA
0.5VDD
V
VOH3
IOH = -1mA
VDD -1.2
V
VOL3
IOL = 1.5mA
1.0
V
IOFF
High impedance status VOUT = VSS or VOUT = VDD
-40
40
A
High level input voltage VIH SLCK and RGT pins Low level input voltage VIL SLCK and RGT pins Ternary input switching threshold voltage (MODE1/MODE2) MDTHL MDTHH
CMOS input cell
0.7VDD
V
CMOS input cell MODE M L level threshold SW7, SW8 = B MODE M H level threshold SW7, SW8 = B
0.3VDD
V
0.2VDD 0.3VDD 0.4VDD 0.6VDD 0.7VDD 0.8VDD
V V
1 Input pins with pull-up resistors: RGT, TEST6, TEST7, TEST8 2 Input pins with pull-down resistors: SLCK, TEST0, TEST1, TEST2, TEST5 3 Output pins except CKO and RPD: HD, VD, VST1, VCK1, VCK2, CLR, EN, HST1, HCK1, HCK2, TEST3, TEST4
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CXA1854AR
Electrical Characteristics - AC Characteristics (1) Unless otherwise specified, Setting 2 and the following setting conditions are required. Vcc1 = 5.0V, Vcc2 = 12.0V, GND1 = GND2 = GND, (VDD = 5.0V, VSS = GND) V5, V55, V56, V57, V60, V61, V63, V64 = 2.5V V3, V58 = 0V V46, V59 = 5.0V V52, V53 = 3.2V SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A. Unless otherwise specified, measure the non-reversed outputs for TP39, TP41 and TP43. Item
Y signal block Video maximum gain GV Input SIG5 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP41. Assume the output amplitude at TP41 when SIG2 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of -3dB. Settings 1 and 3 are required. Y/C input, SW8 = C Composite input (NTSC) Composite input (PAL), SW7 = C 13.5 16.5 19.5 dB
Symbol
Conditions
Min. Typ. Max. Unit
FCYYC Y signal frequency Characteristics FCYCMN FCYCMP
5.0 2.5 3.0
MHz MHz MHz
Sharpness characteristics MAX
Assume the output amplitude at TP41 when SIG8 (100kHz) is input to (A) as 0dB. Obtain the output amplitude ratio for the input SIG8 (2.0MHz). GSHPMXC V5 = 4.0V Settings 1 and 3 are required. Composite input Assume the output amplitude at TP41 when SIG8 (100kHz) is input to (A) as 0dB. Obtain the output amplitude ratio for the input SIG8 (2.5MHz). GSHPMXY V5 = 4.0V, SW8 = C Settings 1 and 3 are required. Y/C input Assume the output amplitude at TP41 when SIG8 (100kHz) is input to (A) as 0dB. Obtain the output amplitude ratio for the input SIG8 (2.0MHz). GSHPMNC V5 = 0V Settings 1 and 3 are required. Composite input Assume the output amplitude at TP41 when SIG8 (100kHz) is input to (A) as 0dB. Obtain the output amplitude ratio for the input SIG8 (2.5MHz). GSHPMNY V5 = 0V, SW8 = C Settings 1 and 3 are required. Y/C input
7
12
dB
10
16
dB
-1
2
dB
Sharpness characteristics MIN
1
4
dB
- 13 -
CXA1854AR
Item
Symbol
Conditions
Adjust the output amplitude at TP41 when SIG1 (APL: 50%) is input to (A) to 1.5Vp-p with V61. Assume this as 0 dB, and obtain the TP41 output amplitude ratio when input SIG1 (APL: 90%) is input. V3 = 2.5V, V60 = 3.5V Adjust the output amplitude at TP41 when SIG1 (APL: 50%) is input to (A) to 1.5Vp-p with V61. Assume this as 0dB, and obtain the TP41 output amplitude ratio when input SIG1 (APL: 10%) is input. V3 = 2.5V, V60 = 3.5V Input SIG5 to (A) and obtain the ratio between the TP41 output amplitude when V61 = 2.5V and the TP41 output amplitude when V61 = 5V. Input SIG5 to (A) and obtain the ratio between the TP41 output amplitude when V61 = 2.5V and the TP41 output amplitude when V61 = 1V. Input SIG3 (0dB) to (A) and (B). Adjust the chroma signal phase so that the amplitude (black - white) at TP43 is at a maximum. Using a spectrum analyzer, measure the input and the 3.58MHz or 4.43MHz component, and obtain CRRLK = 150mV x 10 d/20 using their difference d. SW7 = A for NTSC measurement, and C for PAL measurement. Input SIG6 (VL = 150mV) to (A). Measure the delay time from the rising edge of the input signal to the rising edge of the non-reversed output. V5 = 2V Y/C input SW8 = C Composite input (NTSC) Composite input (PAL), SW7 = C
Min. Typ. Max. Unit
AGC characteristics
APL = 90%
GAPL90
-4
-2.5
-1
dB
APL = 10%
GAPL10
1
2.5
4
dB
Contrast characteristics MAX
GCNTMX
2
5
dB
Contrast GCNTMN characteristics MIN
-10
-6
dB
Carrier leak (residual carrier)
CRRLK
30
mVpp
TDYYC Y signal I/O delay time TDYCMN TDYCMP
250 630 610
400 780 760
550 930 910
ns ns ns
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CXA1854AR
Electrical Characteristics - AC Characteristics (2) Item Symbol Conditions Min. Typ. Max. Unit
Chroma signal block
ACC1N ACC amplitude characteristics 1 ACC1P Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB/+6dB/-20dB, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B). Measure the output amplitude at TP51, assuming the output corresponding to 0dB, +6dB and -20dB as V0, V1 and V2, respectively. ACC1 = 20log (V1/V0) ACC2 = 20log (V2/V0) NTSC PAL SW7 = C NTSC PAL SW7 = C NTSC upper limit CL = 20pF NTSC lower limit CL = 20pF PAL upper limit SW7 = C CL = 16pF PAL lower limit SW7 = C CL = 16pF 350 -3 0 +3 dB
-3
0
+3
dB
ACC2N ACC amplitude characteristics 2 ACC2P
-3
0
+3
dB
-3
0
+3
dB
FAPCNU
FAPCND APC pull-in range FAPCPU
FAPCPD Color adjustment characteristics MAX Color adjustment characteristics MIN HUE adjustment range MAX HUE adjustment range MIN
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B), and measure the output amplitude at TP43. Changing the SIG3 burst frequency, mesure the frequency fl which TP43 output changes (the killer mode is canceled). (The crystal parallel floating capacitance is 2pF or less) NTSC: FAPCN = fl - 3579545Hz PAL: FAPCP = fl - 4433619Hz
350
Hz
-350
Hz
Hz
-350
Hz
GCOLMX
GCOLMN
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz burst/chroma phase = 180) to (B). Assume the chroma amplitude when V53 = 3.2V, 5V and 2.1V as V0, V1 and V2, respectively, and calculate GCOLMX = 20log (V1/V0) and GCOLMN = 20log (V2/V0). Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB) to (B). Assume the phase at which the output amplitude at TP43 reaches a minimum when V53 = 3.2V, 5V and 1.6V as 0, 1 and 2, respectively, and calculate TNTMX = 1 - 0 and TNTMN = 2 - 0. Input SIG6 (VL = 0mV) to (A) and SIG3 (level variable, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B), and measure the output amplitude at TP43. Gradually reduce the SIG3 amplitude and measure the level at which the killer operation is activated.
3
5.5
dB
-20
-15
dB
TNTMX
30
deg
TNTMN
-30
deg
ACKN Killer operation input level ACKP
NTSC
-36
-30
dB
PAL SW7 = C
-33
-27
dB
- 15 -
CXA1854AR
Item
Symbol
VRBN
Conditions
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz) to (B) and change the chroma phase. Assume the maximum amplitude at TP39 as VR, the maximum amplitude at TP41 as VG, and the maximum amplitude at TP43 as VB, and calculate VRBN = VR/VB and VGBN = VG/VB. V60 = 3.5V Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz) to (B) and change the chroma phase. Assume the phase at which the maximum amplitude at TP39, TP41 and TP43 as R, G and B, respectively, and calculate RBN = R - B and GBN = G - B. V60 = 3.5V Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz) to (B) and change the chroma phase. Assume the maximum amplitude at TP39 as VR, the maximum amplitude at TP41 as VG, and the maximum amplitude at TP43 as VB, and calculate VRBP = VR/VB and VGBP = VG/VB. V60 = 3.5V, SW7 = C Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz) to (B) and change the chroma phase. Assume the phase at which the maximum amplitude at TP39, TP41 and TP43 as R, G and B, respectively, and calculate RBP = R - B and GBP = G - B. V60 = 3.5 V, SW7 = C
Min. Typ. Max. Unit
0.53 0.63 0.73
Demodulation output amplitude ratio (NTSC)
VGBN
0.25
0.32
0.39
Demodulation output phase difference (NTSC)
RBN
99
109
119
deg
GBN
230
242
254
deg
Demodulation output amplitude ratio (PAL)
VRBP
0.65
0.75
0.85
VGBP
0.33
0.40
0.47
Demodulation output phase difference (PAL)
RBP
80
90
100
deg
GBP
232
244
256
deg
- 16 -
CXA1854AR
Electrical Characteristics - AC Characteristics (3) Item Symbol Conditions Min. Typ. Max. Unit
RGB signal output characteristics
RGB output DC voltage VOUT Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the output (black-black) at TP41 is 9Vp-p and measure the DC voltage at TP39, TP41 and TP43. Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the output (black-black) at TP41 is 9Vp-p, measure the DC voltage at TP39, TP41 and TP43, and obtain the maximum difference between these values. Input SIG6 (VL = 0mV) to (A) and measure the output (black-black) at TP39, TP41 and TP43 when V60 = 0V. Input SIG6 (VL = 0mV) to (A) and measure the output (black-black) at TP39, TP41 and TP43 when V60 = 5V. Input SIG6 (VL = 0mV) to (A) and measure the difference between the outputs (black-black) at TP39 and TP43 and the output (black-black) at TP41 when V55 and V56 = 1V and when V55 and V56 = 4V. Input SIG5 to (A) and measure the difference between the outputs (white-black) at TP39 and TP43 and the output (white-black) at TP41 when V63 and V64 = 1V and when V63 and V64 = 4V. Input SIG5 to (A) and obtain the gain difference between the non-reversed output amplitudes (white-black) and the reversed output amplitudes at TP39, TP41 and TP43. 9.0 5.85 6.05 6.25 V
RGB output DC voltage difference
VOUT
0
100
mV
BRTMX Amount of change in brightness BRTMN
V
3.0
V
Amount of change in sub-brightness
SBBRT
2
4
V
Amount of change in sub-contrast Difference in RGB reversed/ non-reversed gain
SBCNT
2
dB
G (NR)
-0.6
0
0.6
dB
characteristics
G1 gain G2 G3 Input SIG9 to (A) and adjust the non-reversed output amplitude (white-black) at TP41 to 4Vp-p with V61. Calculate the following: G 1 = 20log (VG1/0.0357) G 2 = 20log (VG2/0.0357) G 3 = 20log (VG3/0.0357) (See Fig. 6 for definitions of VG1, VG2 and VG3.) Input SIG4 to (A) and adjust the output amplitude (whiteblack) at TP41 to 4Vp-p with V61 when V57 and V58 = 0V and V59 = 5V. Measure the point where the gain of the non-reversed output at TP41 changes and the voltage difference V 1 between this output and VCC2/2 when V59 = 0V and when V59 = 2.7V. V 1MN when V59 = 0V, and V 1MX when V59 = 2.7V (See Fig. 7.) Input SIG4 to (A) and adjust the output amplitude (whiteblack) at TP41 to 4Vp-p with V61 when V57 and V58 = 0V. Measure the point where the gain of the non-reversed output at TP41 changes and the voltage difference V 2 between this output and VCC2/2 when V58 = 5V and when V58 = 1.5V. V 2MN when V58 = 5V and V 2MX when V58 = 1.5V. (See Fig. 7.) 21.5 9.5 18.5 25.5 12.5 23.5 29.5 15.5 26.5 dB dB dB
V 1MN V 1 adjustment variable range V 1MX
2.0
V
3.5
V
V 2MN V 2 adjustment variable range V 2MX
0.9
V
2.0
V
- 17 -
CXA1854AR
Electrical Characteristics - AC Characteristics (4) Item Symbol Conditions Min. Typ. Max. Unit
Sync separation, TG block
Sync separation input voltage sensitivity Input SIG6 (VL = 0mV, WS = 4.7s, VS variable) to (A) and confirm that it is synchronized with the output at TP30. Gradually reduce the VS of SIG6 from 143mV and obtain the VS at which input and output become non-synchronized. Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7s) to (A) and measure the delay time with the output at TP30. TDHDH is from the falling edge of the input sync signal to the rising edge of TP30, and TDHDL from the rising edge of the input sync signal to the falling edge of TP30. 2.9
VSSEP
40
60
mV
TDHDH HD output delay time TDHDL
3.2
3.5
s
4.4
4.7
5.0
s
HPLLN Horizontal pull-in range HPLLP
Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7s, horizontal frequency variable) to (A) and confirm that NTSC 500 it is synchronized with the output at TP30. Obtain the frequency fH where the input and output are synchronized by changing the horizontal frequency PAL 500 of SIG6 from the non-synchronized condition. SW7 = C HPLLN = fH - 15734, HPLLP = fH - 15625
Hz
Hz
External I/O characteristics
VT1EXT Input SIG6 (VL = 0mV) to (A) and SIG7 (VL variable) to (C), (D) and (E). Raise the amplitude from 0 V and assume the voltage, where the outputs at TP39, TP41 and TP43 go to black level as VT1EXT. Then raise the amplitude further and assume the voltage where these outputs go to white level as VT2EXT. SW9 = B, SW10 = B, SW11 = B Input SIG6 (VL = 0 mV) to (A) and SIG7 (VL = 3 V) to (C), (D) and (E), and adjust the output amplitudes at TP39, TP41 and TP43 to 2.0V with V57. Measure the rise delay time TD1EXTand the fall delay time TD2EXT. SW9 = B, SW10 = B, SW11 = B (See Fig. 2.) Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 1.7V) to (C), (D) and (E), and measure the difference from the black level of the outputs at TP39, TP41 and TP43. SW9 = B, SW10 = B, SW11 = B Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 2.7V) to (C), (D) and (E), and measure the difference from the black level of the outputs at TP39, TP41 and TP43. SW9 = B, SW10 = B, SW11 = B 1.0 1.2 1.4 V
External RGB input threshold voltage
VT2EXT
2.0
2.2
2.4
V
Propagation delay time between external RGB input and output Black level voltage during external RGB input White level voltage during external RGB input
TD1EXT TD2EXT
100 100
200 200
300 300
ns ns
EXTBK
0
V
EXTWT
1.8
2.2
V
- 18 -
CXA1854AR
Electrical Characteristics - AC Characteristics (5) Item Symbol Conditions Min. Typ. Max. Unit
Filter characteristics
F0BPFN BPF center frequency F0BPFP Input SIG6 (VL =0 mV) to (A) and SIG2 (0dB, frequency variable) to (B). Obtain frequencies fc1 and fc2 which reduce the output amplitude by 3dB from the maximum output at TP51 by changing the frequency, and calculate F0BPF = (fc1 + fc2)/2. Settings 1 and 3 are required.
NTSC
3.33
3.58
3.83
MHz
PAL 4.13 SW7 = C -7
4.43
4.73
MHz
Amount of BPF attenuation
ATBPF
Input SIG6 (VL = 0mV) to (A) and SIG2 2.78MHz (0dB, frequency variable) to (B). NTSC Assume TP51 when the center 1.50MHz frequency is input as 0dB and measure the output level at TP51 when the 3.23MHz PAL frequencies noted on the right are SW7 = C 2.00MHz input. Settings 1 and 3 are required. Input SIG2 (0dB, 3.58MHz, 4.43MHz) to (A) and measure the output at TP41 with a spectrum analyzer. Assume the output during Y/C mode (SW8 = A) as 0dB and measure the amount of attenuation during COMP mode (SW8 = C). Settings 1 and 3 are required. NTSC
-3 -23
-1 -15 -1 -15 -35
dB dB dB dB dB
-8
-3 -20
ATRAPN Amount of TRAP attenuation ATRAPP
PAL SW7 = C
-35
dB
R-Y, B-Y and LPF characteristics
DEMLP
Input SIG6 (VL = 0mV) to (A) and SIG2 (amplitude 100mV, frequency variable) to (F) and (G). Assume the output amplitude at TP41 when 100kHz is input as 0dB, and measure the frequency which attenuates the output amplitude by -3dB.
0.6
0.8
1.2
MHz
Digital block I/O characteristics
Output transition time (Note 3 pins) Cross-point time difference tTLH tTHL T Input SIG6 (VL = 0mV) to (A). Load 30pF (See Fig. 4.) V3, V46, V58, V59 = 2.5V Input SIG6 (VL = 0 mV) to (A). Load 30pF (see Fig. 5.) HCK1/HCK2 V3, V46, V58, V59 = 2.5V Input SIG6 (VL = 0mV) to (A). Measure the HCK1 and HCK2 output duty. Load 30pF V3, V46, V58, V59 = 2.5V 30 25 10 ns ns ns
HCK duty
DTYHC
47
50
53
%
- 19 -
CXA1854AR
Description of Electrical Characteristics Measurement Methods
3V
Chroma output
SIG7 GND TP39, 41, 43 non-reversed output 2V 1V
CMAX CMAX - 3dB
BPF center frequency FOBPF = fc1 + fc2 2
TD1EXT
TD2EXT
fc1 fc2 f
Fig. 2. Measuring the delay between external RGB input and output
Fig. 3. BPF center frequency
tTLH
tTHL
T
90% 50%
10% T
Fig. 4. Output transition time measurement condition
Fig. 5. Cross-point time difference measurement condition
White
White peak limiter 1/2 VCC2
White 1/2 VCC2
Non-reversed output
Non-reversed output
G3
V1
V2
G2
Black
G1 Input
Black Input
Fig. 6. characteristics measurement condition
Fig. 7. adjustment variable range
- 20 -
CXA1854AR
Input Waveforms (1) SG No.
APL variable, 5-step waveform
Waveform
APL10%
0.357V
0.143V
SIG1
APL50%
0.179V
0.357V APL90%
Sine wave video signal with burst. (Amplitude and frequency are variable.) 0.15V
SIG2
0.15V 0.143V
VSWEEP
Chroma signal:Burst, chroma frequency (3.579545MHz, 4.433619MHz) Chroma phase and burst frequency variable
SIG3
0.15V 0.143V
Lamp waveform
0.357V
SIG4
0.143V 1H
5-step waveform
0.15V
SIG5
0.143V
- 21 -
CXA1854AR
Input Waveforms (2) SG No. Waveform
VL
SIG6
fH
VS WS
VL amplitude is variable. VS variable: 143mV unless otherwise specified WS variable:4.7s unless otherwise specified fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL) unless otherwise specified
5s 30s
GND
VL
VL amplitude is variable.
SIG7
SYNC timing
0.075V 0.175V
SIG8
Frequency variable 0.143V
10-step waveform
SIG9
0.357V
0.143V
- 22 -
CXA1854AR
Electrical Characteristics Measurement Circuit
+VCC1 +5V
+VCC2 +12V 0.1
TP43
TP41
TP39
+VCC1 +5V
100p
100p
V46
47
100p
1
1
1
47 0.1
330k
330k
1
330k
47
0.1
SW46
A
A
BLKLIM VCC1 REG
A
GND 2 FB B R OUT VCC2 FB R G OUT TEST8 TEST7 TEST6 B OUT FB G RGT VDD
TEST5 32 VD 31 HD 30 HCK1 29 HCK2 28 HST1 27 TEST4 26 CXA1854AR CLR 25 EN 24 VCK1 23 VCK2 22 VST1 21 TEST3 20 SLCK 19 TEST0 18 TEST1 17 S18 S17 10k B SW19 A TP31 TP30 TP29 TP28 TP27 TP26 TP25 TP24 TP23 TP22 TP21 +5V 10k
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
(G) TP51 (F) 4.7k V52 V53
1 1
49 B-YIN 50 R-YIN 51 COUT
SW52 SW53 1 CL
52 HUE/RST 53 COLOR 54 XVXO 55 R-BRT 56 B-BRT 57 RGB-GAIN 58 GAMMA2 59 GAMMA1 60 BRIGHT 61 CONTRAST (B) 62 CIN 63 R-GAIN 64 B-GAIN
V55 V56 V57 V58 V59 V60 V61
SW55 SW56 SW57 SW58 SW59 SW60 SW61
V63 V64
SW63 SW64
AGCADJ
SYNCIN
AGCTC
MODE1
MODE2
EXT-R
EXT-G
CKO
TEST2
PICT
EXT-B
GND1
RPD
YIN
1
2
SW10
SW11
SW9
3 1
4 1
5
6
7
8
9 10 11 12 13 14 15 16 1k L3 30p +12V 2 10k 47k 0.01 VR12 S16
SW7 (A) SW3 V3 SW5 V5 C B AC B
(C) (D) (E) A +5V SW810k 3.3
220p 33k
3300p
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm During NTSC: 3.579545MHz, load capacity: 16pF, CL = 20pF During PAL: 4.433619MHz, load capacity: 16pF, CL = 16pF Measure under the condition that the crystal parallel floating capacitance is within 2pF. 2 Vari-cap diode: 1T369 (SONY) 3 L value: 10H when using the LCX005 4.7H when using the LCX009
- 23 -
VSS
CKI
S19
CXA1854AR
Description of Operation The CXA1854AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing generator (TG) block onto a single chip using BiCMOS technology. This section describes these functions and their mutual relationship. 1) Description of the overall configuration
CXA1854AR Corresponding LCD panels Y SYNC C R-Y B-Y R G B R OUT G OUT B OUT
RGB driver
FRP RGB decoder SYNC BLK HCK1 HCK2 HST1 VCK1 VCK2 VST1 CLR ENB
EXT-R EXT-G EXT-B
TG
LCX009AK/AKB 1.8cm 180K dots
LCX005BK/BKB 1.4cm 113K dots
RPD
3.58MHz or 4.43MHz
VCO
2) Description of RGB decoder block operation * Input mode switching Signal input: Composite input, (MODE2). During composite input: During Y/C input: During Y/color difference input:
Y/C input and Y/color difference input switching is supported by Pin 8
The composite signal is input to Pins 1, 2 and 62. The Y signal is input to Pins 1 and 2, and the C signal to Pin 62. The Y signal is input to Pins 1 and 2, the R-Y signal to Pin 50, and the B-Y signal to Pin 49. (Chroma signal input (delay line output) is also used during PAL, but is switched with the MODE1 setting.) Recommended input signal voltages for each mode are shown in the Pin Description table. The Y signal enters the TRAP circuit in composite mode, but through operation is performed in all other modes. Also, the picture center frequency is set separately for composite input and Y/C input. (See the AC Characteristics tables.)
* NTSC/PAL switching NTSC and PAL (DPAL using an external delay line and SPAL) are switched by MODE1. The built-in TRAP and BPF center frequencies are switched automatically according to the external crystal. The center frequency is stabilized by the APC operation. The R-Y demodulation detective axis is set internally to 90 during SPAL/DPAL. However, optimally adjust the demodulation phase axis with the HUE adjustment pin. * Video AGC/ACC circuit Different AGC characteristics are obtained depending on the APL level of the luminance signal. The gain for the luminance signal is adjusted with the average value. The sync amplitude of the burst signal output is detected and used to adjust the ACC amplifier gain. - 24 -
CKI
CXA1854AR
* VXO, APC detection The VXO local oscillation circuit is crystal oscillation circuit. The phases of the input burst signal and the VXO oscillator output are compared in the APC detection block, and the detective output is used to form a PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. In addition, the filter f0 is automatically adjusted, since the BPF and TRAP center frequency is feedback controlled by VXO. * Crystal oscillator for the XVXO pin connection A 3.579545MHz crystal vibrator is connected to the XVXO pin during NTSC, and a 4.433619MHz crystal vibrator during PAL. (Use KINSEKI CX-5F crystal vibrator with a load capacity of 16pF, frequency deviation within 30ppm, and frequency temperature characteristics within 30ppm.) * External inputs Digital input with two thresholds is optimal for multiplexed character output to screens. When one of the RGB inputs is higher than the lower threshold Vth1, all RGB outputs go to black level. When the higher threshold Vth2 is exceeded, the output for only the signal in question goes to white level, while the other outputs remain at black level. Externally connect a pull-down resistor (10k or more). 3) Description of RGB driver block operation * 2-point compensation circuit In order to support the characteristic of LCD panels, the I/O characteristics are as shown in Fig. 1. The voltage at gain change point A can be changed to that shown in Fig. 2 by adjusting the GAMMA1 pin (Pin 59). Also, the voltage at the 2 gain change point can be changed to that shown in Fig. 3 by adjusting the GAMMA2 pin (Pin 58). The drive for LCD panels can be optimized by adjusting the overall gain with these two gain change points and the RGB-GAIN pin (Pin 57).
Output
Output
1 A
B
A 1
Output
2
2 B
2 1 A B
Input
Input
Input
Fig. 1
Fig. 2
Fig. 3
- 25 -
CXA1854AR
* Sample-and-hold circuit As the LCD panels sample-and-hold RGB signals simultaneously, RGB signal output from CXA1854R must be synchronized to LCD panel drive pulses and sample-and-hold performed. Sample-and-hold is performed by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. These timing pulses are generated by the TG block. Accordingly, RGB signals are each sampled-and-held at the optimal timing and output by the RGB driver block.
Normal scan B S/H S/H HCK SH3 SH1 G S/H S/H SH4 SH2 SH1 SH3 SH4 SH2 SH4 SH3 Reverse scan HCK SH2 SH1
R
S/H
S/H
Example of sample-and-hold circuits and S/H timing * RGB output RGB outputs (Pins 39, 41, and 43) are reversed each horizontal line by the FRP pulse supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage of the output signal matches the reference voltage (VCC2 + GND1)/2. In addition, the white level output is clipped by the Vsig center voltage level, and the black level output is clipped by the limiter operation point that is adjusted at the BLKLIM pin (Pin 46).
Video IN
FRP Black level limiter (reversed side)
RGB OUT waveform
Vsig center voltage
Black level limiter (non-reversed side)
- 26 -
CXA1854AR
4) Description of TG block operation This section describes the main functions of the TG block. (See individual description materials for details.) * PLL circuit block The PLL circuit block contains a phase comparator and frequency division counter circuit in order to accurately align the timing, and performs PLL operation by externally connecting a VCO circuit. The average voltage of the RPD pin (Pin 12) is locked roughly in the center by adjusting it to VDD/2. (See the attached Application Circuit for the external circuit diagram. The 1T369 is recommended as the vari-cap diode used in the VCO circuit.) * SYNC detection circuit This circuit separates the input SYNC signal into HSYNC and VSYNC, and recognizes the EVEN and ODD fields and line numbers, etc. This circuit is necessary for the reasons (1) and (2). (1) Shifts 1.5 dots each horizontal line for the RGB delta arrangement. (2) Field recognition and accurate line number recognition for changing the eliminated lines for each EVEN and ODD field and smoothing the picture during PAL. In addition, if the SYNC waveform is not detected for more than a certain interval, the unit shifts automatically to the free running state and the LCD panel is driven by self oscillation. * Pulse generator block The pulse generator circuit is synchronized to the previously mentioned SYNC detection circuit and PLL circuit, and generates the pulses necessary to drive the LCD panel. (The main output pulse timings are shown for each mode in a later section.) At the same time, the pulse generator circuit also generates the BGP, BLK and other waveforms for the RGB decoder. Therefore, TG block PLL circuit operation is necessary for RGB decoder functions. * AC drive during no signal HST1, HCK1, HCK2, FRP, VST1, VCK1, VCK2, HD and VD are made to run free so that the LCD panel is AC driven even when there is no composite sync from the SYNC pin. During this time, the HSYNC separation circuit stops and the PLL counter is made to run free. In addition, the reference pulse for generates VD and VST, and the auxiliary V counter creates the reference pulse for generates VD and VST. The VSYNC separation circuit is also stopped and The period of the V counter is designed to be 269H for NTSC and 321H for PAL. When there is no VSYNC during 269H or 321H, the free running state is assumed. In addition, RPD is kept at high impedance in order to prevent the AFC circuit from producing a phase error due to phase comparison when there is no signal. * AFC circuit (702/1050fh generation) A fully synchronized AFC circuit is built in. PLL error signal is generated at the following timing. The phase comparison output of the entire bottom of SYNC and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter, and then it changes the vari-cap diode capacitance and the oscillation frequency is stabilized at 702fh in the LCX005BK/BKB and 1050fh in the LCX009AK/AKB.
SYNC 4.7s VDD RPD VDD/2 0V SYNC center
- 27 -
CXA1854AR
5) Description of TG block mode settings * SLCK: Selects the driven LCD panel. L H Selects the LCX009 Selects the LCX005
Note) The VCO frequency varies depending on the used panel. VCO center frequency LCX005 (702fh) NTSC PAL 11.06MHz 10.97MHz
LCX009 (1050fh) NTSC PAL 16.52MHz 16.41MHz
The external VCO circuit diagram is shown in the Application Circuit. Recommended value: L value LCX005: 10H, LCX009: 4.7H
* RGT: Switches the horizontal scan direction. H L Normal scan mode Reverse scan mode
The HST1, HCK1 and HCK2 timing are switched by the RGT selection. The timing of the internal sample-and-hold pulse is also switched at the same time. Connect the panel RGT pin directly, as it does not support output.
* MODE1/MODE2: Sets the type of video signal input. MODE1 H M L NTSC D-PAL SPAL MODE2 H M L Composite input Y/color difference input Y/C input
Signal input connections for each mode are noted in the RGB decoder block.
- 28 -
CXA1854AR
LCX009AK/AKB and LCX005BK/BKB Color Coding Diagram The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note that the shaded region within the diagram is not displayed. LCX009AK/AKB pixel arrangement
dummy1 to 4 HSW1 HSW2 HSW267 HSW268 dummy5 to 8
dummy1 dummy2 Vline1 Vline2 Vline3 R R R
B G B G B G B R B G
R B R B R B R B R G B R G B 14
G R G R G R G R G R G R
B G B G B G B G B G B G
R B R B R B R B R B R B
G R G R G R G R G R G R
B G B G B
R B R B R
G R G R G
B G B G B
R B R B R B R G B R G B R G B
G R G R G R G R G R G R
B
RGBR Photo-shielding area GBRG R G B R G B R G B R G B R G B G R 13 G R B G G R B G R G R B G R G R B G R B G R R
2
B
B
BRG G Display area B G B G B G R B R B G R R B G R B G R B B
B
225 228
B
Vline224 Vline225 dummy3
R B R
B
1
800 827
LCX005BK/BKB pixel arrangement
dummy1 HSW1 HSW2 HSW3 HSW174 HSW175 dummy2 to 5
dummy1 dummy2 Vline1 Vline2 Vline3 R B R Vline217 Vline218 dummy3 dummy4 R 3 R B G B G R B G R B G R R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B R B G R G R B G B G R B G B R G B G R R B G B G R B G R B G R B G R B G R B G G R B G B G
Photo-shielding area RGBR B R B R B R B R B R G G R B G R B G R 13 G R B G R B G R B G R B R B G R B G R B B
2
GBR Display area B G R R B G
218 222
2
521 537
- 29 -
CXA1854AR
Application Circuit - NTSC (COMP and Y/C input)
+VCC1 +5V +VCC2 +12V 0.1 47 1 B-LIM 47k 0.01 1 1 47 0.1 To panel Blue Green Red +VDD +5V
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
330k
330k
47
330k
0.1 1
BLKLIM
FB R
G OUT
TEST8
TEST7
GND 2
TEST6
VCC1
B OUT
FB G
REG
FB B
RGT
R OUT
VCC2
VDD
TEST5 32 VD 31 HD 30 HCK1 29 HCK2 28 HST1 27 TEST4 26 To panel
49 B-YIN 50 R-YIN 1.7k 47k HUE COLOR 47k 47k 47k 47k 47k 47k 47k 47k 0.01 1 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 20pF 51 COUT 52 HUE/RST 53 COLOR 54 XVXO 55 R-BRT 56 B-BRT 57 RGB-GAIN 58 GAMMA2 59 GAMMA1 60 BRIGHT 61 CONTRAST 62 CIN 47k R-G B-G AGC PIC 47k 47k 47k 0.01 0.01 0.01 0.01 63 R-GAIN 64 B-GAIN CXA1854AR
R-BRT B-BRT RGB GAM2 GAM1 BRT CONT
CLR 25 EN 24 VCK1 23 VCK2 22 VST1 21 TEST3 20 SLCK 19 TEST0 18 TEST1 17
+VDD +5V 005 009
SYNCIN
AGCADJ
MODE1
MODE2
AGCTC
EXT-R
EXT-G
YIN
1
2
3 1
4 1
5
6
7
8
9 10 11 12 13 14 15 16
VSS
CKI
Y/C
COMP
10k
10k
10k
1k
+VDD +5V C IN COMP/Y IN 10k Y/C COMP 3.3
220p 33k 2
CKO
L3
30p +VCC2 +12V
3300p
10k 0.01
TEST2
47k
PICT
EXT-B
GND1
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm 3.579545MHz, load capacity: 16pF 2 Vari-cap diode: 1T369 (SONY) 3 L value: 10H when using the LCX005 4.7H when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 30 -
RPD
CXA1854AR
Application Circuit - PAL (COMP and Y/C input)
To panel +VCC1 +5V +VCC2 +12V 0.1 Blue Green Red +VDD +5V
47 1 B-LIM 47k 0.01 1 1 47 0.1
330k
330k
1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
330k
47
0.1
TEST8
TEST7
B OUT
FB G
REG
GND 2
FB B
R OUT
VCC2
BLKLIM
FB R
G OUT
TEST6
VCC1
RGT
VDD
TEST5 32 VD 31 HD 30 HCK1 29 HCK2 28 HST1 27 TEST4 26
49 B-YIN 50 R-YIN 1.7k HUE COLOR 47k 47k R-BRT B-BRT RGB GAM2 GAM1 BRT CONT 47k 47k 47k 47k 47k 47k 0.01 1 0.01 0.01 0.01 0.01 0.01 0.01 0.01 47k 0.01 16pF 51 COUT 52 HUE/RST 53 COLOR 54 XVXO 55 R-BRT 56 B-BRT 57 RGB-GAIN 58 GAMMA2 59 GAMMA1 60 BRIGHT 61 CONTRAST 62 CIN 47k R-G B-G AGC PIC 47k 47k 47k 0.01 0.01 0.01 0.01 63 R-GAIN 64 B-GAIN CXA1854AR
CLR 25 EN 24 VCK1 23 VCK2 22 VST1 21 TEST3 20 SLCK 19 TEST0 18 TEST1 17
To panel
+VDD +5V 005 009
SYNCIN
AGCADJ
MODE1
MODE2
AGCTC
EXT-R
EXT-G
EXT-B
GND1
RPD
YIN
1
2
3 1
4 1
5
6
7
8
9 10 11 12 13 14 15 16
VSS
CKI
Y/C
COMP
10k
10k
10k
1k
+VDD +5V C IN COMP/Y IN 10k Y/C COMP 3.3
220p 33k 2
CKO
L3
30p +VCC2 +12V
3300p
10k 47k 0.01
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm 4.433619MHz, load capacity: 16pF 2 Vari-cap diode: 1T369 (SONY) 3 L value: 10H when using the LCX005 4.7H when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 31 -
TEST2
PICT
CXA1854AR
Application Circuit - Y/color difference input (NTSC/PAL)
+VCC1 +5V
+VCC2 +12V 0.1
To panel Blue Green Red
+VDD +5V
47 1 B-LIM 1 47k 0.01 1 1 47 0.1
R-YIN B-YIN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
330k
330k
330k
47
0.1
G OUT
TEST8
TEST7
GND 2
TEST6
VCC1
B OUT
FB G
REG
FB B
R OUT
VCC2
1 49 B-YIN 50 R-YIN 1 1.7k HUE COLOR 47k R-BRT B-BRT RGB GAM2 GAM1 BRT CONT 47k 47k 47k 47k 47k 47k 47k 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 47k 0.01 51 COUT 52 HUE/RST 53 COLOR 54 XVXO 55 R-BRT 56 B-BRT 57 RGB-GAIN 58 GAMMA2 59 GAMMA1 60 BRIGHT 61 CONTRAST 62 CIN 63 R-GAIN 64 B-GAIN CXA1854AR TEST5 32 VD 31 HD 30 HCK1 29 HCK2 28 HST1 27 TEST4 26 CLR 25 EN 24 VCK1 23 VCK2 22 VST1 21 TEST3 20 SLCK 19 TEST0 18 TEST1 17 +VDD +5V 005 009 To panel
R-G B-G AGC PIC
47k 47k 47k 47k
0.01 0.01 0.01 0.01
SYNCIN
AGCADJ
BLKLIM
MODE1
MODE2
AGCTC
FB R
RGT CKO
1
EXT-R
EXT-G
GND1
RPD
YIN
1
2
3 1
4 1
5
6
7
8
9 10 11 12 13 14 15 16
VSS
CKI
10k
10k
10k
1k
L2
+VDD +5V Y IN 10k PAL NTSC 3.3
220p 33k
30p +VCC2 +12V
3300p
10k 0.01
TEST2
47k
1 Vari-cap diode: 1T369 (SONY) 2 L value: 10H when using the LCX005 4.7H when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
PICT
- 32 -
EXT-B
VDD
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: H (Normal scan) Composite In 683 702 693 1 11 21 31 41 51 61 71 81 91
653
663
673
CLK
SYNC 4.7s (52fh) 2.0s (22fh) 4.5s (50fh) 23.5fh
4.7s (52fh)
(BLK)
HD
HST
13fh
HCK1
- 33 -
EVEN FIELD 3.0s (33fh) ODD LINE
HCK2
FRP (Internal pulse)
ODD FIELD
18.5fh
VCK1
VCK2 0.5s (6fh)
CLR
EN (PAL)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
CXA1854AR
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: H (Normal scan) Composite In 683 702 693 1 11 21 31 41 51 61 71 81 91
653
663
673
CLK
SYNC 4.7s (52fh) 2.0s (22fh) 4.5s (50fh) 22fh
4.7s (52fh)
(BLK)
HD
HST
13fh
HCK1
- 34 -
ODD FIELD 3.0s (33fh) EVEN LINE
HCK2
FRP (Internal pulse)
EVEN FIELD
VCK1
18.0fh
VCK2 0.5s (6fh)
CLR
EN (PAL)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
CXA1854AR
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: L (Reverse scan) Composite In 683 702 693 1 11 21 31 41 51 61 71 81 91
653
663
673
CLK
SYNC 4.7s (52fh) 2.0s (22fh) 4.5s (50fh) 23fh
4.7s (52fh)
(BLK)
HD
HST
13fh
HCK1
- 35 -
ODD FIELD EVEN FIELD 3.0s (34fh) ODD LINE
HCK2
FRP (Internal pulse)
18.0fh
VCK1
VCK2 0.5s (5fh)
CLR
EN (PAL)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
CXA1854AR
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: L (Reverse scan) Composite In 683 702 693 1 11 21 31 41 51 61 71 81 91
653
663
673
CLK
SYNC 4.7s (52fh) 2.0s (22fh) 4.5s (50fh) 24.5fh
4.7s (52fh)
(BLK)
HD
HST
13fh
HCK1
- 36 -
ODD FIELD EVEN FIELD 3.0s (34fh) EVEN LINE
HCK2
FRP (Internal pulse)
VCK1
18.5fh
VCK2 0.5s (5fh)
CLR
EN (PAL)
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
CXA1854AR
LCX005 Vertical Direction Timing Chart (NTSC)
HD 3.0H 3.0H 1 13 20H Display start 11.5H
1 23 4 12 34 56 78 12 3 4 1 2 3 45 67 8
(VD) 3.0H 263 275
3.0H
3.0H 20 243
3.0H
SYNC
505
20H
(BLK) 12H Display start
VST
VCK1
VCK2
FRP (Internal pulse)
- 37 -
ODD FIELD
HST
EN
CLR
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
VD
VRST (Internal pulse)
EVEN FIELD
CXA1854AR
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
LCX005 Vertical Direction Timing Chart (PAL)
6, 8 decimation
HD 2.5H 2.5H 1 16 25H Display start
1 2 34 1 2 3 4 56 78 1 2 3 4 56 1 2 3 4 5 6 7 8 1 2 3 4 5 6 78
(VD) 2.5H 314
2.5H
2.5H 26 288
2.5H
SYNC 328 Display start 14H
1 23 4 1 2 3 45 6 7 8 1 2 3 4 5 6 1 2 3
600
25H
(BLK) 14.5H
VST
VCK1
VCK2
1 2 3456 78
FRP (Internal pulse)
- 38 -
ODD FIELD
HST
EN
CLR
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
VD
VRST (Internal pulse)
EVEN FIELD
CXA1854AR
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: H (Normal scan) Composite In 1011 1050 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
971
981
991
1001
CLK
SYNC 4.7s (78fh) 2.0s (33fh) 4.5s (73fh)
4.7s (78fh)
(BLK)
HD
20.5fh 12fh
HST
HCK1
- 39 -
ODD FIELD EVEN FIELD 3.0s (50fh) ODD LINE
HCK2
FRP (Internal pulse)
VCK1
43.5fh
VCK2 0.5s (8fh)
CLR
EN (PAL)
CXA1854AR
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: H (Normal scan) Composite In 1011 1050 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
971
981
991
1001
CLK
SYNC 4.7s (78fh) 2.0s (33fh) 4.5s (73fh)
4.7s (78fh)
(BLK)
HD
19fh 12fh
HST
HCK1
- 40 -
EVEN FIELD ODD FIELD 3.0s (50fh) EVEN LINE
HCK2
FRP (Internal pulse)
43.0fh
VCK1
VCK2 0.5s (8fh)
CLR
EN (PAL)
CXA1854AR
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: L (Reverse scan) Composite In 1011 1050 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
971
981
991
1001
CLK
SYNC 4.7s (78fh) 2.0s (33fh) 4.5s (73fh)
4.7s (78fh)
(BLK)
HD
20fh 12fh
HST
HCK1
- 41 -
ODD FIELD EVEN FIELD 3.0s (51fh) ODD LINE
HCK2
FRP (Internal pulse)
VCK1
43.0fh
VCK2 0.5s (7fh)
CLR
EN (PAL)
CXA1854AR
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
RGT: L (Reverse scan) Composite In 1011 1050 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
971
981
991
1001
CLK
SYNC 4.7s (78fh) 2.0s (33fh) 4.5s (73fh)
4.7s (78fh)
(BLK)
HD
21.5fh 12fh
HST
HCK1
- 42 -
ODD FIELD EVEN FIELD 3.0s (51fh) EVEN LINE
HCK2
FRP (Internal pulse)
43.0fh
VCK1
VCK2 0.5s (7fh)
CLR
EN (PAL)
CXA1854AR
Note) During Y/C input, the HST timing is delayed 6fh from the above timing. The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified.
LCX009 Vertical Direction Timing Chart (NTSC)
HD 3.0H 3.0H 1 20H 272 Display start
12 3 4 12 34 56 78
(VD) 3.0H 263
3.0H
3.0H 10 Display start 8.5H
1 2 34 1 23 45 67 8
3.0H 20 243
SYNC
505
20H
(BLK) 9H
VST
VCK1
VCK2
FRP (Internal pulse)
HST
- 43 -
ODD FIELD
EN
CLR
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
VD
VRST (Internal pulse)
EVEN FIELD
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins. CXA1854AR
LCX009 Vertical Direction Timing Chart (PAL)
6, 8 decimation
HD 2.5H 2.5H 1 26 25H 314 324 Display start
12 34 1 23 456 78 1 2 3 4 5 6 7 8 1 2 34 5 6 12 3
(VD) 2.5H
2.5H
2.5H 12 288 Display start
1 23 4 1 2 3 4 5 6 7 8 1 2 34 56 12 34 5 6 7 81
2.5H
SYNC
600
25H
(BLK) 10.5H 5.5H 10.0H 6.0H
VST
VCK1
1 2 3 45 6 7 8
VCK2
FRP (Internal pulse)
HST
- 44 -
ODD FIELD
EN
CLR
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
VD
VRST (Internal pulse)
EVEN FIELD
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins. CXA1854AR
CXA1854AR
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 10.0 0.2 48 49 33 32 0.15 0.05 0.1
A 64 17
1 1.25 0.5
16 + 0.08 0.18 - 0.03
1.7 MAX 0.1 M
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
(0.5)
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
LQFP-64P-L061 LQFP064-P-1010-AY
- 45 -

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