View DS1215_120818.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS1215
DS1215 Phantom Time Chip
FEATURES
PIN ASSIGNMENT
X1 X2 WE BAT1 GND D Q GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCCI VCCO BAT2 RST OE CEI CEO ROM/RAM
* Keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years
* Adjusts for months with fewer than 31 days * Leap year automatically corrected up to 2100 * No address space required * Provides
nonvolatile controller functions for battery backup of RAM redundant batteries for high-reliability applications
16-PIN DIP (300 MIL) X1 X2 WE BAT1 GND D Q GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCCI VCCO BAT2 RST OE CEI CEO ROM/RAM
* Supports
* Uses a 32.768 KHz watch crystal * Full 10% operating range * Operating temperature range 0C to 70C * Space-saving, 16-pin DIP package and SOIC * Optional industrial temperature range -40C to +85C
(IND)
16-PIN SOIC (300 MIL)
PIN DESCRIPTION
X1, X2 - 32.768 KHz Crystal Connections WE - Write Enable BAT1 - Battery 1 Input GND - Ground D - Data In Q - Data Out - ROM/RAM Select ROM/RAM - Chip Enable Out CEO CEI - Chip Enable Input - Output Enable OE RST - Reset BAT2 - Battery 2 Input - Switched Supply Output VCCO - +5 VDC Input VCCI NOTE: Both pins 5 and 8 must be grounded.
DESCRIPTION
The DS1215 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory controller. In the absence of power, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including correction for leap year every four years. The watch operates in one of two formats: a 12-hour mode with an AM/PM indicator or a 24-hour mode. The nonvolatile controller supplies all the necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The DS1215 can be interfaced with either RAM or ROM without leaving gaps in memory.
ORDERING INFORMATION
DS1215 DS1215S DS1215N DS1215SN 16-pin DIP 16-pin SOIC 16-pin DIP (IND) 16-pin SOIC (IND)
ECopyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.
032697 1/15
DS1215
OPERATION
The block diagram of Figure 1 illustrates the main elements of the Time Chip. Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO). After recognition is established, the next 64 read or write cycles either extract or update data in the Time Chip and
CEO remains high during this time, disabling the connected memory. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input (CEI), output enable (OE), and write enable (WE). Initially, a read cycle using the CEI and OE control of the Time Chip starts the pattern recognition sequence by moving a pointer to the first bit of the 64 bit comparison register. Next, 64 consecutive write cycles are executed using the CEI and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
TIMING BLOCK DIAGRAM Figure 1
X1 32.768 kHz ROM/RAM CEO UPDATE READ CEI OE WE RST CONTROL LOGIC WRITE TIMEKEEPING REGISTER POWER-FAIL X2 CLOCK/CALENDAR LOGIC
ACCESS ENABLE SEQUENCE DETECTOR
COMPARISON REGISTER
D Q I/O BUFFERS
DATA INTERNAL VCC
VCCI
POWER-FAIL DETECT LOGIC
VCCO
BAT1
BAT2
032697 2/15
DS1215
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched. (This bit pattern is shown in Figure 2.) With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the timekeeping registers may proceed. The next
64 cycles will cause the Time Chip to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the Time Chip. A 32,768 Hz quartz crystal can be directly connected to the DS1215 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real Time Clocks".
TIME CHIP COMPARISON REGISTER DEFINITION Figure 2
7 BYTE 0 1 6 1 5 0 4 0 3 0 2 1 1 0 0 1 HEX VALUE C5
BYTE 1
0
0
1
1
1
0
1
0
3A
BYTE 2
1
0
1
0
0
0
1
1
A3
BYTE 3
0
1
0
1
1
1
0
0
5C
BYTE 4
1
1
0
0
0
1
0
1
C5
BYTE 5
0
0
1
1
1
0
1
0
3A
BYTE 6
1
0
1
0
0
0
1
1
A3
BYTE 7
0
1
0
1
1
1
0
0
5C
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Time Chip are less than 1 in 1019.
032697 3/15
DS1215
NONVOLATILE CONTROLLER OPERATION
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the ROM/RAM select pin. When ROM/RAM is connected to ground, the controller is set in the RAM mode and performs the circuit functions required to make static CMOS RAM and the timekeeping function nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS SRAM. The DS1215 also performs redundant battery control for high reliability. On power-fail, the battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the system, the unused battery input should be connected to ground. The DS1215 safeguards the Time Chip and RAM data by power-fail detection and write protection. Power-fail detection occurs when VCCI falls below VTP, which is equal to 1.26 x VBAT. The DS1215 constantly monitors the VCCI supply pin. When VCCI is less than VTP, a comparator outputs a power-fail signal to the control logic. The power-fail signal forces the chip enable output (CEO) to VCCI or VBAT-0.2 volts for external RAM write protection. During nominal supply conditions, CEO will track CEI with a maximum propagation delay of 20 ns. Internally, the DS1215 aborts any data transfer in progress without changing any of the Time Chip registers and prevents future access until VCCI exceeds VTP. A typical RAM/Time Chip interface is illustrated in Figure 3. When the ROM/RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a read- only device that retains data in the absence of power, battery backup and write protection is not required. As a result, the chip enable logic will force CEO low when power fails. However, the Time Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. In addition, the chip enable output is set at a low level on power-fail as VCCI falls below the level of VBAT. A typical ROM/Time Chip interface is illustrated in Figure 4.
TIME CHIP REGISTER INFORMATION
Time Chip information is contained in 8 registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 5. Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all 8 registers, starting with bit 0 of register 0 and ending with bit 7 of register 7.
AM-PM/12/24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 -23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin (Pin 13). When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic 0, the oscillator turns on and the watch becomes operational.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.
032697 4/15
DS1215
RAM/TIME CHIP INTERFACE Figure 3
CMOS STATIC RAM A0 - AN ADD DATA I/O WE D0 - D7
OE CE VCC
DS1215 10 12 3 WE CE RST 11 13 4 + BAT1 CEI RST BAT1 X1 1 Q VCCI ROM/ RAM BAT2 X2 2 9 14 + BAT2 OR TIE TO GND FOR ONE-BATTERY OPERATION +5 VDC CEO OE VCCO D 15 6 7
32.768 KHz
ROM/TIME CHIP INTERFACE Figure 4
ROM A0 - AN ADD VCC DATA I/O A2 D0 - D7
OE
OE A0 CE
DS1215 6 12 3 WE CE RST 11 13 4 + BAT1 CEI RST BAT1 X1 1 VCCI VCCO ROM/ RAM BAT2 X2 2 15 9 14 + BAT2 OR TIE TO GND ONE-BATTERY OPERATION FOR D OE CEO Q 10 7 16 +5 VDC
32.768 KHz
032697 5/15
DS1215
TIME CHIP REGISTER DEFINITION Figure 5
REGISTER 7 0 6 0.1 SEC 5 4 3 2 1 0.01 SEC 0 00-99 RANGE (BCD)
1
0
10 SEC
SECONDS
00-59
2
0
10 MIN
MINUTES
00-59
3
12/24
0
10 A/P
HR
HOUR
01-12 00-23
4
0
0
OSC
RST
0
DAY
01-07
5
0
0
10 DATE
DATE
01-31
6
0
0
0
10 MONTH
MONTH
01-12
7
10 YEAR
YEAR
00-99
032697 6/15
DS1215
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Logic 1 Logic 0 VBAT1 or VBAT2 Battery Voltage SYMBOL VCC VIH VIL VBAT MIN 4.5 2.2 -0.3 2.5 TYP 5.0 MAX 5.5 VCC+0.3 +0.8 3.7 V V UNITS V
(0C to 70C)
NOTES 1 1 1 7
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Current Supply Current VCCO = VCCI-0.3 Input Leakage Output Leakage Output @ 2.4V Output @ 0.4V SYMBOL ICCI ICCO1 IIL ILO IOH IOL -1.0 -1.0 -1.0 MIN TYP
(0C to 70C; VCC = 4.5 to 5.5V)
MAX 5 80 +1.0 +1.0 UNITS mA mA A A mA 4.0 mA 2 2 NOTES 6 8 11
DC ELECTRICAL CHARACTERISTICS
PARAMETER CEO Output VBAT1 or VBAT2 Battery Current Battery Backup Current @ VCCO = VBAT-0.2V SYMBOL VOH1 IBAT ICCO2 MIN VCCI or VBAT-0.2 1 10 TYP
(0C to 70C; VCC < 4.5V)
MAX UNITS V A A NOTES 9 6 10
032697 7/15
DS1215
AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND
PARAMETER Read Cycle Time CEI Access Time OE Access Time CEI to Output Low Z OE to Output Low Z CEI to Output High Z OE to Output High Z Read Recovery Write Cycle Write Pulse Width Write Recovery Data Setup Data Hold Time CEI Pulse Width RST Pulse Width CEI Propagation Delay CEI High to Power-Fail SYMBOL tRC tCO tOE tCOE tOEE tOD tODO tRR tWC tWP tWR tDS tDH tCW tRST tPD tPF 20 120 100 20 40 10 100 200 5 10 10 10 MIN 120 TYP
(0C to 70C; VCC = 4.5 to 5.5V)
MAX UNITS ns 100 100 ns ns ns ns 40 40 ns ns ns ns ns ns ns ns ns ns 20 0 ns ns 2, 3 4 5 5 NOTES
AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND
PARAMETER Recovery at Power-Up VCC Slew Rate 4.5 - 3.0V SYMBOL tREC tF 0 MIN TYP 2
(0C to 70C; VCC > 4.5V)
MAX UNITS ms ms NOTES
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 5 5 MAX 10 10 UNITS pF pF
(tA = 25C)
NOTES
032697 8/15
DS1215
AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO
PARAMETER Read Cycle Time CEI Access Time OE Access Time CEI to Output in Low Z OE to Output in Low Z CEI to Output in High Z OE to Output in High Z Address Setup Time Address Hold Time Read Recovery Write Cycle Time CEI Pulse Width OE Pulse Width Write Recovery Data Setup Time Data Hold Time RST Pulse Width CEI Propagation Delay CEI High to Power Fail SYMBOL tRC tCO tOE tCOE tOEE tOD tODO tAS tAH tRR tWC tCW tOW tWR tDS tDH tRST tPD tPF 20 120 100 100 20 40 10 200 5 10 20 10 10 MIN 120 TYP
(0C to 70C; VCC = 5V 10%)
MAX UNITS ns 100 100 ns ns ns ns 40 40 ns ns ns 10 ns ns ns ns ns ns ns ns ns 20 0 ns ns 2, 3 4 5 5 NOTES
AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO
PARAMETER Recovery at Power-Up VCC Slew Rate 4.5 - 3.0V SYMBOL tREC tF 0 MIN TYP 2
(0C to 70C; VCC < 4.5V)
MAX UNITS ms ms NOTES
032697 9/15
DS1215
TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND
WE = VIH tRC CEI tCO tRR
tOD OE tOE
tOEE tCOE OUTPUT DATA VALID
tODO
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND
OE = VIH tWC WE tWP tWR
tWR CEI tCW
tDS D
tDH tDH
DATA IN STABLE
032697 10/15
EEEEEEE EEEEEEE
EEE EEE
EEE EEE
Q
EEEEE EEEEE
DS1215
TIMING DIAGRAM: READ CYCLE ROM/RAM = VCCO
tRC
CEI
OE
WE
Q
TIMING DIAGRAM: WRITE CYCLE ROM/RAM = VCCO
tWC tCW tWR
CEI
OE
WE
D
EEEEE EEEEE CCCCCCC CCCCCCC CCCCCCC CCCCCC CCCCCC CCCCCC
tAS tAS
tCO
tRR
tOD tRR tRC tOE tODO tAH tAH
tOEE
tCOE OUTPUT DATA VALID
CCCCC CCCCC CCCCC CCCCCCC CCCCCCC CCCCCC CCCCCC
tAS tAS
tWR tWC tOW
tAH tAH
tDS tDS DATA IN STABLE tDH
tDH
032697 11/15
DS1215
TIMING DIAGRAM: POWER DOWN
tCE CEI
VIH VIL tPD tCE
ROM/RAM = GND
CEO VIH VIL
ROM/RAM = VCCO
CEO
VCCI 4.5V tF 3V
TIMING DIAGRAM: POWER UP
VIH VIL
CEI
BAT - 0.2V
ROM/RAM = GND
CEO VIL tREC tPD
ROM/RAM = VCCO
CEO 4.5V
VCCI
TIMING DIAGRAM: RESET FOR TIME CHIP
RST
tRST
032697 12/15
CCCCCCCCCC CCCCCCCCCC CCCCCCCCCC
tPF VBAT - 0.2V
CCCCCC CCCCCC
DS1215
NOTES:
1. All voltages are referenced to ground. 2. Measured with load shown in Figure 6. 3. Input pulse rise and fall times equal 10 ns. 4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 6. Measured without RAM connected. 7. Trip point voltage for power-fail detect. VTP = 1.26 x VBAT. For 10% VCC= 5V + 10% operation VBAT = 3.5V max.; for 5% operation VBAT = 3.7V max. 8. ICC01 is the maximum average load current the DS1215 can supply to memory. 9. Applies to CEO with the ROM/RAM pin grounded. When the ROM/RAM pin is connected to VCCO, CEO will go to a low level as VCCI falls below VBAT. 10. ICC02 is the maximum average load current that the DS1215 can supply to memory in the battery backup mode. 11. Applies to all input pins except RST. RST is pulled internally to VCCI.
OUTPUT LOAD Figure 6
+5V
1.1K
50 pF 680
032697 13/15
DS1215
DS1215 TIME CHIP
B
D
J
H 1
A
PKG C DIM A IN. MM F K G E B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM
16-PIN MIN 0.740 0.240 0.120 0.300 0.015 0.110 0.090 0.300 0.008 0.015 MAX 0.780 0.260 0.140 0.325 0.040 0.140 0.110 0.370 0.012 0.021
032697 14/15
DS1215
DS1215S SERIAL TIMEKEEPER 16-PIN SOIC
K G
B
H
1
A C E phi J F L
PKG DIM A IN. MM B IN. MM C IN. MM E IN. MM F IN. MM G IN. MM H IN MM J IN MM K IN. MM L IN MM PHI
16-PIN MIN 0.402 10.21 0.290 7.37 0.089 2.26 0.004 0.102 0.094 2.38 MAX 0.412 10.46 0.300 7.65 0.095 2.41 0.012 0.30 0.105 2.68
0.050 BSC 1.27 BSC 0.398 10.11 0.009 0.229 0.013 0.33 0.016 0.40 0 0.416 10.57 0.013 0.33 0.019 0.48 0.040 1.02 8
032697 15/15

▲Up To Search▲

Price & Availability of DS1215

	To Download DS1215 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .