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| PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F160S5NS-L70 16M (2MB x 8/1MB x 16) (Model No.: LHF16KA4) Flash Memory Spec No.: EL128040 Issue Date: August 22, 2000 SHARP .LHF16KA4 l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). ' aOffice electronics l instrumentation and measuring equipment l Machine tools *Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers *Traffic control systems aGas leak detectors and automatic cutoff devices *Rescue and security equipment l Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment l Communications equipment for trunk lines *Control equipment for the nuclear power industry aMedical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. l Please direct all queries regarding the products covered herein to a sales representative of the company. Rev.1.9 SHAl?P .-- - LHFlGKA4 1 CONTENTS PAGE 1 INTRODUCTION ...................................................... 1 .l Product Overview ................................................ 2 PRINCIPLES OF OPERATION ................................ 2.1 Data Protection ................................................... 3 BUS OPERATION.. .................................................. 3.1 Read ................................................................... 3.2 Output Disable .................................................... 3.3 3.4 3.5 3.6 Standby ............................................................... Deep Power-Down .............................................. Read identifier Codes Operation.. ....................... Query Operation .................................................. 3 3 6 7 7 7 7 7 7 8 8 8 8 11 11 11 11 12 12 PAGE 5 DESIGN CONSIDERATIONS ................................ .30 5.1 Three-Line Output Control ................................ .30 5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Polling.. ............................................................. .30 5.3 Power Supply Decoupling.. ............................... .30 5.4 V,, Trace on Printed Circuit Boards.. ............... .30 5.5 V,,, V,,, RP# Transitions.. .............................. .31 5.6 Power-Up/Down Protection.. ............................. .31 5.7 Power Dissipation ............................................. .31 6 ELECTRICAL SPECIFICATIONS.. ........................ 6.1 Absolute Maximum Ratings .............................. 6.2 Operating Conditions ........................................ 6.2.1 Capacitance ................................................ .32 .32 .32 3.7 Write.. .................................................................. 4 COMMAND DEFINITIONS ....................................... 4.1 Read Array Command.. ..................................... 4.2 Read Identifier Codes Command.. .................... 4.3 Read Status Register Command.. ..................... 4.4 Clear Status Register Command.. ..................... 4.5 Query Command ............................................... 4.5.1 Block Status Register .................................. .32 6.2.2 AC Input/Output Test Conditions.. ............... .33 6.2.3 DC Characteristics.. ..................................... .34 6.2.4 AC Characteristics - Read-Only Operations .36 AC Characteristics - Write Operations.. ....... .39 Alternative CE#-Controlled Writes.. ............. .41 Reset Operations ........................................ .43 Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Performance.. ........................ .44 45 45 6.2.5 6.2.6 6.2.7 6.2.8 4.5.2 CFI Query Identification String.. ................... 13 4.5.3 System Interface Information.. ..................... 13 4.5.4 Device Geometry Definition ......................... 14 4.5.5 SCS OEM Specific Extended Query Table . . 14 4.6 Block Erase Command.. .................................... 15 4.7 Full Chip Erase Command ................................ 15 4.8 Word/Byte Write Command.. ............................. 4.9 Multi Word/Byte Write Command.. .................... 4.10 Block Erase Suspend Command.. ................... 16 16 17 7 ADDITIONAL INFORMATION ................................ 7.1 Ordering Information .......................................... - 4.11 (Multi) Word/Byte Write Suspend Command ... 17 4.12 Set Block Lock-Bit Command.. ........................ 18 4.13 Clear Block Lock-Bits Command.. ................... 18 4.14 STS Configuration Command ......................... 19 Rev. 1.9 SHAFZP LHF16KA4 2 LH28F160S5NSL70 1GM-BIT (2MBx8/1 MBxl6) Smart 5 Flash MEMORY I Smart 5 Technology - 5V vcc - sv vpp n Enhanced Data Protection Features - Absolute Protection with Vpp=GND - Flexible Block Locking - Erase/Write Lockout during Power Transitions n Extended Cycling Capability - 100,000 Block Erase Cycles - 3.2 Million Block Erase Cycles/Chip n Low Power Management - Deep Power-Down Mode - Automatic Power Savings Mode Decreases ICC in Static Mode n Automated Write and Erase - Command User Interface - Status Register n Industry-Standard Packaging - 56-Lead SSOP n ETOXTM' V Nonvolatile Technology Flash n Common Flash Interface (CFI) - Universal & Upgradable Interface n Scalable Command Set (SCS) n High Speed Write Performance - 32'Bytes x 2 plane Page Buffer - 2pslByte Write Transfer Rate I I I High Speed Read Performance - 70ns(SV*O.25!/), 80ns(5V*OSV) Operating Temperature - 0C to +7O"C Enhanced Automated Suspend Options - Write Suspend to Read - Block Erase Suspend to Write - Block Erase Suspend to Read High-Density Symmetrically-Blocked Architecture - Thirty-two 64K-byte Erasable Blocks Write Interface x8 or x16 Operation I n CMOS Process (P-type silicon substrate) n Not designed or rated as radiation hardened n SRAM-Compatible n User-Configurable SHARP's LH28F160S5NS-L70 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage snd extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory :ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S5NSL70 offers three levels of protection: absolute protection with V,, at SND, selective hardware block locking, or flexible software block locking. These alternatives give designers Jltimate control of their code security needs. The LH28F160S5NS-L70 is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer `ates and minimize device and system-level implementation costs. The LH28F160S5NS-L70 is manufactured on SHARP's 0.35um ETOX TM* V process technology. ndustry-standard package: the 56-Lead SSOP, ideal for board constrained applications. `ETOX is a trademark of Intel Corporation. Rev. 1.9 It come in SHARP .1 INTRODUCTION This datasheet contains LH28F160SSNSL70 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LHF16KA4 3 execute code from any other flash memory array location. Individual block locking uses a combination of bits and WP#, Thirty-two block lock-bits, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. Block lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) set and cleared block lock-bits. The status register indicates when the WSM's block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. The STS output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using STS minimizes both CPU overhead and system power consumption. STS pin can be configured to different states using the Configuration command. The STS pin defaults to RY/BY# operation. When low, STS indicates that the WSM is performing a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. STS-High Z indicates that the WSM is ready for a new command, block erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down mode. The other 3 alternate configurations are all pulse mode for use as a system interrupt. The access time is 70ns (tAvQv) over the commercial temperature range (0C to +7O"C) and V,, supply voltage range of 4.75V-5.25V. At lower V,-c voltage, the access time is 80ns (4.5V-5.5V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical Icon current is 1 mA at 5V V,,. When either CEc# or CE,#, and RP# pins are at Vcc, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tpHQv) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL)from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 56-Lead SSOP (Shrink Small Outline Package). Pinout is shown in Figure 2. 1.l Product Overview The LH28F160S5NSL70 is a high-performance 16Mbit Smart 5 Flash memory organized as 2MBx8/1 MBxl6. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3. Smart 5' technology provides a choice of Vc, and V,, combinations, as shown in Table 1, to meet system performance and power expectations. 5V Vo, provides the highest read performance. V,, at 5V eliminates the need for a separate 12V converter, while V,,=5V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated V,, pin gives complete data protection when V+V,,L,. Table 1. V,, and VP, Voltage Combinations Offered by Smart 5 Technology Vcc Voltage Vpp Voltage E;v !iv detection Internal Vco . and Circuitry VW automatically configures the device for optimized read and write operations. .I' A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. A block erase operation erases one of the device's WK-byte blocks typically within 0.34s (5V Vco, 5V V,,) independent of other blocks. Each block can be independently erased 100,000 times (3.2 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. A word/byte write is performed in byte increments typically within 9.24us (5V Voc, 5V V,,). A multi word/byte write has high speed write performance of 2uslbyte (5V Voc, 5V V,,). (Multi) Word/byte write suspend mode enables the system to read data or Rev. 1.9 SHARF= _- LHFlGKA4 4 Figure 1. Block Diagram _ CEn,# A12. A13. A14 4s c$ VPP RP# 41 40 A9 Al A2 / NC A20 49 Ale A17 4s VCC i$ 56 LEAD SSQP 1.8mm x 16mm x 23.7mm TOP VIEW 43 A7 GND GND DQ6 vcc DQg DQI 43 DQ14 DQ7 DQls STS OE# WE# WP# DQa DQo 43 BYTE# NC 2, DQn DQ5 DQ12 DQ4 vcc DQlo DQ3 DQII GND Figure 2. SSOP 56-Lead Pinout L Rev. 1.9 SHARI= .-- - LHF16KA4 Table 2. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. Ao: Byte Select Address. Not used in x16 mode(can be floated). AI-AK Column Address. Selects 1 of 16 bit lines. A5-A15: Row Address. Selects 1 of 2048 word lines. Air+A20 : Block Address. DATA INPUT/OUTPUTS: DQo-DQ7:lnputs data and commands during CUI write cycles; outputs data during memory array, status register, query, and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQs-DQt5:lnputs data during CUI write cycles in xl 6 mode; outputs data during memory array read cycles in xl 6 mode; not used for status register, query and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(Byte#=V,, ). Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers decoders, and sense amplifiers. Either CE,# or CE,# V,, deselects the device and reduces power consumption to standby levels. Both CEr,# and CE,# must be V,, to select the devices. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP# V,, enables normal operation. When driven V,,, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). STS High Z indicates that the WSM is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. For alternate configurations of the `STATUS pin, see the Configuration command. WRITE PROTECT: Master control for block locking. When V,,, Locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on DQO-,, and DQs-,5 float. BYTE# V,, places the device in xl 6 mode , and turns off the A, input buffer. BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCKBIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or configuring block lock-bits. With V+V~~XL~, memory contents cannot be altered. Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid Vpp (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do not float any power pins. With Vc,IV,kO, all write attempts to the flash memory are inhibited. Device operations at invalid Voo voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated. 5 Symbol Type A0420 INPUT INPUT/ C )QO-DC&5 OUTPUT CE,#, CE,# INPUT RP# OE# WE# INPUT INPUT INPUT STS OPEN DRAIN OUTPUT WP# BYTE# INPUT INPUT VPP SUPPLY VCC SUPPLY SUPPLY GND NC Rev. 1.9 SHARP .2 PRINCIPLES . .- - LHF16KA4 6 OF OPERATION I FOOOO 1 EFFFF 1 EOOOJI 1 DFFFF 1 LIOOGQ 1CFFFF 1c0OOa 1 BFFFF lBO@JO IAFFFF IAOWO ISFFFF IWOOO IEFFFF 160000 17FFFF 17ocoO IGFFFF 16OMM 1 SFFFF The LH28F160S5NS-L70 Flash memory includes an on-chip WSM to manage block erase, full chip erase, write and block lock-bit (multi) word/byte configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status :egister, query structure and identifier codes can be accessed through the CUI independent of the VP, voltage. High voltage on VP, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. All functions associated with altering memory contents-block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes-are accessed via the CUI and verified through the status register. are written using standard Commands microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, (multi) word/byte write and block lockbit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, and margining of data. internal verification, Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. Interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. 150000 14FFFF 14OMx) 1 BFFFF 13OooO IPFFFF 120coO 1 IFFFF IIOWO 1OFFFF IWOQO OFFFFF OF0000 OEFFFF OEOOOO ODFFFF OLloGaO OCFFFF ocoooo OBFFFF 0B0000 OAFFFF OAOOOO OSFFFF 09CHY30 OBFFFF OtlMMO 07FFFF 07ccoo OGFFFF 06WOO OSFFFF o5oooo 04FFFF 040000 OBFFFF 03coOo OPFFFF OZooOO 01 FFFF 01OaJ0 OOFFFF Figure 3. Memory Map Rev. 1.9 SHARP .LHF16KA4 7 2.1 Data Protection 3.2 Output Disable Depending on the application, the system designer may choose to make the Vpp power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to V,,,,. The device accommodates either design practice and encourages optimization of the processor-memory interface. With OE# at a logic-high level (VI,), the device outputs are disabled. Output pins DC&,-DQ,, arc placed in a high-impedance state. 3.3 Standby Either CE,# or CE,# at a logic-high level (V,,) places the device in standby mode which substantially reduces device power consumption. DQ,-DQ,, outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, full chip erase, (multi) word/byte write ant block lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. When VpplVppLK, memory contents cannot be altered. The CUI, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit sequences, provides configuration command protection from unwanted operations even when high voltage {is applied to V,,. All write functions are disabled when Vcc is below the write lockout voltage V,,, or when RP# is at V,,. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations. 3.4 Deep Power-Down RP# at V,, initiates the deep power-down mode. In read modes, RP#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQv is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, norma operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, `full chip erase, (multi) word/byte write or block lock-bit configuration modes, RP#-low will abort the operation. STS remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHwL is required after RP# goes to logic-high (V,,) before another command can be written. As with any automated device, it is important tc assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may no! occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3 BUS OPERATION The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, query structure,`.or status register independent of the V,, voltage. RP# must be at VI,. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component: CE# (CE,#, CE,#), OE#, WE#, RP# and WP#. CE,#, CE,# and OE# must be driven active to obtain data at the outputs. CE,#, CE,# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQc-DQ,s) control and when active drives the selected memory data onto the I/O bus. WE# and RP# must be at V,,. Figure 17, 18 illustrates a read cycle. Rev. 1.9 SHARI= LHF16KA4 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. a 3.6 Query Operation The query operation outputs the query structure. Query database is stored in the 48Byte ROM. Query structure allows system software to gain critical information for controlling the flash component. Query structure are always presented on the lowestorder data output (DQc-DQ,) only. 3.7 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When Vcc=Vcc1,2 and VPP=VPPHI, the CUI additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/byte Write command requires the command and address of the location to be written. Set Block Lock-Bit command requires the command and block address within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 19 and 20 illustrate WE# and CE#-controlled write operations. 1FFFFF 1 ' :. "&tie. l~plementation IF0006 1 FOO05 1 FOOQ4 1 FOO03 `.. ml ~' 31 Status Code ----------------------- Reserved fbr ~tufe fmplementation " Block 31 1Foooo 1 EFFFF 020000 01 FFFF 3locks2thiw$i30) : 4. Resewed. far Future tmplementation 01ocHx~ 010005 010004 010003 .; " t-----------------------t-------------- ovlooo OOFFFF ----------. I I i Ft i ___----------------- Block 1 Status Code _----------------- ------- 4 COMMAND DEFINITIONS : When the V,, voltage I V,,,,, Read operations from the status register, identifier codes, query, or blocks are enabled. Placing V,,,, on V,, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. bsatnted for rture lmpl&w4~tion `.. / ._______----------------------n'- -I- I MOCK `I Status Code :ode "- - `acturer Code ManuT Black 0 Figure 4. Device Identifier Code Memory Map Rev. 1.9 SliARP LHFlGKA4 Mode Read Output Disable Standby Deep Power-Down Read Identifier Codes Query I 9 Notes 1,2,3,9 3 3 4 9 9 I Table 3. Bus ODerations(BYTE#=VIuI RP# CE"# CE,# OE# WE# V,, V,, V,, V,H V,H V,w V,, V,, V,H V,M VI, VI, VlH 4, Address X X X X See Figure 4 See Table I Vpp X X X X X x I DQ0.,5 Dn,,r High Z High Z High Z Note 5 Note 6 1 DIN 1 STS X X X High Z High Z High Z x X x VI, VI, I I X X vlH VI, V,, VI, VI, I x~ YL VI, V,H x- 4, VI, I 7-11 Write 13,7,8,9 1 V,H 1 VI, 1 v,, 1 V,I-I 1 v,, 1 i 1 x Deep Power-Down Read identifier Codes Query 4 9 9 V,, `IH vlH X VI, VI, X VI, VI, X VI, VI, X vlH vlH X DIN X 3,7,8,9 VIH V,, V,, V,H v,, Write IOTES: I. Refer to DC Characteristics. When VpplVppLK, memory contents can be read, but not altered. !. X can be VI, or VI, for control pins and addresses, and V,,,, or VP,,, for V,,. See DC Characteristics for V,,,, and VP,,, voltages. !. STS is Vo, (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep powegdown mode. 8 i. RP# at GNDfl.2V ensures the lowest deep power-down current. i. See Section 4.2 for read identifier code data. i. See Section 4.5 for query data. `. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when VPP=VPrzzHt Vco=Voo1,2. and I. Refer to Table 4 for valid D,, during a write operation. L Don't use the timing both OE# and WE# are V,,. X See Figure 4 See Table 7-11 X X X x High Z Note 5 Note 6 High Z High Z High Z Rev. 1.9 SHAI?l= . LHFlGKA4 10 Command Read Array/Reset Read Identifier Codes Query Read Status Register Clear Status Reaister Block Erase Setup/Confirm Full Chip Erase Setup/Confirm Word/Byte Write Setup/Write Alternate Word/Byte Write SetuoMlrite Multi Word/Byte Write a WA E8H Write WA N-l SetuoKonfirm Block Erase and (Multi) E \A/&m 1 x BOH Word/byte Write Suspend Confirm and Block Erase and Write X DOH 1 5 (Multi) Word/byte Write Resume Write BA 2 7 Write BA 60H OlH Block Lock-Bit Set Setup/Confirm Block Lock-Bit Reset Write X 2 8 Write X 60H DOH Setup/Confirm STS Configuration Write X B8H Write X OOH 2 Level-Mode for Erase and Write (RY/BY# Mode) I I I I I I I I STS Configuration Write X Write Pulse-Mode for Erase STS Configuration Write X Write Pulse-Mode for Write STS Configuration Write 2 Write X Pulse-Mode for Erase and Write NOTES: 1. BUS operations are defined in Table 3 and Table 3.1. 2. X=Any valid address within the device. IA=ldentifier Code Address: see Figure 4. QA=Query Offset Address. BA=Address within theblock being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 14 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes. QD=Data read from query database. 4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status codes. See Section 4.2 for read identifier code data. 5. If the block is locked, WP# must be at VI, to enable block erase or (multi) word/byte write operations. Attempts to issue a block erase or (multi) word/byte write to a locked block while RP# is VI,. 6. Either 40H or 10H are recognized by the WSM as the byte write setup. 7. A block lock-bit can be set while WP# is VI,. 8. WP# must be at VI, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. 9. Following the Third Bus Cycle, inputs the write address and write data of `N' times. Finally, input the confirm command `DOH'. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. \Alrita Table 4. Command Definitions(lO) First Bus Cycle Second Bus Cycle Bus Cycles Notes Req'd Oper(`) 1 Addr(*) 1 Data13) Oper(`) 1 Addr(*) Datat3) 1 Write 1 X 1 FFH 4 Write X IA ID 22 22 Write X , SA QD 2 Write X 70H 1 Read 1 X SRD I Write I X I 50H 1 I 1 I 2 5 Write BA 20H Write BA DOH 2 Write X 30H Write X DOH Write WA 40H Write WA WD 2 56 r) CC \A/ritn WA 10H Write WA WD El! I Rev. 1.9 SHARP .- LHFlGKA4 4.3 Read Status Register Command 11 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend and (Multi) Word/byte Write Suspend command. The Read Array command functions independently of the V,, voltage and RP# must be VI,- The status register may be read to determine when a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully(see Table 14). It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#(Either CE,# or CE,#), whichever occurs. OE# or CE#(Either CE,# or CE,#) must toggle to VrH before further reads to update the status register latch. The Read Status Register command functions independently of the V,, voltage. RP# must be VI,. The extended status register may be read to determine multi word/byte write availability(see Table 14.1). The extended status register may be read at any time by writing the Multi Word/Byte Write command. After writing this command, all subsequent read operations output data from the extended status register, until another valid command is written. Multi Word/Byte Write command must be re-issued to update the extended status register latch. 4.2 &ad Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device, block lock configuration and block erase status (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the V,, voltage and RP# must be VI,. Following the Read Identifier Codes command, the following information can be read: Table 5. Identifier Codes Code Address 00000 Manufacture Code 0000 1 00002 Device Code 00003 Block Status Code Data BO DO 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3 and SR.l are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 14). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurs during the sequence. To clear the status register, the Clear Status Register command @OH) is written. It functions independently of the applied V,, Voltage. RP# must be Vi,. This command is not functional during block erase, full chip erase, (multi) word/byte write block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes. l Last erase operation 1 DQ,=O 1 completed successfully *Last erase operation did DC&=1 not completed successfully *Reserved for Future Use DQ3-, _ NOTE: 1. X selects the specific block status code to be read. See Figure 4 for the device identifier code memory map. Rev. 1.9 SHARP LHF16KA4 -- 12 1.5 Query Command ;luery database can be read by writing Query :ommand (98H). Following the command write, read ycle from address shown in Table 7-l 1 retrieve the xitical information to write, erase and otherwise :ontrol the flash component. A, of query offset iddress is ignored when X8 mode (BYTE#=V,L). Juery data are always presented on the low-byte lata output (DQc-DQ,). In x16 mode, high-byte :DQs-DQ,s) outputs OOH. The bytes not assigned to iny information or reserved for future use are set to `0". This command functions independently of the J,, voltage. RP# must be VI,. 4 Table 6. Example of Query Structure Output Mode Offset Address output DQ,5;-8 D&-n A,, A,, A,, A,, A,, A, 1 , 0 , 0 , 0 , 0 , 0 (20H) High Z "Q" X8mode 1 ,O,O,O,O,l (21H) HighZ "Q" 1, O,O,O,l ,0(22H) HighZ "R" 1 , 0 , 0 , 0 , 1 , 1 (23H) High Z "R" A,, A,, A,, A,, A, X16mode 1 ,O,O,O,O (10H) OOH "Q" 1 ,O,O,O,l (11H) OOH "R" 1.5.1 Block Status Register rhis field provides lock configuration and erase status for the specified block. These informations are only available Nhen device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status Iit will be set to "1 `I. If bit 1 is "l", this block is invalid. Table 7. Query Block Status Register Offset (Word Address) (BA+2)H Length OlH Description Block Status Register bit0 Block Lock Configuration O=Block is unlocked 1=Block is Locked bit1 Block Erase Status O=Last erase operation completed successfully l 1=Last erase operation not completed successfully bit2-7 reserved for future use i' Uote: I. BA=The beginning of a Block Address. Rev. 1.9 SHARP .~. LHFlGKA4 String 13 -- - 4.5.2 CFI Query Identification The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Table 8. CFI Query Identification Offset (Word Address) lOH,llH,12H 13H,14H 15H,16H 17H,18H \ lSH,lAH Length 03H 02H 02H 02H 02H String Description Query Unique ASCII string "QRY" 51 H,52H,59H Primary Vendor Command Set and Control Interface ID Code 01 H,OOH (SCS ID Code) Address for Primary Algorithm Extended Query Table 31 H,OOH (SCS Extended Query Table Offset) Alternate Vendor Command Set and Control Interface ID Code OOOOH(OOOOH means that no alternate exists) Address for Alternate Algorithm Extended Query Table OOOOH(OOOOH means that no alternate exists) 4.53 System Interface Information The following device information can be useful in optimizing system interface software. Table 9. System Information Offset (Word Address) 1BH 1CH 1DH 1EH 1FH 20H 21H 22H / 23H 24H 25H 26H ./' Length OlH OlH OlH OlH .Ol H 01H OlH OlH OlH OlH OlH OlH String Description Vc, Logic Supply Minimum Write/Erase voltage 27H (2.7V) V,, Logic Supply Maximum Write/Erase voltage 55H (5.5V) V,, Programming Supply Minimum Write/Erase voltage 27H (2.7V) U,, Programming Supply Maximum Write/Erase voltage 55H (5.5V) Typical Timeout per Single Byte/Word Write 03H (23=8us) Typical Timeout for Maximum Size Buffer Write (32 Bytes) 06H (26=64us) Typical Timeout per Individual Block Erase OAH (OAH=lO, 210=1 024ms)Typical Timeout for Full Chip Erase OFH (OFH=15, 215=32768ms) Maximum Timeout per Single Byte/Word Write, 2N times of typical. 04H (24=1 6, 8usxl6=128us) Maximum Timeout Maximum Size Buffer Write, 2N times of typical. 04H (24=16, 64usxl6=1024us) Maximum Timeout per Individual Block Erase, 2N times of typical. 04H (24=1 6,1024msxl6=16384ms) Maximum Timeout for Full Chip Erase, 2N times of typical. 04H (24=1 6,32768msxl6=524288ms) Rev. 1.9 SHARP .- LHF16KA4 14 1.5.4 Device Geometry Definition rhis field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset (Word Address) 27H 28H,29H 2AH,2BH 2CH 2DH,2EH 4 2FH,30H Length OlH 02H 02H OlH 02H 02H Description Device Size 15H (15H=2 1, 221=2097152=2M Bytes) Flash Device Interface description 02H,OOH (x8/x1 6 supports x8 and xl 6 via BYTE#) Maximum Number of Bytes in Multi word/byte write 05H,OOH (2s=32 Bytes ) Number of Erase Block Regions within device 01 H (symmetrically blocked) The Number of Erase Blocks 1FH,OOH (1 FH=31 ==> 31+1=32 Blocks) The Number of "256 Bytes" cluster in a Erase block OOH,OlH (01 OOH=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block) 1.5.5 SCS OEM Specific Extended Query Table Zertain flash features and commands may be optional in a vendor-specific algorithm specification. The optional rendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s). Table 11. SCS OEM Specific Extended Query Table Offset (Word Address) 31 H,32H,33H 34H 35H 36H,37H, 38H,39H Length 03H OlH OlH 04H " Description PRI 50H,52H,49H 31 H (1) Major Version Number , ASCII 30H (0) Minor Version Number, ASCII OJ=H,OOH,OOH,OOH Optional Command Support bitO=l : Chip Erase Supported bitl=l : Suspend Erase Supported bit2=1 : Suspend Write Supported bit3=1 : Lock/Unlock Supported bit4=0 : Queued Erase Not Supported bit5-31=0 : reserved for-future use OlH Supported Functions after Suspend bitO=l : Write Supported after Erase Suspend bit1 -7=O : reserved for future use 03H,OOH Block Status Register Mask bitO=l : Block Status Register Lock Bit [BSR.O] active bitl=l : Block Status Register Valid Bit [BSR.l] active b&Z-15=0 : reserved for future use Vcc Logic Supply Optimum Write/Erase voltage(highest performance) 50H(5OV) V,, Programming Supply Optimum Write/Erase voltage(highest performance) 50H(5.OV) Reserved for future versions of the SCS Specification 3AH OlH 3BH,3CH 02H 3DH 3EH 3FH OlH OlH reserved Rev. 1.9 SHARP .-- - LHFlGKA4 15 4.6 Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the STS pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when Vcc=Vcc,,2 and VPP=VPPH1.In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while V,,IV,,,,, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or if set, that WP#=V,,. If block erase is attempted when the corresponding' block lock-bit is set and WP#=VIL, SR.l and SR.5 will be set.to "1". erase setup is first written, followed by a full chip erase confirm. After a confirm command is written, device erases the all unlocked blocks from block 0 to Block 31 block by block. This command sequencr requires appropriate sequencing. Bloc1 preconditioning, erase and verify are handlec internally by the WSM (invisible to the system). Afte the two-cycle full chip erase sequence is written, tht device automatically outputs status register dat; when read (see Figure 6). The CPU can detect ful chip erase completion by analyzing the output data o the STS pin or status register bit SR.7. When the full chip erase is complete, status registe bit SR.5 should be checked. If erase error i! detected, the status register should be cleared before system software attempts corrective actions. The CU remains in read status register mode until a nev command is issued. If error is detected on a bloc1 during full chip erase operation, WSM stops erasing Reading the block valid status by issuing Read IC Codes command or Query command informs whict blocks failed to its erase. This two-step command sequence of set-up followec by execution ensures that block contents are no accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable ful chip erasure can only occur when Vcc=Vcc1,2 ant In the absence of this high voltage, block VPP=VPPHIcontents are protected against erasure. If full chir erase is attempted while Vpp~Vpp,k, SR.3 and SR.E will be set to "1". When WP#=V,,, all blocks are erased independent of block lock-bits status. Wher WP#=V,,, only unlocked blocks are erased. In this case, SR.l and SR.5 will not be set to "1". Full chip erase can not be suspended. 4.7 Full Chip Erase Command This command followed by a confirm command (DOH) erases all of the unlocked blocks. A full chip Rev. 1.9 SHARP .- LHF16KA4 16 4.8 Word/Byte Write Command Word/byte write is executed by a two-cycle command sequence. Word/Byte Write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect the completion of the word/byte write event by analyzing the STS pin or status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when Vcc=Vcc,,2 and VPP=VPPH1. In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while V,+V,,L,, status register bits SR.3 and SR.4 will be set to "1 `I. Successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=V,,. If word/byte write is attempted when the corresponding block lock-bit is set and WP#=V,L, SR.l and SR.4 will be set to "1 `I. Word/byte write operations with V,LcWP#cV,, produce spurious results and shquld not be attempted. continue monitoring XSR.7 by writing multi word/byte write setup with write address until XSR.7 transitions to 1. When XSR.7 transitions to 1, the device is ready for loading the data to the buffer. A word/byte couni (N)-1 is written with write address. After writing a word/byte count(N)-1, the device automatically turns back to output status register data. The wordlbyte count (N)-1 must be less than or equal to 1FH in x8 mode (OFH in x16 mode). On the next write, device start address is written with buffer data. Subsequent writes provide additional device address and data depending on the count. All subsequent addres must lie within the start address plus the count. Afte the final buffer data is written, write confirm (DOH must be written. This initiates WSM to begin copyinf the buffer data to the Flash Array. An invalid Mull Word/Byte Write command sequence will result ir both status register bits SR.4 and SR.5 being set tc "I ". For additional multi word/byte write, write anothe multi word/byte write setup and check XSR.7. Thf Multi Word/Byte Write command can be queue< while WSM is busy as long as XSR.7 indicates "1" because LH28F160S5NS-L70 has two buffers. If ar error occurs while writing, the device will stop writin< and flush next multi word/byte write command loadec in multi word/byte write command. Status register bi SR.4 will be set to "1". No multi word/byte write command is available if either SR.4 or SR.5 are se to "1 `I. SR.4 and SR.5 should be cleared before issuing multi word/byte write command. If a mult word/byte write command is attempted past an era.% block boundary, the device will write the data to Flast Array up. to an erase block boundary and then star writing. Status register bits SR.4 and SR.5 will be se1 to "1 `I. Reliable multi byte writes can only occur wher Vcc=VccI12 and VPP=VPPHI. In the absence of this high voltage, memory contents are protected againsl multi word/byte writes. If multi word/byte write is attempted while V,,sV,,L,, status register bits SR.3 and SR.4 will be set to "1". Successful multi word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=V,,. If multi byte write is attempted when the corresponding block lock-bit is set and WP#=V,L, SR.l and SR.4 will be set to "1 `I. 4.9 Multi Word/Byte Write Command Multi word/byte write is executed by at least fourcycle or up to 35cycle command sequence. Up to 32 bytes in x8 mode (16 words in x16 mode) can be oaded into the buffer and written to the Flash Array. First, multi word/byte write setup (E8H) is written with :he write address. At this point, the device automatically outputs extended status register data :XSR) when read (see Figure 8, 9). If extended status register bit XSR.7 is 0, no Multi Word/Byte Nrite command is available and multi word/byte write setup which just has been written is ignored. To retry, Rev. 1.9 SHARP ..- _- LHFlGKA4 17 1.10 Block Erase Suspend Command The Block Erase Suspend command allows blockerase interruption to read or (multi) word/byte-write data in another block of memory. Once the block3rase process starts, writing the Block Erase Suspend command requests that the WSM suspend :he block erase sequence at a predetermined point in :he algorithm. The device outputs status register data Nhen read after the Block Erase Suspend command s written. Polling status register bits 93.7 and SR.6 :an determine when the block erase operation has 3een suspended (both will be set to "1"). STS will also transition to High Z. Specification twHRH2 defines :he block erase suspend latency. 4t this Roint, a Read Array command can be written :o read data from blocks other than that which is suspended. A (Multi) Word/Byte Write command sequence can also be issued during erase suspend :o program data in other blocks. Using the (Multi) rNord/Byte Write Suspend command (see Section 1.1 l), a (multi) word/byte write operation can also be suspended. During a (multi) word/byte write operation Nith block erase suspended, status register bit SR.7 NilI return to "0" and the STS (if set to RY/BY#) output will transition to VOL. However, SR.6 will *emain "1' to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume :ommand is written to the flash memory, the WSM NilI continue the block erase process. Status register ,its SR.6 and SR.7 will automaticajly clear and STS NilI return to VOL. After the Erase Resume command s written, the device automatically outputs status ,egister data when read `(see Figure 10). Vpp must *emain at VP,+,, (the same V,, level used for block xase) while block erase is suspended. RP# must aIs0 remain at V,,. Block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed. 4.11 (Multi) Word/Byte Command Write Suspend The (Multi) Word/Byte Write Suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. Once the (multi) word/byte write process starts, writing the (Multi) Word/Byte Write Suspend command requests that the WSM suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the (Multi) Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to "1"). STS will also transition to High Z. Specification twHRr+ defines the (multi) word/byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while (multi) word/byte write is suspended are Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and STS will return to VOL. After the (Multi) Word/Byte Write command is written, the device automatically outputs status register data when read (see Figure 11). V,, must remain at VppH1 (the same V,, level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. WP# must also remain at V,, or YL. Rev.1.9 ..- - LHFlGKA4 18 4.12 Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V,,+ individual block lock-bits can be set using the Set Block Lock-Bit command. See Table 13 for a summary of hardware and software write protection options. Set block lock-bit is executed by a two-cycle command sequence. The set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set block lock-bit algorithq. After the sequence is written, the device automatically outputs status register data when read (see Figure 12). The CPU can detect the completion of the set block lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set block lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being setto "1 `I. Also, reliable operations occur Drily when Vcc=Vccj,2 and VPP=VPPH,. In the absence of this high voltage, block lock-bit contents are protected against alteration. 4 successful set block `lock-bit operation requires NP#=V,,. If it is attempted with WP#=V,,, SR.l and jR.4 will be set to "1" and the operation will fail. Set Ilock lock-bit operations with WP# 411set block lock-bits are cleared in parallel via the Zlear Block Lock-Bits command. With WP#=V,,, Rev.1.9 SHARP _- ~. Command LHFlGKA4 19 I.14 STS Configuration The Status (STS) pin can be configured to different ;tates using the STS Configuration command. Once he STS pin has been configured, it remains in that :onfiguration until another configuration command is ssued, the device is powered down or RP# is set to J,,. Upon initial device power-up and after exit from leep power-down mode, the STS pin defaults to ?Y/BY# operation where STS low indicates that the NSM is busy. STS High 2 indicates that the WSM is ,eady for a new operation. To reconfigure the STS pin to other modes, the STS Configuration is issued followed by the appropriate :onfiguration code. The three alternate configurations ire all pulse mode for use as a system interrupt. The ;TS Configuration command functions independently If the V,, voltage and RP# must be VI,. Table 12. STS Configuration Coding Description Configuration Effects Bits Set STS pin to default level mode (RY/BY#). RY/BY# in the default OOH level-mode of operation will indicate WSM status condition. Set STS pin to pulsed output signal for specific erase operation. In this mode, STS provides low pulse at OlH the completion of BLock Erase, Full Chip Erase and Clear Block Lock-bits operations. Set STS pin to pulsed output signal for a specific write operation. In this 02H mode, STS provides low pulse at the completion of (Multi) Byte Write and Set Block Lock-bit operation. Set STS pin to pulsed output signal for specific write and erase operation. STS provides low pulse 03H at the completion of Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-bit Configuration operations. Table 13. Write Protection Operation Block Erase, (Multi) Word/Byte Write .,.' Full Chip Erase Set Block Lock-Bit Clear Block Lock-Bits Block Lock-Bit 0 , WP# V,, or V,,, VI, VI, Alternatives Effect 0,1 X X X V,, V,I , V,, V,H V,, V,H Block Erase and (Multi) Word/Byte Write Enabled Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled All unlocked blocks are erased, locked blocks are not erased All blocks are erased Set Block Lock-Bit Disabled Set Block Lock-Bit Enabled Clear Block Lock-Bits Disabled Clear Block Lock-Bits Enabled Rev. 1.9 SHARI= .- WSMS 7 1 BESS 6 / Table 14. Status Register Definition ECBLBS 1 WSBLBS 1 VPPS 1 wss 5 4 3 NOTES: SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS 1 = Error in Erase or Clear Bloc1 Lock-Bits 0 = Successful Erase or Clear Block Lock-Bits 4 SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS 1 = Error in Write or Set Block Lock-Bit 0 = Successful Write or Set Block Lock-Bit SR.3 = V,, STATUS 1 = V,, Low Detect, Operation Abort O=V,,OK SR.2 = WRITE SUSPEND STATUS 1 = Write Suspended 0 = Write in Progress/Completed SR.l = DEVICE PROTECT STATUS 1 = Block Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock` SR.0 = RESERVED FOR FUTURE'ENHANCEMENTS Table 14.1. Extended R R I 5 4 Status Register Definition R R 2 3 NOTES: XSR.7 = STATE MACHINE STATUS 1 = Multi Word/Byte Write available 0 = Multi Word/Byte Write not available XSR.G-O=RESERVED FOR FUTURE ENHANCEMENTS XSR.G-0 is reserved for future use and should be masked out when polling the extended status register. After issue a Multi Word/Byte Write command: XSR.7 indicates that a next Multi Word/Byte Write command is available. Check STS or SR.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1 "s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or STS configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of V,, level. The WSM interrogates and indicates the V,, level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when V,,+V,,,, . SR.l does not provide a continuous indication of block lock-bit values. The WSM interrogates block lock-bit, and WP# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set and/or WP# is not V,,. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. 2 DPS 1 R 0 LHFlGKA4 20 1 1 SMS 7 R 6 R 1 R 0 Rev. 1.9 SHARI= LHF16KA4 21 r Command I write Read Read Statis Register Data-70H AddhX Status Register Data Standby Check SR.7 l-WSM Ready 0sWSM Busy Erase Setup Data-ZOH AddhWithin Block to be Erased Data-DOH Add-Within Wnte I write Erase Confirm Block to be Erased I Read / / Status Register Data Standby Check SR.7 l=WSM Ready 0.xWSM Busy Repeat for subsequent block erasures. Full stake check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in mad array mode. Check if Desired FULL STATUS CHECK PROCEDURE (7) ) Bus Operation Command I Check SR.3 t=Vpp Error Detect Standby Standby Check SR.4.5 Both l=Command Sequence Error Check SR.5 l-Block Erase Error I Standby SRS.SR.4.SR.3 and SR.l am only cleared by the Clear Status Register Command in casas where multiple blocks am emsed If ermr IS detected. clear the Status Register before attempting Figure 5. Automated Block Erase Flowchart Rev. 1.9 SHARP _- - LHFlGKA4 22 (-y-) write 1 I Standby Read 1 I I Command Read Status Register Data=70H Addr=X 1 Status Register Data I I Check SR.7 l.WSM Ready O-WSM Busy Full Chip Erase S-JP Full Chip Erase Conflml Data-3OH Ad&-X Data-DOH Add-X I Write Write Read Status Register Data I Full stalls check can b-a done after each full chip erase. Write FFH after tie last operation to place device in read army mode. Check if Desired Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Command Comments Standby Chedc SR.3 laVpp Error Detect Check SR.4,5 Both 1-Command Sequence Error Check SR.5 l-Full Chip Erase Error Standby Standby SRS.SR.4.SR.3 and SR.l are only deared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If enw is detected, clear the St&e Register before attempting retry or other error recovery. Figure 6. Automated Full Chip Erase Flowchart Rev. 1.9 Bus Operation Command Commanb write Read Status Register Data=70H Addr-X Read stahls Read Status Register Data Reglrter Standby SR.7= 23 0 Setup Word/Byte Write Check SR.7 1-WSM Rea&+ O=WSM Bury Data-40H or 1OH Addr-Location to Be Written Data-Data to Be Written Addr-Location to Be Wlitten &, . wiite Wlfte WordByte write Data and Address Read Status Register Data standby Check SR.7 l=WSM Ready O=WSM Busy Repeat for subsequent wotiyte writes. SR full status check can be done after each wordmyte write. or after a sequence of wmdhyte writes. Write FFH after the last word/byte write operation to place device m read array mode. Check if Desired FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus operation Command Commenla Standby Check SR.3 l=VP, Error Detect Check SR.1 l=Device Protect Detect WPX=V,$Jock Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4 l-Data Write Error Standby Dwce Protect Error Standby SR.4.SR.3 and SR.l are only cleared by the Clear Status Ragstar command in cases where multiple lxabons are wtftten before full status IS checked. If error is detected, clear the Status Register before attempbng retry or other error recovery. Figure 7. Automated Word/byte Write Flowchart Rev. 1.9 SHARP LHFlGKA4 Bus Operation Read Extend status Register Command Commenk Wlik SetuP Multi WordlByte Write DatapE3f-l Addr=Stwt Address Read Extended Status Register Data standby Check XSR.7 1rMulti Wml/Byk O=MJlti wodmyk Wtite Ready write Busy write (Nokl) write (Note2.3) write (Note4.5) Data-Word or Byte Count (N)-1 Add&tart Address Data=Buffer Data Addr-Start Address Data=Buffer Data AddrPDevice Address Data=DOH Addr-X write Read Status Register Data Check SR.7 I=WSM Ready OIWSM Busy Write Anotier Block Address Standby Write Buffer Data, Device Address Multi Word/Byte Write Abort 1, Byte or word count values on DQ,., are loaded into the count register. 2. Write Buffer contents will be programmed at the start address. 3. Align the start address on a Write Buffer boundary for mamum programming performance. 4.The device aborts the Multi Word/Byte Write command if the current address is oukide of the original blockaddress. B.The Status Register indicates an `improper command sequence' if the Multi Word/Byte command is aborted. Follow this with a Clear Status Register command. SR lull status check can be done after each multi word/byte write. or after a sequence of multi wonVbyte writes. Write FFH afterthe last multi w&byte write operation to place device in read army mode. Figure 8. Automated Multi Word/Byte Write Flowchart Rev. 1.9 SHARI= _LHFlGKA4 25 FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Bus Operalion Command Comments Standby Check SR.3 l-VP,, Error Detect Check SRI l=Dovica Protect Detect WP#+,Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4.5 Both l-Command Sequence Error Check SR.4 14ata Write Error standby Device Protect Enor Standby Standby SRS.SR.4.SR.3 and SR.1 are only deared by the Clear Status Register command in cases where multiple locations are written before full status is checked. I`f ermr)s detected, clear the Status Regtstar before attempting retry or other efmr reccNery. Figure 9. Full Status Check Procedure for Automated Multi Word/Byte Write Rev. 1.9 LHFlGKA4 Reed status Ragistar Data Addr.=X Check SR.7 1-WSM Rea&y O-WSM Busy check SR.6 l-Block Erase Sutpwded O-Block Ease Completed Data-WI-l Addr-X c\iSR.7= 1 0 Read Standby standby Write Figure IO. Block Erase Suspend/Resume Flowchart Rev.1.9 SHARI= LHF16KA4 27 stall Command Comments write 5x4 =I_I Read status Register Read (Multi) wonvByta Wntc Suspend Data-SOH AddhX Status Register Data Addr-X Check SR.7 l=WSM Rea* OIWSM Busy Check SR.2 l=(MlJlti) wo#Syte write suspendsd Ow(Multl) Word/Byte Write Completed standby SR.73 O 3 1 (Multi) write\ woldmte Complel ted Data..FFH AddhX Read Array lccatiis other than that being written. Data-DOH Addr-X Figure 11. (Multi) Word/Byte Write Suspend/Resume Flowchart Rev. 1.9 SHARI= LHFlGKA4 Command I Sat Block Write Lock-Bit Selup Data-6OH Add&lock Address write I Set Block Lock-Bit Confirm 1 DatazOlH. Add&lock Address Check if Desired Repeat for subsequent block lock-bit set operations. Full status cback can be done after each block l&-bit set operation or after a sequence of block lock-bit sat operabns. Wri!e FFH after the last block lock-bit sat operation to place device in read array mode. Set Block Lock-Sit FULL STATUS CHECK PROCEDURE Command Standby Check SR.3 l=Vpp Error Detect SRS.SR.4.SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple Mock lock-bits are set before Figure 12. Set Block Lock-Bit Flowchart 1 Rev. 1.9 SHARP LHF16KA4 29 Wlite 60H Clear Block Lock-Bits Confinn Data-DOH Add-X Write Write DOH Read Slatus Register Data Standby Check SR.7 l=WSM Ready o=WSM Busy Write FFH after the Clear Block Lock-Bits operation to place device in read army mode. Full Status Check if Dewed Clear Block Lock-Sits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) BUS OpSMiOll Command j Standby 1 Check SR.3 I-Vpp Error Detect Check SR.l l-Device Protect Detect WP%.V,L I I SRS,SR.4.SR.3 and SR.l are only cleared by the Clear Status Register command. If enor is detected, clear the Status Register before attempting mhy or other envr recovery. Figure 13. Clear Block Lock-Bits Flowchart Rev. 1.9 SHARI= LHFlGKA4 .- - 30 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. three control inputs to SHARP provides accommodate multiple memory connections. ThreeLine control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ#,control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. STS, in default mode, is also High Z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a O.luF ceramic capacitor connected between its Vcc and GND and between its V,, and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7uF electrolytic capacitor should be placed at the array's power supply connection between Voc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Polling STS is an open drain output that should be connected to Vcc by a pullup resistor to provide a hardware method of detecting block erase, full chip erase, (multi) word/byte write and block lock-bit completion. In default mode, it configuration transitions low after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to V,, when the WSM has finished executing the. internal algorithm. For alternate STS pin configurations, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. 5.4 Vpp Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V,, Power supply trace. The V,, pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. Use similar trace widths and layout considerations given to the Vcc power bus. Adequate V,, supply traces and decoupling will decrease V,, voltage spikes and overshoots. Rev. 1.9 SHARP LHFlGKA4 .- 31 5.5 Vcc, Vpp, RP# Transitions Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if V,, falls outside of a valid V,,,, range, Vcc falls outside of a valid Vcc,,2 range, or RP#=V,,. If V,, error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V,, during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, STS(if set to RY/BY# mode) will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to V,, clear thd status register. The CUI latches commands issued by system software and is not altered by V,, or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Vcc transitions below V,ko. After block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after V,, transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. powers-up first. Internal circuitry resets the CUI tc read array mode at power-up. A system designer must guard against spuriou: writes for Vco voltages above VLKO when V,, iz active. Since both WE# and CE# must be low for i command write, driving either to V,, will inhibit writes The CUl's two-step command sequence architecture provides added level of protection against datz alteration. In-system block lock and unlock capability prevent: inadvertent data alteration. The device is disablec while RP#=V,, regardless of its control inputs state. 5.7 Power Dissipation When designing portable systems, designers mus consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatilib increases usable battery life because data is retainec when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when systerr power is applied. For example, portable computing products and other power sensitive applications thal use an array of devices for solid-state storage car consume negligible power by lowering RP# to VI, standby or sleep modes. If access is again needed. the devices can be read following the t,HQv ant tPHWL wake-up cycles required after RP# is firsi raised to V,,. See AC CharacteristicsRead Only and Write Operations and Figures 17, 18, 19, 20 for more information. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during Dower transitions. Upon power-up, the device is indifferent as to which power supply (V,, or Voc) Rev. 1.9 SHARP .6 ELECTRICAL 6.1 Absolute -- SPECIFICATIONS Maximum Ratings* LHFlGKA4 32 *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on Vcc and V,, pins. During transitions, this level may undershoot to -2.OV for periods <20ns. Maximum DC voltage on input/output pins and Vcc is Vcc+OSV which, during transitions, may overshoot to Vcc+2.OV for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration . .. .. ...O"C to +70"C(1) Temperature under Bias .. .. .. .. .. .. .. . -10C to +8O"C Storage Temperature .. .. . .. ... . ... . .. .. ... .. -65C to +125"C Voltage On Any Pin (except Vcc, V,,) . .. .. . ... .. . .. . -09 to Vcc+0.5V(2) V,, Suply Voltage .. .. .. .. .. .. .. .. .. .. . .. ... .. -0.2v to +7.ov(2) V,, Upgate Voltage during Erase, Write and Block Lock-Bit Configuration . ... ..-0.2V to +7.0Vt2) Output Short Circuit Current . .. .. .. .. .. .. . ... . .. ... . 100mA(3) 6.2 Operating Symbol Ta Vnc, ~v(-y Conditions and Vcc Ouerating Conditions Min. Max. Unit 0 +70 "C 4.75 5.25 V 4.50 5.50 V Test Condition Ambient Temperature Temperature Parameter Operating Temperature Vnr: Supply Voltage (5ViO.25V) Vno Supply Voltage (5V+O.5V) 6.2.1 CAPACITANCE(l) ,, Symbol Parameter. C,N Input Capacitance cn, ,T Output Capacitance VOTE: I. Sampled, not 100% tested. T,=+25"C, Typ. 7 9 f=l MHz Max. 10 12 Unit pF pF Condition v,,=o.ov Vn, ,T=O.OV Rev. 1.9 SHARP _.. i LHFl6KA4 33 2.2 AC INPUT/OUTPUT TEST CONDITIONS AC test inputs are driven at 3.OV for a Logic "1" and O.OV for a Logic Input rise and fall times (10% to 90%) cl 0 ns. "0." input timing begins, and output timing ends, at 1.W. Figure 14. Transient Input/Output Reference Waveform for VcC=5V*0.25V (High Speed Testing Configuration) 4 o~T-)(--pzfzy)(yr AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" ahd VOL (0.45 VTL) for a Logic "0." input timing begins (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. input rise and fall times (10% to 90%) ~10 ns. at VIH Figure 15. Transient Input/Output Reference Waveform for Vcc=UkO.5V (Standard Testing Configuration) Test Confi N uration Ca acitance Loadin Value DEVICE UNDEq TEST CL Includes Jib Capacitance 0 OUT Figure 16. Transient Equivalent Load Circuit Testing Rev. 1.9 SHARI= LHF16KA4 -- - 34 5.2.3 DC CHARACTERISTICS DC Characteristics VCCZ5V Symbol `Ll `LO Parameter Input Load Current Output Leakage Current Vcc Standby Current Notes 1 1 1,396 TYP- Max. *l *lO Unit IJA IJA CIA Test Conditions V,,=VccMax. V,,=Vcc or GND ;~";vccMa* or GND =Vcc CMOS Inputs V,,=V,,Max. CE#=RP#=V,,i0.2V TTL Inputs V,,=V,,Max. CE#=RP#=V,,, RP#=GND*O.2V louT(STS)=OmA CMOS Inputs Vcc=VccMax. CE#=GND f=8MHz, louT=OmA TTL Inputs Vcc=VccMax., CE#=V,, f=8MHz, lo,,,=OmA v,,=5.ov~o.5v `cc, 25 100 2 4 mA IJA mA V,, Deep Power-Down 4 Current V,, Read Current `CCR `CCD 1 156 15 50 65 mA `ccw `CC, `ccws II;cFs `PPS lnnn `PPD IPPW `PPE `PPWS IppFs Vcc Write Current ((Multi) W/B Write or Set Block Lock Bit) V,, Erase Current (Block Erase, Full Chip Erase, Clear Block Lock Bits) V,, Write or Block Erase Suspend Current VP, StandbyCurrent V&Read Current VP, Deep Power-Down Current VP, Write Current ((Multi) W/B Write or Set Block Lock Bit) VP, Erase Current (Block Erase, Full Chip Erase, Clear Block Lock Bits) VP, Write or Block Erase , Suspend Current 1,7 35 1,7 30 mA mA mA IJA PA vpp=5.ov*o.5v 12 1 1 1 1,7 1 *2 10 *15 200 CE#=V,, V,,IV,, VPP>VCC 10 0.1 5 80 PA mA RP#=GNDk0.2V vpp=5.ov*o.5v 1,7 40 mA IJA vpp=5.ov+o.5v 1 10 200 VPP=VPPHl I Rev. 1.9 SHARI= LHFlGKA4 -. DC Characteristics Symbol v,, Parameter Input Low Voltage Input High Voltage Output Low Voltage `OH1 VOH2 35 Notes 7 7 397 397 3,7 (Continued) Vcc=5V Min. ( Max. -0.5 0.8 2.0 Vcc +0.5 n AK ".-tJ Unit v V \I " Test Conditions Output High Voltage u-w Output High Voltage (CMOS) 2.4 0.85 Vcc Vcc -0.4 V V v Vcc=VccMin. loL=5.8mA Vcc=V,,Min. I,,=-2SmA Vcc=VccMin. IoH=-2.!%lA Il,,=V,oMin. m=-l OOuA VP, Lockout during Normal 1.5 r-v -/Operations I 4v7 I VPPH1 ' VP, during Write or Erase 4.5 5.5 V Operations v, KO Vc, Lockout Voltage 2.0 V IOTES: All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and TA=+25"C. !I ICCWS and `CCES are specified with the device de-selected. If read or byte written while in erase suspend mode, the device's current draw is the sum of I,,,, or IccEs and I,,, or lccw, respectively. I. Includes STS. . Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when VpplVppLK, and not guaranteed in the range between VPPLk(max.) and VppH, (min.) and above VppH, (max.). I. Automatic Power Savings (APS) reduces typical lo,, to 1 mA at 5V Voo in static operation. i. CMOS inputs are either Vccf0.2V or GNDkO.2V. TTL inputs are either VI, or Vi,. `. Sampled, not 100% tested. `PPLK I I Rev. 1.9 SHARI= LHF16KA4 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(`) 36 Sym. 1 Vcc=SVdL5V, 5VkO.25V, TA=O"C to +70X Vcc=5V+Q.25V LH28F16OS5-L70@) Versiond4) v~,r.=5v*o.5v Parameter 1 Notes Min. 1 Max. LH28Fi 6OS5-L80@) Min. 1 Max. Unit NOTES: 1. See AC input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELov-&ov after the falling edge of CE# without impact on t,LQv. 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). 3. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics. 3. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. Rev. 1.9 SHARP LHFlGKA4 37 Device Address Selection Address rc VIH Stable kVAV k CE#(E) ML VIH OE#(G) ML WE#(W) VIL VOH DATA( D/Q) VOL kc RP#(P) ML NOTE: CE# isdefined as the latter of CEO# and CE,# going Low or the first of CEo# or CE1# going High. Figure 17. AC Waveform for Read Operations Rev. 1.9 SHARI= .Device Address Selection Address Stable LHFlGKA4 38 VIH OE#(G) WL {VlH tFLClV=tAVQV BYTE#(F) VIL l . ..s*..*.- VOH DATA D/Cl) PQo- &l 7) VOL HIGH Z Data Output ::::::::::$i?& HIGH Z VOH DATA( D/Q) PQdQd VOL HIGH Z NOTE: CE# is defined as the latter of CEO# and CE,# going Low or the first of CEo# or CE,# going High. Figure 18. BYTE# Timing Waveforms Rev. 1.9 LHF16KA4 6.2.5 AC CHARIicTERISTICS - WRITE OPERATIONS(`) 39 Sym. tavnv tPHWL Vcc=5VdMV, 5kO.25V, T,,=O"C to +70X Vcc=5V*0.25V LH28F16OS5-L70@) v~~=5v*o.5v Versions@) 1 Notes Min. 1 Max. Parameter I 70 1Write Cycle Time High Recovery to WE# Going 1CE# Setup to ' 1Vpp Setup to W 1Data Setup to W 1Data Hold from WE# High LH28Fl 60S5-L80(7) Min. 1 Max. 80 Unit ns tF, ,,,,, tvpww tnvwcr &,,-,Y tWHR, twHn, bWl taVSL WE# High to Sl Write Recovery before Read VP,, Hold from Valid SRD, STS High Z WP# V Hold from Valid SRD, STS , I llLJlI 2,4 2,4 I I 0 0 0 I I 0 0 0 I I ns ns ns Uinh L 71H NOTES: 1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A,, and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. Vpp should be held at VppH, until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combkrations). 6. See Transient Input/Output Refecence Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. Rev. 1.9 SHARI= LHFl6KA4 40 #--I----ADDRESSES(A) 1 2 3 4 5 6 CE#(E) OE#(G) WEW') DATA(D/Q) STS(R) WP#(S) RP#(P) ::: VPPHl vPP(v) VPPLK """"""""""""""ru j= NOTES: VIL1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase donfirm or,valid address and data. 4. Automated erase or program delay. 5. Read statusregister data. 6. Write ReadArray command. 7. CE# is defined as the latter of CEo# and CE1# going Low or the first of CEo# or CEI# going High. Figure 19. AC Waveform for WE#-Controlled Write Operations Rev. 1.9 LHFlGKA4 6.2.6 ALTERNAfliiE CE#-CONTROLLED WRITES(l) 41 Vcc=5V*0.5V, 5V*O.25V, TA=O"C to +7O"C Vcc=5Vi0.25V LH28F16OS5-L70@) v~~=5v*osv LH28Fl 60S5-L80(7) NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. VP, should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 7. See Transie,nt Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. Rev. 1.9 SHARP r -- LHFlGKA4 42 ADDRESSES(A) WE#(W) OE#(G) CE#(E) DATA( D/Q) 4 STS(R) WP#(S) NOTES: 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase confirm or.valid address and data. 4. Automated erase or pragram delay. 5. Read status,register data. 6. Write ReadArray command. 7. CE# is defined as the latter of CEO# and CE,# going Low or the first of CEo# or CE1# going High. Figure 20. AC Waveform for CE#-Controlled Write Operations Rev. 1.9 SHARI= .-- - LHFlGKA4 43 6.2.7 RESET OPERATIONS High Z STS(R) VOL VIH RP#(P) VIL (A)Reset High Z STS( R) VOL . VIH tPLRH During Read Array Mode RP#( P) WL \ r bLPH 4 (B)Reset During Block Erase, Full Chip Erase, or Block Lock-Bit Configuretion 5V VIL VIH I t5VPH . I I- (Multi) Word/Byte Write vcc RP#(P) I VIL (C)Vcc Power Up Timing Figure 21. AC Waveform for Reset Operation Reset AC Specifications. Symbol tPLPH tPLRH I. Vn,=5V Parameter Notes Min. 100 12 13.1 Max. Unit ns IJS tG"pH 3 100 ns 1 UOTES: I. If RP# is asserted while a block erase, full chip erase, (multi)-word/byte write or block lock-bit configuration operation is not executing, the reset will complete within loons. !. A reset time, tPHQv, is required from the latter of STS going High Z or RP# going high until outputs are valid. 3. When the device power-up, holding RP# low minimum 100ns is required after Vcc has been in predefined range and also has been in stable there. RP# Pulse Low Time (If RP# is tied to Voc, this specification is not applicable) RP# Low to Reset during Block Erase, Full Chip Erase, (Multi) Word/Byte Write or Block Lock-Bit Configuration Vcc at 4.5V to RP# High Rev. 1.9 SHARP 6.2.8 LHFlGKA4 44 WRITE AND BLOCK BLOCK EFiiSE, FULL CHIP ERASE, (MULTI) WORD/BYTE LOCK-BIT CONFIGURATION PERFORMANCE@) t WKM Set Block Lock-Bit Time tfH(J"g t WI-K&M Clear Block Lock-Bits Time tFHn"d 2 2 9.24 0.34 5.6 9.4 120 10 7 13.1 IJS S `WHnHl Write Suspend Latency Time to Read f&qqRH, pHnr-f2 FHRH? IJS LJS Erase Suspend Latency Time to Read NOTES: 1. Typical values measured at TA=+25"C and nominal voltages. Assumes corresponding block lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. Rev. 1.9 SHARI= _-- - LHFlGKA4 45 ADDITIONAL ,l Ordering INFORMATION Information Product line designator for all SHARP Flash products I I I IL/H~2181FI1/6/O/S15~H1/NSI-/L17lO~ u L-rl Device Density 160 = 16-Mbit PArchitecture S = Regular Block Power Supply Type 5 = Smart 5 Technology Operating Temperature Blank = 0C - +7O"C :,,1 H = -40C - +85"C Access Speed (ns) 70:70ns (5V,3OpF), 80ns (5V) 10: 1OOns(5V) Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend) NS = 56-Lead SSOP B = 64-Ball CSP D = 64-Lead SDIP Jption 1 Order Code LH28F160S5NS-L70 Valid Operational v~~=5v*o.5v 1OOpF load, TTL l/O Levels LH28F16OS5L80 Combinations Vcc=5V*0.25V 3OpF load, 1.5V I/O Levels LH28F160S5-L70 .I' Rev. 1.9 SHARI= LHF16KA4 Flash memory LI@XXKXX family Noises having generated Such noises, To protect operating appropriate: 1) Protecting Setting operation into, section). By controlling For further (See chapter WPSt, desired information 4.12 and 4.13.) through Vpp voltage), write operation on the Allblocksare refer RP# power up and power down sequence such as voltage memory is- disabled, write protecting all on the flash refer lockedandthedata intheblocksarecompletely (See chapter 6.2.3. > blocks can be locked/unlocked block bit, through refer the software. on. I on setting/resetting to the specificati data in specific block a level Data Protection the limit conditions specified in the specification may be interpreted may be as false systems designs, as 46 exceeding operating under specific on some systems. when induced onto WE#signal the data stored or power supply, commands, caus ing undesired with the flash memory updat ing. in the flash memory against unwanted overwriting, write protect memory should have the following the lock bit for example, of the desired on that block. block and pul ling WP# low d isab `les the writing the flash memory space can be divided By using this feature, section) and data section(unlocked the program section(locked, 2) Data protection When the level flashmemory write protected. of Vpp is lower than VPPLK (lockout is disabled. voltage, For the lockout 3) Data protection transition, blocks. write to the specification. through operation When the RP# is kept low during For the detai Is of RP# control, to the specification. (See chapter 5.6 and 6.2.7.) Rev 1.9 SHARP LHF16KA4 -- - 47 LH28F16OSXX-LXX Flash MEMORY ERRATA 1. Multi Word/Byte Write Operations PROBLEM; When two planesof 32-byte pagebuffer are both in full and first buffer data are being written to the flash array, the extendedstatusregisterbit XSR.7 may be erroneouslyset to "l", which indicates the Multi Word/Byte Write command is available. WORKAROUND (1) U8e One PageBuffer After writing the data by the Multi Word/Byte Write command, the statusregister must be read to check the bit SR.7. At this point, the device is in read statusregister mode whether the Read Status Register command is written or not. After the status register bit SR.7 is set to "l", the next Multi Word/Byte Write command will be available. (2) Use Two PageBuffers After writing the data in two planesby the Multi Word/Byte Write command, the statusregistermust be readto check the bit SR.7.At this point, the device is in readstatusregistermode whether the Read StatusRegistercommand is written or not. After the statusregisterbit SR.7 is setto "l", the next Multi Word/Byte Write command will be available. SHARP .-- - LHF16KA4 48 LH28Fl6OSXX-LXX Flash MEMORY ERRATA Use One Page Buffer Multi Command Sequence Write E8H + I Read XSR I Use Two Page Buffers .,.' No Multi Word/Byte Write Command Sequence Write Buffer Data, Device Address Full Status check if desired 1 SHARP _- RELATED DOCUhiEkT Document No. AP-#l-SD-E AP-006-P-r-E INFORMATIOti') Document Name FlashMemory Family Software Drivers Data Protection Method of SHARP Flash Memory I--AP-O07SW-E I RP#, Vpp Electric Potential Switching Circuit -1 NOTE : 1. International customers should contact their local SHARP or distribution sales o5ce. SHARI= IPRELlh,llNARy SEE DETAIL A PIG. XASX PLAUE DETAIL A 3% i ME i SSOP56-P-600 `I - K {Yk LEAD FINISH 4m MAWINGNO. i AA2021 UNIT / TIN-LEAC M%$ l7Xir 1h?-:iM%ft, 4 ~2Z?#~dtt4 D i PLATING NOTE Plastic body dimensions do not include of resin. [ j mm burr |
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