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INTEGRATED CIRCUITS
DATA SHEET
P83C524; P80C528; P83C528 8-bit microcontrollers
Product specification File under Integrated Circuits, IC20 1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 10 11 11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 12 12.1 12.2 13 13.1 13.2 13.2.1 13.3 14 14.1 14.2 14.3 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION General Instruction Set Execution MEMORY ORGANIZATION Program Memory Internal Data Memory Addressing I/O FACILITIES TIMERS/COUNTERS Timer 0 and Timer 1 Timer/Counter Mode Control register (TMOD) Timer/Counter Control Register (TCON) Timer 2 Timer 2 Control Register (T2CON) Capture Mode Automatic Reload Mode Baud Rate Generator Mode Watchdog Timer T3 SERIAL PORT (UART) Serial Port Control Register (SCON) SM0 and SM1 operating modes (SCON) BIT-LEVEL I2C INTERFACE I2C Interrupt Register (S1INT) Single-bit Data Register with I2C Auto-clock (S1BIT) Reading or Writing the S1BIT SFR Control and Status Register for the I2C-bus (S1SCS) INTERRUPT SYSTEM Interrupt Enable Register (IE) Interrupt Priority Register (IP) Interrupt Vectors 15 15.1 15.2 15.3 15.4 16 17 17.1 18 19 20 21 21.1 21.2 22 23 24 25 25.1 26 27 27.1 27.2 27.2.1 27.2.2 27.3 27.3.1 27.3.2 27.3.3 28 29 30
P83C524; P80C528; P83C528
IDLE AND POWER-DOWN OPERATION Power Control Register (PCON) Idle Mode Power-down Mode Wake-up from Power-down Mode OSCILLATOR CIRCUIT RESET CIRCUIT Power-on reset INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS AC Characteristics 16 MHz version AC Characteristics 24 MHz version I2C CHARACTERISTICS (BIT-LEVEL) XTAL1 CHARACTERISTICS SERIAL PORT CHARACTERISTICS TIMING DIAGRAMS Timing symbol definitions PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints PLCC and QFP Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Dec 15
2
Philips Semiconductors
Product specification
8-bit microcontrollers
1 FEATURES 2
P83C524; P80C528; P83C528
GENERAL DESCRIPTION
* 80C51 CPU * 32 kbytes on-chip ROM, expandable externally to 64 kbytes Program Memory address space * P83C524: - 16 kbytes on-chip ROM, expandable externally from 32 kbytes to 64 kbytes Program Memory address space (address space 16 k to 32 k not usable) * P80C528: - ROMless version of P83C528 * P83C528: - 32 kbytes on-chip ROM, expandable externally from 32 kbytes to 64 kbytes Program Memory address space * EPROM versions are available: see separate data sheet P87C524 and P87C528 * 512 bytes on-chip RAM, expandable externally to 64 kbytes Data Memory address space * Four 8-bit I/O ports * Full-duplex UART compatible with the standard 80C51 and the 8052 * Two standard 16-bit timer/counters * An additional 16-bit timer (functionally equivalent to the timer 2 of the 8052) * On-chip Watchdog Timer (WDT) with an own oscillator * Bit-level I2C-bus hardware serial I/O Port * 7-source and 7-vector interrupt structure with 2 priority levels * Up to 3 external interrupt request inputs * Two programmable power reduction modes (Idle and Power-down) * Termination of Idle mode by any interrupt, external or WDT (watchdog) reset * Wake-up from Power-down by external interrupt, external or WDT reset * ROM code protection * XTAL frequency range: 3.5 MHz to 16 MHz and 3.5 MHz to 24 MHz * All packaging pin-outs fully compatible to the standard 8051/8052.
The P83C524 and P83C528 single-chip 8-bit microcontrollers are manufactured in an advanced CMOS process and are derivatives of the PCB80C51 microcontroller family. These devices provide architectural enhancements that make them applicable in a variety of applications in general control systems, especially in those systems which need a large ROM and RAM capacity on chip. The P83C524 and P83C528 contain a non-volatile 16 k x 8 respectively 32 k x 8 read-only program memory, a volatile 512 bytes x 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 8052), a multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and bit-level I2C-bus), a watchdog timer (WDT) with a separate oscillator, an on-chip oscillator and timing circuits. For systems that require extra capability, the P83C524 and P83C528 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The P83C524 and P83C528 have the same instruction set as the PCB80C51 which consists of over 100 instructions: 49 one-byte, 46 two-byte and 16 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 750 ns and 40% in 1.5 s. Multiply and divide instructions require 3 s.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
3 QUICK REFERENCE DATA SYMBOL PARAMETER
P83C524; P80C528; P83C528
CONDITION
MIN.
MAX.
UNIT
P83C524, P80C528, P83C528 (see characteristics tables for extended temperature range versions) VDD IDD IID IPD Ptot Tstg Tamb 4 supply voltage range supply current: operating modes 16 MHz supply current: Idle mode 16 MHz supply current: Power-down mode total power dissipation storage temperature range operating ambient temperature range VDD = 5.5 V, fCLK = 16 MHz VDD = 5.5 V, fCLK = 16 MHz 2V VPD VDD max. 4.5 - - - - -65 -40 5.5 33 6 100 1 +150 +85 V mA mA A W C C
ORDERING INFORMATION PACKAGE NAME DESCRIPTION VERSION TEMPERATURE RANGE (C) FREQ. (MHZ)
EXTENDED TYPE NUMBER ROMless P80C528EBP P80C528EFP P80C528IBP P80C528IFP P80C528EBA P80C528EFA P80C528IBA P80C528IFA P80C528EBB P80C528EFB P80C528IBB P80C528IFB ROM P83C524EBP P83C524EFP P83C524IBP P83C524IFP P83C524EBA P83C524EFA P83C524IBA P83C524IFA P83C524EBB P83C524EFB P83C524IBB P83C524IFB
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
0 to +70 -40 to +85 0 to +70 -40 to +85
3.5 to 16 3.5 to 24 3.5 to 16 3.5 to 24 3.5 to 16 3.5 to 24
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2
0 to +70 -40 to +85 0 to +70 -40 to +85
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
0 to +70 -40 to +85 0 to +70 -40 to +85
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
0 to +70 -40 to +85 0 to +70 -40 to +85
3.5 to 16 3.5 to 24 3.5 to 16 3.5 to 24 3.5 to 16 3.5 to 24
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2
0 to +70 -40 to +85 0 to +70 -40 to +85
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
0 to +70 -40 to +85 0 to +70 -40 to +85
1997 Dec 15
4
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
EXTENDED TYPE NUMBER P83C528EBP P83C528EFP P83C528IBP P83C528IFP P83C528EBA P83C528EFA P83C528IBA P83C528IFA P83C528EBB P83C528EFB P83C528IBB P83C528IFB
PACKAGE NAME DIP40 DESCRIPTION plastic dual in-line package; 40 leads (600 mil) VERSION SOT129-1
TEMPERATURE RANGE (C) 0 to +70 -40 to +85 0 to +70 -40 to +85
FREQ. (MHZ) 3.5 to 16 3.5 to 24 3.5 to 16 3.5 to 24 3.5 to 16 3.5 to 24
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2
0 to +70 -40 to +85 0 to +70 -40 to +85
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
0 to +70 -40 to +85 0 to +70 -40 to +85
1997 Dec 15
5
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frequency reference XTAL2 XTAL1 counters T0 T1 T2 T2EX RST RAM OSCILLATOR AND TIMING PROGRAM PROGRAM MEMORY MEMORY (32 K x 8 ROM (32 K x 8 ROM/ or 16 K x 8 ROM) EPROM) DATA MEMORY (256 x 8 RAM) AUX - RAM DATA MEMORY (256 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS 16-BIT TIMER WATCHDOG TIMER CPU P83C524 P80C528 P83C528 PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT
5
Philips Semiconductors
8-bit microcontrollers
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
6
P83C524; P80C528; P83C528
internal interrupts
64K-BYTE BUS EXPANSION CONTROL
BIT-LEVEL I 2C INTERFACE
PROGRAMMABLE I/O
MBC455
INT0 INT1 external interrupts
control
parallel ports, address/data bus and I/O pins
serial in
serial out
SDA
SCL
shared with Port 3
Product specification
Philips Semiconductors
Product specification
8-bit microcontrollers
6 FUNCTIONAL DIAGRAM
P83C524; P80C528; P83C528
VSS
handbook, full pagewidth
VDD
RST
XTAL1 XTAL2
Port 0
address and data bus
EA T2 PSEN P83C524 P80C528 P83C528 P83C528 Port 1 T2EX
ALE
SCL SDA RXD / data TXD / clock INT0 alternative functions INT1 T0 T1 WR RD
MBC454 - 1
Port 3
Port 2
address bus
Fig.2 Functional diagram.
1997 Dec 15
7
Philips Semiconductors
Product specification
8-bit microcontrollers
7 7.1 PINNING INFORMATION Pinning
P83C524; P80C528; P83C528
handbook, halfpage
T2 P1.0 1 T2EX P1.1 2 P1.2 P1.3 P1.4 P1.5 SCL P1.6 SDA P1.7 RST 3 4 5 6 7 8 9 P83C524 P80C528 P83C528 P83C528
40 VDD 39 P0.0 AD0 38 P0.1 AD1 37 P0.2 AD2 36 P0.3 AD3 35 P0.4 AD4 34 P0.5 AD5 33 P0.6 AD6 32 P0.7 AD7 31 EA 30 ALE 29 PSEN 28 P2.7 A15 27 P2.6 A14 26 P2.5 A13 25 P2.4 A12 24 P2.3 A11 23 P2.2 A10 22 P2.1 A9 21 P2.0 A8
MBC453
RXD / data P3.0 10 TXD / clock P3.1 11 INT0 P3.2 12 INT1 P3.3 13 T0 P3.4 14 T1 P3.5 15 WR P3.6 16 RD P3.7 17 XTAL2 18 XTAL1 19 VSS 20
Fig.3 Pin configuration DIP40 (SOT129-1).
1997 Dec 15
8
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
P1.1 / T2EX
43 P0.0 / AD0
42 P0.1 / AD1
41 P0.2 / AD2 35
handbook, full pagewidth
44
43
42
37
36
41
39
P1.5
7
40
38
34
40 P0.3 / AD3
P1.0 / T2
44 V DD
P1.4
P1.3
P1.2
6
5
4
3
2
1
n.c.
39 P0.4 / AD4 38 P0.5 / AD5 33 37 32 P0.6 / AD6 36 31 P0.7 / AD7 P83C524 P80C528 P83C528 P83C528 35 30 EA 34 29 n.c. 33 28 ALE 32 27 PSEN 31 26 P2.7 / A15 30 25 P2.6 / A14 29 24 P2.5 / A13 23 MBC452 WR / P3.6 18 12 RD / P3.7 19 13 XTAL2 20 14 XTAL1 21 15 VSS 22 16 n.c. 17 23 P2.0 / A8 24 18 P2.1 19 25 / A9 P2.2 / 20 26 A10 P2.3 / 21 27 A11 P2.4 / 22 28 A12
SCL / P1.6 8 1 SDA / P1.7 9 2 RST 10 3 RXD / data / P3.0 4 11 n.c. 12 5 TXD / clock / P3.1 13 6 INT0 / P3.2 14 7 INT1 / P3.3 15 8 T0 / P3.4 16 9 17 T1 / P3.5 10 11
Fig.4 Pin configuration QFP44 (SOT307-2).
1997 Dec 15
9
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
P1.1 / T2EX
43 P0.0 / AD0
42 P0.1 / AD1
41 P0.2 / AD2
handbook, full pagewidth
P1.5
7
40 P0.3 / AD3
P1.0 / T2
44 V DD
P1.4
P1.3
P1.2
6
5
4
3
2
1
n.c.
39 P0.4 / AD4 38 P0.5 / AD5 37 P0.6 / AD6 36 P0.7 / AD7 P83C524 P80C528 P83C528 P83C528 35 EA 34 n.c. 33 ALE 32 PSEN 31 P2.7 / A15 30 P2.6 / A14 29 P2.5 / A13
MBC452
SCL / P1.6 8 SDA / P1.7 9 RST 10 RXD / data / P3.0 11 n.c. 12 TXD / clock / P3.1 13 INT0 / P3.2 14 INT1 / P3.3 15 T0 / P3.4 16 T1 / P3.5 17
WR / P3.6 18
RD / P3.7 19
XTAL2 20
XTAL1 21
VSS 22
n.c. 23
P2.0 / A8 24
P2.1 / A9 25
P2.2 / A10 26
P2.3 / A11 27
Fig.5 Pin configuration PLCC44 (SOT187-2).
1997 Dec 15
10
P2.4 / A12 28
Philips Semiconductors
Product specification
8-bit microcontrollers
7.2 Pin description
P83C524; P80C528; P83C528
Table 1
Pin description for P83C524, P80C528 and P83C528; see note 1 PIN DESCRIPTION SOT 129-1 SOT 187-2 SOT 307-2 2-9 (1 n.c.) 1-3, 40-44 (39 n.c.) Port 1: 8-bit quasi-bidirectional I/O Port. Port 1 can sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs without external pull-ups, except P1.6 and P1.7 which have open drain outputs. Port 1 alternative functions: P1.0 P1.1 P1.6 P1.7 Timer/event counter 2 external event counter input (falling edge triggered) Timer/event counter 2 capture/reload trigger or external interrupt 2 input (falling edge triggered) I2C-bus Serial Port clock line I2C-bus Serial Port data line.
SYMBOL P1.0-P1.7 1 to 8
T2 T2EX SCL SDA RST
1 2 7 8 9
2 3 8 9 10
40 41 2 3 4
RESET: a HIGH level on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits power-on reset using only a capacitor connected to VDD. After a WDT overflow this pin is pulled HIGH while the internal reset signal is active. Port 3: 8-bit quasi-bidirectional I/O Port with internal pull-ups. Port 3 can sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs without external pull-ups. Port 3 alternative functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Serial Port data input (asynchronous) or data input/output (synchronous) Serial Port data output (asynchronous) or clock output (synchronous) external interrupt 0 or gate control input for timer/event counter 0 external interrupt 1 or gate control input for timer/event counter 1 external input for timer/event counter 0 external input for timer/event counter 1 external data memory write strobe external data memory read strobe.
P3.0-P3.7 10-17
11, 13-19 (12 n.c.)
5, 7-13 (6 n.c.)
RXD/data
10
11 13 14 15 16 17 18 19
5 7 8 9 10 11 12 13
TXD/clock 11 INT0 INT1 T0 T1 WR RD 12 13 14 15 16 17
The generation or use of a Port 3 pin as an alternative function is carried out automatically by the P83C528 provided the associated Special Function Register (SFR) bit is set HIGH. XTAL2 18 20 14 Crystal input 2: output of the inverting amplifier that forms the oscillator. This pin left open-circuit when an external oscillator clock is used (see Figures 22 and 23).
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
PIN SYMBOL SOT 129-1 SOT 187-2 SOT 307-2 XTAL1 19 21 15 Crystal input 1: input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external oscillator clock signal when an external oscillator is used (see Figures 22 and 23). Ground: circuit ground potential. Port 2: 8-bit quasi-bidirectional I/O Port with internal pull-ups. During access to external memories (RAM/ROM) that use 16-bit addresses (MOVX @DPTR) Port 2 emits the high-order address byte (A8 to A15). Port 2 can sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs without external pull-ups. Program Store Enable output: read strobe to the external program memory via Port 0 and Port 2. It is activated twice each machine cycle during fetches from external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs. It can drive CMOS inputs without external pull-ups. Address Latch Enable output: latches the LOW byte of the address during access to external memory in normal operation. It is activated every six oscillator periods except during an external data memory access. ALE can sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external pull-up. External Access input: when during RESET, EA is held at a TTL HIGH level, the CPU executes out of the internal program ROM, provided the program counter is less than 32768. When EA is held at a TTL LOW level during RESET, the CPU executes out of external program memory via Port 0 and Port 2. EA is not allowed to float. Port 0: 8-bit open drain bidirectional I/O Port. It is also the multiplexed low-order address and data bus during accesses to external memory (AD0 to AD7). During these accesses internal pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs. Power supply: +5 V power supply pin during normal operation, Idle mode and Power-down mode. DESCRIPTION
VSS P2.0-P2.7
20 21-28
22 24-31 (23 n.c.)
16 18-25 (17 n.c.)
PSEN
29
32
26
ALE
30
33
27
EA
31
35 (34 n.c.)
29 (28 n.c.)
P0.0-P0.7
32-39
36-43
30-37
VDD Note
40
44
38
1. To avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD +0.5 V or lower than VSS -0.5 V respectively.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
8 8.1 FUNCTIONAL DESCRIPTION General 9.1
P83C524; P80C528; P83C528
Program Memory
The P83C524, P80C528 and P83C528 are stand-alone high-performance microcontrollers designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications. In addition to the 80C51 standard functions, the devices provide a number of dedicated hardware functions for these applications. The P83C524 and P83C528 are control-oriented CPUs with on-chip program and data memory. They can be extended with external program memory up to 64 kbytes. They can also access up to 64 kbytes of external data memory. For systems requiring extra capability, the P83C524 and P83C528 can be expanded using standard memories and peripherals. The P83C524, P80C528 and P83C528 have two software selectable modes of reduced activity for further power reduction: Idle and Power-down. The Idle mode freezes the CPU while allowing the RAM, timers, serial ports and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative except the WDT if it is enabled. The Power-down mode can be terminated by an external reset, a WDT overflow, and in addition, by either of the two external interrupts. 8.2 Instruction Set Execution
The program memory address space of the P83C528 comprises an internal and an external memory portion. The P83C528 has 32 kbyte of program memory on-chip. The program memory can be externally expanded up to 64 kbyte. If the EA pin is held HIGH, the P83C528 executes out of the internal program memory unless the address exceeds 7FFFH. Locations 8000H through 0FFFFH are then fetched from the external program memory. If the EA pin is held LOW, the P83C528 fetches all instructions from the external program memory. Fig.6 illustrates the program memory address space. By setting a mask programmable security bit the ROM content is protected i.e. it cannot be read out by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during RESET and is 'don't care' after RESET. This implementation prevents reading from internal program code by switching from external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to a logical one. If the security bit has been set to a logical 0 there are no restrictions for the MOVC instructions.
The P83C524, P80C528 and P83C528 use the powerful instruction set of the 80C51. Additional SFRs are incorporated to control the on-chip peripherals. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 16 MHz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 s. Multiply and divide instructions execute in 3 s (see Chapter 18). 9 MEMORY ORGANIZATION
handbook, halfpage
64 K
EXTERNAL
32768
The central processing unit (CPU) manipulates operands in three memory spaces; these are the 64 kbyte external data memory (of which the lower 256 bytes reside in the internal AUX-RAM), 512 byte internal data memory (consisting of 256 bytes standard RAM and 256 bytes AUX-RAM) and the 64 kbyte internal and external program memory.
32767
32767
16383
(1)
INTERNAL (EA = 1)
EXTERNAL (EA = 0)
0
0 PROGRAM MEMORY
MBC456 - 1
(1) Only for P83C524.
Fig.6 Program Memory Address Space.
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Philips Semiconductors
Product specification
8-bit microcontrollers
Table 2
P83C524; P80C528; P83C528
Internal and external program memory access with security bit set INSTRUCTION ACCESS TO INTERNAL PROGRAM MEMORY YES NO ACCESS TO EXTERNAL PROGRAM MEMORY YES YES
MOVC in internal program memory MOVC in external program memory 9.2 Internal Data Memory
The internal data memory is divided into three physically separated parts: 256 byte of RAM, 256 byte of AUX-RAM, and a 128 byte special function area (SFR). These parts can be addressed as follows (see Table 3 and Fig.11): * RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. * RAM 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected register bank. * AUX-RAM 0 to 255 is indirectly addressable as the external data memory locations 0 to 255 with the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. When executing from internal program memory, an access to AUX-RAM 0 to 255 will not affect the ports P0, P2, P3.6 and P3.7. * the SFRs can only be addressed directly in the address range from 128 to 255.
An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 80C51 structure, i.e. with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals (see Figures 7, 8, 9 and 10). Note that the external data memory cannot be accessed with R0 and R1 as address pointer. Fig.11 shows the internal and external data memory address space. Fig.12 shows the Special Function Register (SFR) memory map. Four 8-bit register banks occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-bit register banks reside in the SFR address space.
Table 3
Internal data memory access LOCATION ADDRESSED DIRECT and INDIRECT INDIRECT only INDIRECT only with MOVX DIRECT only
RAM 0 to 127 RAM 128 to 255 AUX-RAM 0 to 255 Special Function Register (SFR) 128 to 255
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Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
one machine cycle S1 S2 S3 S4 S5 S6 S1 S2
one machine cycle S3 S4 S5 S6
ALE
PSEN
RD
WR
P2
P2 OUT
P0
P0 OUT
MBC457
a. Without a MOVX.
handbook, full pagewidth
cycle 1 S1 S2 S3 S4 S5 S6 S1 S2
cycle 2 S3 S4 S5 S6
ALE
PSEN
RD
WR
P2
P2 OUT
P0
P0 OUT
MBC458
b. With a MOVX to the AUX-RAM (read and write).
Fig.7 Internal program memory execution.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
cycle 1 S1 S2 S3 S4 S5 S6 S1 S2
cycle 2 S3 S4 S5 S6
ALE
PSEN
RD
WR
P2
P2 OUT
DPH OUT
P2 OUT
P0
P0 OUT
DPL OUT
DATA IN
MBC459
a. With a MOVX to the External Data Memory (read).
handbook, full pagewidth
cycle 1 S1 S2 S3 S4 S5 S6 S1 S2
cycle 2 S3 S4 S5 S6
ALE
PSEN
RD
WR
P2
P2 OUT
DPH OUT
P2 OUT
P0
P0 OUT
DPL OUT
DATA OUT
MBC460
b. With a MOVX to the External Data Memory (write).
Fig.8 Internal program memory execution (continued).
1997 Dec 15
16
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
one machine cycle
handbook, full pagewidth
one machine cycle S5 S6 S1 S2 S3 S4 S5 S6
S1 ALE
S2
S3
S4
PSEN
RD
WR
P2
PCH OUT
PCH OUT
PCH OUT
PCH OUT
PCH OUT
P0
INST IN
PCL OUT
INST IN
PCL OUT
INST IN
PCL OUT
INST IN
PCL OUT
MBC461
a. Without a MOVX.
cycle 1
handbook, full pagewidth
cycle 2 S4 S5 S6 S1 S2 S3 S4 S5 S6
S1 ALE
S2
S3
PSEN
RD
WR
P2
PCH OUT
PCH OUT
ADDRH OUT
PCH OUT
P0
INST IN
PCL OUT
INST IN
ADDRL OUT (read)
PCL OUT
P2
PCH OUT
PCH OUT
ADDRH OUT
PCH OUT
P0
INST IN
PCL OUT
INST IN
ADDRL OUT (write)
DATA OUT
PCL OUT
MBC462
b. With a MOVX to the AUX-RAM (read and write).
Fig.9 External program memory execution.
1997 Dec 15
17
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
cycle 1 S1 S2 S3 S4 S5 S6 S1 S2 S3
cycle 2 S4 S5 S6
ALE
PSEN
RD
WR
P2
PCH OUT
PCH OUT
DPH OUT
PCH OUT
P0
INST IN
PCL OUT
INST IN
DPL OUT
DATA IN
PCL OUT
MBC463
a. With a MOVX to the External Data Memory (read).
handbook, full pagewidth
cycle 1 S1 S2 S3 S4 S5 S6 S1 S2 S3
cycle 2 S4 S5 S6
ALE
PSEN
RD
WR
P2
PCH OUT
PCH OUT
DPH OUT
PCH OUT
P0
INST IN
PCL OUT
INST IN
DPL OUT
DATA OUT
PCL OUT
MBC464
b. With a MOVX to the External Data Memory (write).
Fig.10 External program memory execution (continued).
1997 Dec 15
18
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
SHARED ADDRESS LOCATION FF FF FF FFFF
handbook, full pagewidth
UPPER 128 BYTES INTERNAL RAM
SPECIAL FUNCTION REGISTERS
AUX - RAM 256 BYTES
80 7F
80
EXTERNAL DATA MEMORY
LOWER 128 BYTES INTERNAL RAM
00
00 DATA MEMORY register indirect addressing
0100
direct byte addressing
MBC466 - 1
Fig.11 Internal and external data memory address space.
1997 Dec 15
19
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
REGISTER MNEMONIC
BIT MNEMONIC / BIT ADDRESS (HEX)
DIRECT BYTE ADDRESS (HEX)
T3 B ACC S1INT S1BIT SDI/ SDO DF CY D7 SCI/ SCO DE AC D6 CLH DO FO D5 BB DC RSI D4 RBF DB RSO D3 WBF DA OV D2 STR D9 FI D1 ENS D8 P D0 F7 E7 F6 E6 F5 E5 F4 E4 F3 E3 F2 E2 F1 E1 F0 E0
FFH F0H E0H DAH D9H
S1SCS
D8H
PSW TH2 TL2 RCAP2H RCAP2L
D0H CDH CCH CBH CAH
T2CON
TF2 CF --BF B7 EA AF
EXF2 CE PS1 BE B6 ES1 AE
RCLK CD PT2 BD B5 ET2 AD
TCLK CC PS BC B4 ES AC
EXEN2 CB PT1 BB B3 ET1 AB
TR2 CA PX1 BA B2 EX1 AA
C/T2 C9 PT0 B9 B1 ET0 A9
CP/RL2 C8 PX0 B8 B0 EX0 A8
C8H
IP P3
B8H B0H
IE WDCON P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0
A8H A5H
A7
A6
A5
A4
A3
A2
A1
A0
A0H 99H
SM0 9F 97
SM1 9E 96
SM2 9D 95
REN 9C 94
TB8 9B 93
RB8 9A 92
TI 99 91
RI 98 90
98H 90H 8DH 8CH 8BH 8AH 89H
TF1 8F
TR1 8E
TF0 8D
TR0 8C
IE1 8B
IT1 8A
IE0 89
IT0 88
88H 87H 83H 82H 81H
87
86
85
84
83
82
81
80
MBC465 - 1
80H
Fig.12 Special Function Register (SFR) memory map.
1997 Dec 15
20
Philips Semiconductors
Product specification
8-bit microcontrollers
9.3 Addressing
P83C524; P80C528; P83C528
The P83C528 has five modes for addressing: * Register * Direct * Register-Indirect * Immediate * Base-Register plus Index-Register-Indirect. The first three methods can be used for addressing destination operands. Most instructions have a 'destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addresses is as follows: * Register in one of the four 8-bit register banks through Register, Direct or Register-Indirect addressing. * 512 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be addressed directly/indirectly. Bytes 128-255 of internal RAM share their address location with the SFRs and so may only be addressed indirectly as data RAM. Bytes 0-255 of AUX-RAM can only be addressed indirectly via MOVX. * SFR through Direct addressing at address locations 128-255. * External data memory through Register-Indirect addressing. * Program memory look-up tables through Base-Register plus Index-Register-Indirect addressing.
1997 Dec 15
21
Philips Semiconductors
Product specification
8-bit microcontrollers
10 I/O FACILITIES The P83C528 has four 8-bit ports. Ports 0-3 are the same as in the 80C51, with the exception of the additional function of Port 1. Port lines P1.0 and P1.1 may be used as inputs for Timer 2, P1.1 may also be used as an additional (third) external interrupt request input. Port lines P1.6 and P1.7 may be selected as the SCL and SDA lines of Serial Port SIO1 (I2C). Because the I2C-bus may be active while the device is disconnected from VDD, these pins are provided with open drain drivers. Pins P1.6 and P1.7 do not have pull-up devices when used as ports. Ports 0, 1, 2, and 3 perform the following alternative functions: * Port 0: provides the multiplexed low-order address and data bus used for expanding the P83C528 with standard memories and peripherals. * Port 1: pins can be configured individually to provide: external interrupt request input (external interrupt 2); external inputs for Timer/counter 2; SCL and SDA for the I2C interface.
P83C524; P80C528; P83C528
* Port 2: provides the high-order address bus when expanding the P83C528 with external program memory and/or external data memory. * Port 3: pins can be configured individually to provide: external interrupt request inputs (external interrupt 0/1); external inputs for Timer/counter 0 and Timer/counter 1; Serial Port receiver input and transmitter output control-signals to read and write external data memory. Bits which are not used for the alternative functions may be used as normal bidirectional I/O pins. The generation or use of a Port 1 or Port 3 pin as an alternative function is carried out automatically by the P83C528 provided the associated SFR bit is HIGH. Otherwise the port pin is held at a logical LOW level.
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
+5 V
p2 p3 I/O PIN PORT
Q from port latch
n I1
input data read port pin INPUT BUFFER
MLA513
Fig.13 I/O buffers in the P83C528 (Ports 1, 2 and 3 except P1.6 and P1.7).
1997 Dec 15
22
Philips Semiconductors
Product specification
8-bit microcontrollers
11 TIMERS/COUNTERS The P83C528 contains three 16-bit timer/counters, Timer 0, Timer 1 and Timer 2, and one 8-bit timer, the Watchdog Timer T3. Timer 0, Timer 1 and Timer 2 may be programmed to carry out the following functions: * measure time intervals and pulse durations * count events * generate interrupt requests. 11.1 Timer 0 and Timer 1
P83C524; P80C528; P83C528
When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rate generator. With a 16 MHz crystal, the counting frequency of these timer/counters is as follows: * in the timer function, the timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12). * in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz. Both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration. The timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described.
Timers 0 and 1 each have a control bit in TMOD SFR that selects the timer or counter function of the corresponding timer. In the timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 112 of the oscillator frequency. In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Timer 0 and Timer 1 can be programmed independently to operate in one of four modes: Mode 0 8-bit timer/counter with divide-by-32 prescaler Mode 1 16-bit timer/counter Mode 2 8-bit timer/counter with automatic reload Mode 3 Timer 0: one 8-bit timer/counter and one 8-bit timer. Timer 1: stopped.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
11.1.1 Table 4 7 GATE Table 5 BIT TIMER 1 7 GATE TIMER/COUNTER MODE CONTROL REGISTER (TMOD) Timer/Counter Mode Control register (address 89H) 6 TIMER 1 C/T M1 M0 GATE 5 4 3
P83C524; P80C528; P83C528
2 TIMER 0 C/T
1 M1
0 M0
Description of the TMOD bits SYMBOL FUNCTION
Timer 1 gating control: when set, Timer/counter '1' is enabled only while 'INT1' pin is HIGH and 'TR1' control bit is set. When cleared, Timer/counter '1' is enabled whenever 'TR1' control bit is set. Timer or counter selector: cleared for timer operation (input from internal system clock). Set for counter operation (input from 'T1' input pin). operating mode: see Table 6. operating mode: see Table 6.
6 5 4 TIMER 0 3
C/T M1 M0
GATE
Timer 0 gating control: when set, Timer/counter '0' is enabled only while 'INT0' pin is HIGH and 'TR0' control bit is set. When cleared, Timer/counter '0' is enabled whenever 'TR0' control bit is set. Timer or counter selector: cleared for timer operation (input from internal system clock). Set for counter operation (input from 'T0' input pin). operating mode: see Table 6. operating mode: see Table 6.
2 1 0 Table 6 M1 0 0 1 1 1
C/T M1 M0
TMOD M1 and M0 operating modes M0 0 1 0 1 1 FUNCTION 8-bit timer/counter: 'THx' with 5-bit prescaler. 16-bit timer/counter: 'THx' and 'TLx' are cascaded, there is no prescaler. 8-bit autoload timer/counter: 'THx' holds a value which is to be reloaded into 'TLx' each time it overflows. Timer 0: TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer controlled by Timer 1 control bits. Timer 1: Timer/counter 1 stopped.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
11.1.2 Table 7 7 TF1 Table 8 BIT 7 6 5 4 3 2 1 0 TIMER/COUNTER CONTROL REGISTER (TCON) Timer/Counter Control register (address 88H) 6 TR1 5 TF0 4 TR0 3 IE1
P83C524; P80C528; P83C528
2 IT1
1 IE0
0 IT0
Description of the TCON bits SYMBOL TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 FUNCTION Timer 1 overflow flag: set by hardware on timer/counter overflow. Cleared when interrupt is processed. Timer 1 run control bit: set/cleared by software to turn timer/counter ON/OFF. Timer 0 overflow flag: set by hardware on timer/counter overflow. Cleared when interrupt is processed. Timer 0 run control bit: set/cleared by software to turn timer/counter ON/OFF. Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared when interrupt is processed. Interrupt 1 type control bit: set/cleared by software to specify falling edge/LOW level triggered external interrupt. Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared when interrupt is processed. Interrupt 0 type control bit: set/cleared by software to specify falling edge/LOW level triggered external interrupt.
1997 Dec 15
25
Philips Semiconductors
Product specification
8-bit microcontrollers
11.2 Timer 2
P83C524; P80C528; P83C528
Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload register. Like Timer 0 and 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in the T2CON SFR. The timer has three operating modes: 'capture', 'autoload' and 'baud rate generator', which are selected by bits in the T2CON SFR (see Table 9). Table 9 Timer 2 operating modes CP/RL2 0 1 X X TR2 1 1 1 0 16-bit automatic reload 16-bit capture baud rate generator OFF MODE
RCLK + TCLK 0 0 1 X 11.2.1
TIMER 2 CONTROL REGISTER (T2CON)
Table 10 Timer 2 Control register (address C8H) 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2
Table 11 Description of the T2CON bits MNEMONIC TF2 POSITION T2CON.7 FUNCTION Timer 2 overflow flag: set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled, TF2 = 1 (see EXF2). Timer 2 external flag: set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. Receive clock flag: when set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. Transmit clock flag: when set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag: when set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control: a logic 1 starts Timer 2. A logic 0 stops Timer 2. Timer/counter select: 0 = internal timer (OSC/12). 1 = external event counter (falling edge triggered). Capture/reload flag: when set, capture will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overflows or negative transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to reload upon overflow.
EXF2
T2CON.6
RCLK
T2CON.5
TCLK
T2CON.4
EXEN2
T2CON.3
TR2 C/T2 CP/RL2
T2CON.2 T2CON.1 T2CON.0
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
11.2.2 CAPTURE MODE 11.2.4
P83C524; P80C528; P83C528
BAUD RATE GENERATOR MODE
In the capture mode (see Fig.14) there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer/counter which on overflow sets bit TF2 (Timer 2 overflow bit). TF2 can be used to generate an interrupt. If EXEN2 = 1, Timer 2 operates as above, with the added feature that a HIGH-to-LOW transition at the external input T2EX causes the current value in Timer 2 registers (TL2 and TH2) to be captured into registers RCAP2L and RCAP2H, respectively. The HIGH-to-LOW transition of T2EX also causes bit EXF2 in T2CON to be set. EXF2 can be used to generate an interrupt. 11.2.3 AUTOMATIC RELOAD MODE
The baud rate generator mode (see Fig.16) is selected by RCLK = 1 and/or TCLK = 1 in T2CON. Overflows of either Timer 2 or Timer 1 can be used independently for generating baud rates for transmit and receive. The baud rate generation by Timer 1 and/or Timer 2 is used for the Serial Port in Mode 1 and Mode 3. The baud rate generation mode is similar to the automatic reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. The baud rate for the Serial Port in Modes 1 and 3 are determined by Timer 2's overflow rate as follows: Timer 2 overflow rate Baud Rate = ------------------------------------------------------16 Timer 2 can be configured for either 'timer' or 'counter' operation. In timer operation a prescaler divides the oscillator frequency by 2 (by 12 in the previous modes) and the baud rate is given by the formula: oscillator frequency Baud Rate = -----------------------------------------------------------------------------------------------------32 x [ 65536 - (RCAP2H,RCAP2L) ] In this mode an overflow of Timer 2 does not set TF2. If EXEN2 = 1, a HIGH-to-LOW transition at pin T2EX sets EXF2 and can be used to generate an interrupt.
In the automatic reload mode (see Fig.15)there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then a Timer 2 overflow sets TF2 and causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, Timer 2 operates as above, with the added feature that a HIGH-to-LOW transition at the external input T2EX triggers the 16-bit reload and sets EXF2.
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 timer 2 interrupt RCAP2L RCAP2H EXF2
MBC468 - 1
transition detector T2EX PIN control EXEN2
Fig.14 Timer 2 in capture mode.
1997 Dec 15
27
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 reload timer 2 interrupt RCAP2L RCAP2H
transition detector T2EX PIN control EXEN2
EXF2
MBC469 - 1
Fig.15 Timer 2 in automatic reload mode.
handbook, full pagewidth
TIMER 1 overflow 2
(note: divided by 2 not by 12) OSC 2
0
1 SMOD
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS)
1
0 RCLK 16 RX CLOCK
T2 PIN
C/T2 = 1
control TR2 1 0
transition detector T2EX PIN control EXEN2
RCAP2L
RCAP2H "TIMER 2" interrupt (additional external interrupt)
TCLK 16 TX CLOCK
MBC470 - 1
EXF2
Fig.16 Timer 2 in baud rate generator mode.
1997 Dec 15
28
Philips Semiconductors
Product specification
8-bit microcontrollers
11.3 Watchdog Timer T3
P83C524; P80C528; P83C528
inhibited to prevent timing problems due to asynchronous increments of T3. To prevent an overflow of the WDT, the user program has to reload T3 within periods that are shorter than the programmed Watchdog time interval. This time interval is determined by the 8-bit reload value that is written into register T3. [ 256 - ( T3 ) ] x 2048 Watchdog time interval = -----------------------------------------------------------------------on-chip oscillator frequency The advantages of this implementation are: * Only an internal reset connection to the microcontroller core * The Power-down mode and the Watchdog (WDT) function can be used concurrently * The WDT also monitors the XTAL oscillator. In case of a failure the port outputs are forced to a defined High state * Interference will not disable the WDT because it is unlikely that it will force WDCON to A5H * Tolerances of the on-chip oscillator can be adjusted by testing the T3 value and adapting the reload value * The WDT can be enabled and disabled under control of the user software. This gives the possibility to use both the Watchdog function and the Power-down function * The direct address A5H of WDCON and its disable value A5H will not unintentionally be present at a random location in the field of program code, except for immediate data, because the opcode A5H is not used in the instruction set.
The Watchdog Timer (WDT) see Fig.17, consists of an 11-bit prescaler and an 8-bit timer formed by SFR T3. The prescaler is incremented by an on-chip oscillator with a fixed frequency of 1 MHz. The maximum tolerance on this frequency is -50% and +100%. The 8-bit timer increments every 2048 cycles of the on-chip oscillator. When a timer overflow occurs, the microcontroller is reset and a reset-output-pulse of 16 x 2048 cycles of the on-chip oscillator is generated at pin RST. The internal RESET signal is not inhibited when the external RST pin is kept LOW by e.g. an external reset circuit. The RESET signal drives Ports 1, 2 and 3 outputs into the High state and Port 0 into high impedance, no matter if the XTAL-clock is running or not. The WDT is controlled by WDCON SFR with the direct address location A5H. WDCON can be read and written by software. A value of A5H in WDCON halts the on-chip oscillator and clears both the prescaler and Timer T3. After RESET, WDCON contains A5H. Every value other than A5H in WDCON enables the WDT. When the WDT is enabled it runs independent of the XTAL-clock. Timer T3 can be read on the fly. Timer T3 can be written only if WDCON has previously been loaded with 5AH, otherwise T3 and the prescaler are not affected. A successful write operation to T3 also clears the prescaler and clears WDCON. During a read or write operation addressing T3, the output of the on-chip oscillator is
handbook, full pagewidth
IBS
WDCON
11 - BIT PRESCALER
8 - BIT TIMER T3 write read clear
over-flow
5AH
(1)
A5H
(1) clear
clear
input
VDD
ON - CHIP OSCILLATOR WR - T3 halt
R RST VSS
RD - T3 (1) internal RESET
RST
this signal is active if WDCON contains this hex value
MBC471 - 1
Fig.17 Watchdog Timer T3.
1997 Dec 15
29
Philips Semiconductors
Product specification
8-bit microcontrollers
12 SERIAL PORT (UART) The Serial Port is functionally similar to the implementation in the 8052AH, with the possibility of two different baud rates for receive and transmit with Timer 1 and Timer 2 as baud rate generators. It is full duplex, meaning it can receive and transmit simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time the reception of the second byte is complete, one of the bytes will be lost. The Serial Port receive and transmit registers are both accessed as SBUF SFR. Writing to SBUF loads the transmit register, and reading SBUF accesses the physically separate receive register. The Serial Port can operate in one of four modes: Mode 0 serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON SFR. The baud rate is variable. Mode 2 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. For example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is variable.
P83C524; P80C528; P83C528
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. In Mode 0, reception is initiated by the condition RI = 0 and REN = 1. Reception is initiated by incoming start bit if REN = 1 in the other modes.
1997 Dec 15
30
Philips Semiconductors
Product specification
8-bit microcontrollers
12.1 Serial Port Control Register (SCON)
P83C524; P80C528; P83C528
Table 12 Serial Port Control register (address 98H) 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 13 Description of the SCON bits BIT 7 6 5 SYMBOL SM0 SM1 SM2 see Table 14. see Table 14. Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit is not received. In Mode 0, SM2 should be 0. Enables serial reception. Set and cleared by software as required. 9th data bit that will be transmitted in Modes 2 and 3. Set and cleared by software as required. In Modes 2 and 3, RB8 is the 9th data bit that is received. In Mode 1, if SM2 = 0, RB8 is the stop bit that is received. In Mode 0, RB8 is not used. Transmit interrupt flag. It is set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes. TI must be cleared by software. Receive interrupt flag. It is set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes (except: see SM2). RI must be cleared by software. FUNCTION
4 3 2 1 0
REN TB8 RB8 TI RI
12.2
SM0 and SM1 operating modes (SCON)
SCON bits SM0 and SM1 can operate in the following modes (see Table 14): Table 14 SM0 and SM1 operating modes MODE 0 1 2 3 0 0 1 1 SM0 0 1 0 1 SM1 8-bit UART 9-bit UART 9-bit UART DESCRIPTION shift register
1 1 12fOSC 1
BAUD RATE variable
32fOSC, 64fOSC
variable
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
13 BIT-LEVEL I2C INTERFACE This bit-level serial I/O interface supports the I2C-bus (see Fig.18). P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C specification concerning the input levels and output drive capability. Consequently, these pins have an open drain output configuration. All four modes of the I2C-bus are supported: * master transmitter * master receiver * slave transmitter * slave receiver. The advantages of the bit-level hardware compared with a full software I2C implementation are: * the hardware can generate the SCL pulse * testing a single bit (RBF respectively, WBF) is sufficient as a check for error free transmission. The bit-level I2C hardware operates on serial bit level and performs the following functions: * filtering the incoming serial data and clock signals * recognizing the START condition * generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock * recognizing the STOP condition * recognizing a serial clock pulse on the SCL line * latching a serial bit on the SDA line (SDI) * stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit * setting Read Bit Finished (RBF) when the SCL clock pulse has finished and Write Bit Finished (WBF) if there is no arbitration loss detected (i.e. SDA = 0 while SDO = 1) * setting a serial clock LOW-to-HIGH detected (CLH) flag * setting a Bus Busy (BB) flag on a START condition and clearing this flag on a STOP condition * releasing the SCL line and clearing the CLH, RBF and WBF flags to resume transfer of the next serial data bit * generating an automatic clock if the single bit data register S1BIT is used in master mode. I2C
P83C524; P80C528; P83C528
The following functions must be done in software: * handling the I2C START interrupts * converting serial to parallel data when receiving * converting parallel to serial data when transmitting * comparing the received slave address with its own * interpreting the acknowledge information * guarding the I2C status if RBF or WBF = 0. additionally, if acting as master: * generating START and STOP conditions * handling bus arbitration * generating serial clock pulses if S1BIT is not used. Three SFRs control the bit-level I2C interface: S1INT, S1BIT and S1SCS.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
RSBIT RSCS SDA FILTER FSDA D Q SDI FSCL C QN Q D WSBIT WSCS RSCS SDO IB7
P1.7 / SDA
DIS
C
P1.7 / SCL
SCL FILTER
FSCL IB6
Q AUTO - CLOCK GENERATOR DIS RSBIT WSBIT FSCL WSCS STAQ FSCL STRQ FSCL RSBIT WSBIT FSDA FSCL WSINT IB7 RSBIT WSBIT FSDA FSCL STOP EN S Q START SI STA R to interrupt logic CLHQ STAQN BBQ FSCLN EN S Q ST R QN START S IB5 RSBIT WSBIT S
D
SCO C WSCS
RSCS Q IB5
CLH R RSCS Q BB STOP R IB4
RBF
RSCS IB3
WBF SDIQN SDOQ
RSCS IB2
RSCS D IBX : internal data bus WSCS RSCS : read WSCS : write S1SCS RSCS RSBIT : read WSBIT : write D S1BIT (with auto-clock) WSCS WSINT : write S1INT PD
MBC484
Q
IB1
STR C
Q
IB0 DIS EN
ENS C
Fig.18 Bit level I2C interface block diagram.
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Philips Semiconductors
Product specification
8-bit microcontrollers
13.1 I2C Interrupt Register (S1INT)
P83C524; P80C528; P83C528
Table 15 I2C Interrupt register (address DAH) (1) 7 SI Note 1. SI bit: writing a logic 0 clears this bit, writing a logic 1 has no effect. Table 16 Description of the S1INT bits BIT 7 SYMBOL SI FUNCTION Serial Interrupt request (SI) flag: if a START condition occurs the SI flag in the S1INT SFR is set on the falling edge of the filtered serial clock. If SI = 1 is detected during a transfer this can be a 'spurious START' error condition. If no transfer is taking place the SI = 1 is a START from an external master. Provided the bits EA and ES1 in IE SFR are set, SI then generates an interrupt so that a slave address receive routine can be started. SI can be cleared by accessing the S1BIT register or by writing '00' to S1INT. Also after reception of a START condition, the LOW period of the clock pulse is stretched, suspending the serial transfer to allow the software to take action. This clock stretching is ended by a read or write access to S1BIT. X = undefined during read, don't care during write. 6 X 5 X 4 X 3 X 2 X 1 X 0 X
6 to 0 13.2
-
Single-bit Data Register with I2C Auto-clock (S1BIT)
Table 17 Single-bit Data register with I2C Auto-clock (address D9H)(1) 7 READ SDI WRITE SDO Note 1. Access of the S1BIT SFR clears SI, CLH, RBF and WBF. It starts the auto-clock if SCO = 0. Table 18 Description of the S1BIT bits BIT 7 SYMBOL SDO/SDI FUNCTION Serial Data Output (SDO) and the filtered Serial Data Input (SDI). SDI data is latched on the rising edge of the filtered serial clock. S1BIT.7 accesses the same memory locations as S1SCS.7. S1BIT SFR is not bit-addressable. X = don't care. X X X X X X X 0 0 0 0 0 0 0 6 5 4 3 2 1 0
6 to 0
-
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Philips Semiconductors
Product specification
8-bit microcontrollers
13.2.1 READING OR WRITING THE S1BIT SFR I2C
P83C524; P80C528; P83C528
Every bit I/O should be followed by a RBF or WBF bit test. A bit transfer has been finished successfully if after reading a bit the RBF flag is 1 or after writing a bit the WBF flag is 1. When after reading a bit the RBF flag is still 0, the bus status just before the S1SCS status read can be determined as follows: * if CLH = 0 then a bus device is still stretching the clock * if SCI = 1 while CLH = 1 then the SCL pulse is not finished * if BB = 0 there has been a STOP condition. When after writing a bit the WBF flag is still 0 and none of the 3 status conditions mentioned for RBF are found then a 'bus arbitration lost' condition will be the cause. This can be determined also from the states of the received bit and the last transmitted bit: 'arbitration loss' if SDO = 1 and SDI = 0.
Reading or writing the S1BIT SFR starts an bit I/O sequence: some flags are cleared (SI, CLH, RBF, WBF), clock stretching is finished and the auto-clock is started. An auto-clock pulse is 'OR-ed' with SCO and thus will be output only if the SCO flag has been set to 0. SCO = 1 inhibits the auto-clock start, so a dummy read or write of S1BIT SFR can be used to finish clock stretching and clear SI, CLH, RBF and WBF if the auto-clock is not used. The auto-clock is an active HIGH SCL pulse that starts 28 XTAL clock periods after the SDI read or SDO write via S1BIT. The duration of the auto-clock pulse is 100 XTAL clock periods. If the SCL line is kept LOW by any device that wants to hold up the bus transfer, the auto-clock counter waits after 20 XTAL clock periods so that the auto-clock pulse length will be at least 80 XTAL clock periods (5 s at fOSC = 16 MHz).
13.3
Control and Status Register for the I2C-bus (S1SCS)
Table 19 Control and Status register for the I2C-bus (address D8H) 7 READ SDI(1) WRITE SDO Notes 1. SDI and SCI bits: read-modify-write operations like 'SETB bit' or 'CLR bit' access SDO and SCO for reading and writing. 2. CLH bit: writing a logic 0 clears this bit, writing a 1 has no effect. 3. RBF and WBF bits: writing a logic 0 to CLH also clears these bits. 4. X = don't care. SCO CLH(2) X X X STR ENS SCI(1) CLH(2) BB RBF(3) WBF(4) STR ENS 6 5 4 3 2 1 0
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Philips Semiconductors
Product specification
8-bit microcontrollers
Table 20 Description of the S1SCS bits BIT 7 SYMBOL SDO/SDI
P83C524; P80C528; P83C528
FUNCTION Serial Data Output and the filtered Serial Data Input. SDI data is latched on the rising edge of the filtered serial clock. S1SCS.7 accesses the same memory locations as S1BIT.7. Access of the data bit via S1SCS will not start an auto-clock pulse. Serial Clock Output and the filtered Serial Clock Input. Serial clock output SCO is 'OR-ed' with the auto-clock. If SCO = 1 the auto-clock output is inhibited. The internal clock stretching logic and external devices can pull the SCL line LOW. If the auto-clock is not used, the SCL line has to be controlled by setting SCO = 1, waiting for CLH = 1 and setting SCO = 0 after the specified SCL HIGH time. (Because of the input filter, CLH will be set at least 8 XTAL clock periods after the SCL LOW-to-HIGH transition.) Serial Clock LOW-to-HIGH transition flag: set with a rising edge of the filtered serial clock. CLH = 1 indicates that, since the last CLH reset, a new valid data bit has been latched in SDI. CLH can be reset by writing a 0 to S1SCS.5 or by a read/write of S1BIT. Clearing CLH also clears RBF and WBF. Bus Busy flag: indicating that there has been a START condition that was not yet followed by a STOP condition. Read Bit Finished flag: indicating a successful bit read. RBF = 1 implies the following conditions: CLH = 1: SCL had a rising edge SCI = 0: the SCL pulse has finished SI = 0: no START condition occurred BB = 1: no STOP condition occurred The RBF flag can be cleared by clearing the CLH flag.
6
SCO/SCI
5
CLH
4 3
BB RBF
2
WBF
Write Bit Finished flag: indicating a successful bit write. The same conditions as for RBF are true and also no 'arbitration loss' condition occurred. Arbitration is lost if a 1 data bit in SDO was over-ruled on SDA by an external device. The WBF flag can be cleared by clearing the CLH flag. STRetch control flag. STR = 1 enables stretching of all SCL LOW periods. This allows the processor in I2C slave mode to react on a fast master. The STR flag remains set until cleared by writing a 0 to S1SCS.1. The STretch (ST) flag (not readable) pulls the serial clock LOW while ST = 1. The ST flag is set on the falling edge of the filtered serial clock if STR = 1. It is also set after reception of a START condition, regardless of the STR contents. ST is cleared with a read or write of S1BIT.
1
STR
0
ENS
ENable Serial I/O flag. ENS = 1 enables the START detection and clock stretching logic. ENS = 0 can be used to switch off the I2C-bus hardware. Note that the SDO and SCO control flags must be set to 1 before ENS is set to avoid pulling SCL or SDA lines to 0.
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Philips Semiconductors
Product specification
8-bit microcontrollers
14 INTERRUPT SYSTEM The P83C528 contains the same interrupt structure as the PCB80C51BH, but with a seven-source interrupt structure with two priority levels (see Fig.19). The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in TCON SFR. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, only if the interrupt was transition-activated. If the interrupt was level-activated then the interrupt request flag remains set until the external interrupt pin INTx goes high. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. The Serial Port Interrupt is generated by the logical 'OR' of RI and TI. Neither of these flags is cleared by hardware. The service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared by software. The Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2. Neither of these flags is cleared by hardware. In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software. An additional (third) external interrupt is available, if Timer 2 is not used as timer/counter or if Timer 2 is used in baud rate generator mode. That external interrupt 2 is falling edge triggered. It shares the Timer 2 interrupt vector, interrupt enable and interrupt priority bits. If bit T2CON.3/EXEN2 = 1, a HIGH-to-LOW transition at pin P1.1/T2EX sets the interrupt request flag T2CON.6/EXF2 and can be used to generate an external interrupt.
P83C524; P80C528; P83C528
The I2C interrupt is generated by SI in S1INT. This flag has to be cleared by software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware, with the exception of the I2C interrupt request flag SI, which cannot be set by software. That is, interrupts can be generated or pending interrupts can be cancelled in software.
handbook, halfpage 0
INT0 1
IE0
TF2 EXF2 SI TF0 0 INT1 1 IE1 interrupt sources
TF1 TI RI
MBC481 - 1
Fig.19 P83C528 Interrupt Sources.
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Philips Semiconductors
Product specification
8-bit microcontrollers
14.1 Interrupt Enable Register (IE)
P83C524; P80C528; P83C528
Table 21 Interrupt Enable register (address A8H) 7 EA 6 ES1 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Table 22 Description of the IE bits BIT 7 SYMBOL EA general enable/disable control: 0 = NO interrupt is enabled 1 = ANY individually enabled interrupt will be accepted 6 5 4 3 2 1 0 14.2 ES1 ET2 ES ET1 EX1 ET0 EX0 enable bit-level I2C I/O interrupt enable Timer 2 interrupt enable Serial Port interrupt enable Timer 1 interrupt enable External interrupt 1 enable Timer 0 interrupt enable External interrupt 0 FUNCTION
Interrupt Priority Register (IP)
Table 23 Interrupt Priority register (address B8H) 7 - 6 PS1 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
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Philips Semiconductors
Product specification
8-bit microcontrollers
14.3 Interrupt Vectors
P83C524; P80C528; P83C528
The interrupt vectors are listed in Table 25. Table 24 Description of the IP bits BIT 7 6 5 4 3 2 1 0 - PS1 PT2 PS PT1 PX1 PT0 PX0 SYMBOL reserved Bit-level I2C interrupt priority level Timer 2 interrupt priority level Serial Port interrupt priority level Timer 1 interrupt priority level External interrupt 1 priority level Timer 0 interrupt priority level External interrupt 0 priority level FUNCTION
Table 25 Interrupt vectors NUMBER 1 2 3 4 5 6 7 IE0 TF2+EXF2 SI (I2C) TF0 IE1 TF1 RI + TI SOURCE PRIORITY WITHIN LEVEL (highest) - - - - - (lowest) 0003H 002BH 0053H 000BH 0013H 001BH 0023H VECTOR ADDRESS
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Philips Semiconductors
Product specification
8-bit microcontrollers
15 IDLE AND POWER-DOWN OPERATION Idle mode operation permits the interrupt, serial ports and timer blocks to function while the CPU is halted. The following functions remain active during Idle mode. These functions may generate an interrupt or reset and thus end the Idle mode: * Timer 0, Timer 1, Timer 2, Watchdog Timer * UART, I2C-Interface * External interrupt
P83C524; P80C528; P83C528
The Power-down operation freezes the oscillator. The Power-down mode can only be activated by setting the PD bit in the PCON register (see Fig.20).
handbook, full pagewidth
XTAL2
XTAL1
OSCILLATOR
interrupts serial ports timer blocks CLOCK GENERATOR CPU
PD
IDL
MBC477 - 1
Fig.20 Internal Idle and Power-down clock configuration.
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Philips Semiconductors
Product specification
8-bit microcontrollers
15.1 Power Control Register (PCON)
P83C524; P80C528; P83C528
Special modes are activated by software via the PCON SFR. PCON is not bit addressable. The reset value of PCON is 0XXX0000. Table 26 Power Control Register (address 87H) 7 SMOD 6 - 5 - 4 - 3 GF1 2 GF0 1 PD 0 IDL
Table 27 Description of the PCON bits BIT 7 6 5 4 3 2 1 0 Notes 1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. 2. User software should not write 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features. SYMBOL SMOD - - - GF1 GF0 PD IDL FUNCTION Double Baud rate bit: when set to logic 1 the baud rate is doubled when Timer 1 is used to generate baud rate, and the Serial Port is used in modes 1, 2 or 3. reserved for future use reserved for future use reserved for future use general-purpose flag bit general-purpose flag bit Power-down bit: setting this bit activates Power-down mode Idle mode bit: setting this bit activates the Idle mode.
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Philips Semiconductors
Product specification
8-bit microcontrollers
15.2 Idle Mode
P83C524; P80C528; P83C528
* The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. * The third way of terminating the Idle mode is by internal watchdog reset. 15.3 Power-down Mode
The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before Idle mode is activated. Once in the Idle mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during Idle mode. The status of external pins during Idle mode is shown in Table 28. There are three ways to terminate the Idle mode: * Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON.0. * The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits.
The instruction that sets PCON.1 is the last executed prior to going into the Power-down mode. The oscillator is stopped. Note that the Power-down mode also can be entered when the watchdog has been enabled. The Power-down mode can be terminated by an external RESET in the same way as in the 80C51 or in addition by any one of the two external interrupts, IE0 or IE1 (see Section 15.4). A reset generated by the WDT terminates the Power-down mode in the same way as an external RESET. The status of the external pins during Power-down mode is shown in Table 28. If the Power-down mode is activated while in external program memory, the port data that is held in the P2 SFR is restored to Port 2. If the data is a logic 1, the port pin is held HIGH during the Power-down mode by the strong pull-up transistor p1 (see Fig.13).
Table 28 Status of the external pins during Idle and Power-down modes MODE Idle Idle Power-down Power-down MEMORY internal external internal external 1 1 0 0 ALE 1 1 0 0 PSEN PORT 0 port data floating port data floating PORT 1 port data port data port data port data PORT 2 port data address port data port data PORT 3 port data port data port data port data
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Philips Semiconductors
Product specification
8-bit microcontrollers
15.4 Wake-up from Power-down Mode
P83C524; P80C528; P83C528
Table 29 Internal registers status after a RESET REGISTER ACC B DPH, DPL IE IP PCH, PCL PCON PSW P0 to P3 SBUF SCON SP TCON TMOD TH0, TL0 TH1, TL1 T2CON TH2, TL2 RCAP2H, RCAP2L S1BIT S1INT S1SCS T3 WDCON 00H 00H 00H 0000 0000B X000 0000B 00H 0XXX 0000B 00H FFH Indeterminate 00H 07H 00H 00H 00H 00H 00H 00H 00H X000 0000B 0XXX XXXXB XXX0 0000B 00H A5H CONTENTS
The Power-down mode of the P83C528 can also be terminated by any one of the two external interrupts, IE0 or IE1. A termination with an external interrupt does not affect the internal data memory and does not affect the Special Function Registers (SFRs). This gives the possibility to exit Power-down without changing the port output levels. To terminate the Power-down mode with an external interrupt, IE0 or IE1 must be switched to be level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept LOW till the oscillator has restarted and stabilized (see Fig.21). In order to prevent any interrupt priority problems during wake-up, the priority of the desired wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. The instruction following the one that put the device into the Power-down mode will be the first one which will be executed after an interrupt has been serviced.
internal timing stopped power down oscillator stopped oscillator start up min. 20 ms
C1
C1 IDLE MODE interrupts are polled INT0 2 cycles INT1 1 cycle
C1 LCALL
C2
interrupt routine
INT0 / INT1 set external interrupt latch
MBC508 - 1
Fig.21 Wake up by external interrupt input.
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Philips Semiconductors
Product specification
8-bit microcontrollers
16 OSCILLATOR CIRCUIT The oscillator circuit of the P83C528 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between the XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the output (see Fig.22). To drive the P83C528 externally, XTAL1 is driven from an external source and XTAL2 left open-circuit (see Fig.23).
P83C524; P80C528; P83C528
17 RESET CIRCUIT The reset circuitry for the P83C528 is connected to the reset pin RST. A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods). The CPU responds by executing an internal reset. During reset ALE and PSEN output a HIGH level. In order to perform a correct reset, this level must not be affected by external elements. With the P83C528, the RST line can also be pulled HIGH internally by a pull-up transistor activated by the WDT T3. The length of the reset pulse from T3 is 16 x 2048 cycles of the on-chip watchdog oscillator. If the WDT is also used to reset external devices, the usual capacitor arrangement should not be connected to RST pin. Instead, an extra circuit should be used to perform the Power-on Reset operation. It should be remembered that a Timer T3 overflow, if enabled, will force a reset condition to the P83C528 by an internal connection, whether the output RST is tied LOW or not (see Fig.24). The internal reset is executed during the second cycle in which RST is pulled HIGH and is repeated every cycle until RST goes LOW. It leaves the internal registers as shown by Table 29.
handbook, halfpage
C1 20 pF
XTAL1
C2 20 pF
XTAL2
MBC473
Fig.22 P83C528 oscillator circuit.
VDD
handbook, halfpage
handbook, halfpage
external clock (not TTL compatible)
XTAL1
SCHMITT TRIGGER RESET CIRCUITRY
overflow timer T3
not connected
XTAL2
RST on-chip resistor R RST
MBC476 - 1
MBC472
Fig.23 Driving the P83C528 from an external source.
Fig.24 On-chip reset configuration.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
17.1 Power-on reset
P83C524; P80C528; P83C528
When VDD is turned on, and provided its rise-time does not exceed 10 ms, an automatic reset can be obtained by connecting the RST pin to VDD via a 2.2 F capacitor. When the power is switched on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRST) to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles, or 16 x 2048 cycles of the on-chip watchdog oscillator if it is running, whichever is longer (see Fig.25).
DD handbook, halfpage
V
2.2 F
VDD
P83C528
RST
R RST
MBC474
Fig.25 Power-on reset.
1997 Dec 15
45
Philips Semiconductors
Product specification
8-bit microcontrollers
18 INSTRUCTION SET
P83C524; P80C528; P83C528
The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz oscillator, 64 instructions execute in 1 cycle (1 s) and 45 instructions execute in 2 cycles (2 s). Multiply and divide instructions execute in 4 cycles (4 s). Table 30 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A Add register to A Add direct byte to A Add indirect RAM to A Add immediate data to A Add register to A with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX)
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Philips Semiconductors
Product specification
8-bit microcontrollers
Table 31 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate data to A Exclusive-OR A to direct byte DESCRIPTION
P83C524; P80C528; P83C528
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67 64 62 63 E4 F4 23 33 03 13 C4
Exclusive-OR immediate data to direct byte Clear A Complement A Rotate A left Rotate A left through the carry flag Rotate A right Rotate A right through the carry flag Swap nibbles within A
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Philips Semiconductors
Product specification
8-bit microcontrollers
Table 32 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A,Rr A,direct (note 1) A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @RI,A @Ri,direct @Ri,#data DPTR,#data 16 Move register to A Move direct byte to A Move indirect RAM to A Move immediate data to A Move A to register Move direct byte to register Move immediate data to register Move A to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM DESCRIPTION
P83C524; P80C528; P83C528
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7
Load data pointer with a 16-bit constant Move code byte relative to DPTR to A Move code byte relative to PC to A Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A Move A to external RAM (8-bit address) Move A to external RAM (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange register with A Exchange direct byte with A Exchange indirect RAM with A Exchange LOW-order digit indirect RAM with A
MOVC A,@A+DPTR MOVC A,@A+PC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri
1. MOV A,ACC is not permitted.
1997 Dec 15
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Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 33 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag Move direct bit to carry flag Move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1addr 12 22 32 1addr 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6, B7 D* D5 00 DESCRIPTION BYTES CYCLES OPCODE (HEX)
Program and machine control ACALL addr11 LCALL addr16 RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel @Ri,#data,rel Rr,rel direct,rel Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if A is zero Jump if A is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to register and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
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Philips Semiconductors
Product specification
8-bit microcontrollers
Table 34 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel working register R0-R7.
P83C524; P80C528; P83C528
DESCRIPTION
128 internal RAM locations and any special function register (SFR). indirect internal RAM location addressed by register R0 or R1 of the actual register bank. 8-bit constant included in instruction. 16-bit constant included as bytes 2 and 3 of instruction. direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64 kbytes program memory address space. 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of program memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E, F. 11, 31, 51, 71, 91, B1, D1, F1. 01, 21, 41, 61, 81, A1, C1, E1.
1997 Dec 15
50
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8-bit microcontrollers P83C524; P80C528; P83C528
SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1
Product specification
Philips Semiconductors
Product specification
8-bit microcontrollers
19 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134) SYMBOL VDD VI Ptot Tstg Tamb supply voltage range all input voltages total power dissipation storage temperature range operating ambient temperature range: version xBx version xFx PARAMETER
P83C524; P80C528; P83C528
MIN. -0.5 -0.5 - -65 0 -40
MAX. +6.0 VDD +0.5 1 +150 +70 +85 V V W C C C
UNIT
1997 Dec 15
52
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
20 DC CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = 0 to +70C; -40 to +85C. All voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD IID IPD Inputs VIL VIL1 VIL2 VIH VIH1 VIH2 IIL LOW level input voltage (except EA, P1.6, P1.7) LOW level input voltage EA LOW level input voltage P1.6, P1.7 HIGH level input voltage (except RST, XTAL1, P1.6, P1.7) HIGH level input voltage RST, XTAL1 HIGH level input voltage P1.6, P1.7 LOW level input current Ports 1, 2 and 3 (except P1.6 and P1.7) note 6 VI = 0.45 V note 6 -0.5 -0.5 -0.5 0.2 VDD +0.9 0.7 VDD 0.7 VDD - 0.2 VDD-0.1 0.2 VDD-0.3 0.3 VDD VDD +0.5 VDD +0.5 5.5 -50 V V V V V V A supply voltage range supply current operating modes, note 1 supply current Idle mode, note 2 VDDmax, 16 MHz VDDmax, 24 MHz VDDmax, 16 MHz VDDmax, 24MHz supply current Power-down mode 2 V VDD VDDmax; note 3 - - 4.5 - 5.5 33 43 6 7.5 100 V mA mA mA mA A PARAMETER CONDITIONS MIN. MAX. UNIT
ITL
input current HIGH-to-LOW transition VI = 2.0 V Ports 1, 2 and 3 (except P1.6 and P1.7) input leakage current Port 0, EA input leakage current P1.6 and P1.7 0.45 < VI < VDD 0 V < VI < 5.5 V 0 V < VDD < 5.5 V IOL = 1.6 mA; notes 6 and 7
-
-650
A
ILI1 ILI2 Outputs VOL
- -
10 10
A A
LOW level output voltage Ports 1, 2 and 3 (except P1.6 and P1.7) LOW level output voltage Port 0, ALE, PSEN LOW level output voltage P1.6 and P1.7 HIGH level output voltage Ports 1, 2 and 3 (except P1.6 and P1.7)
-
0.45
V
VOL1 VOL2 VOH
IOL = 3.2 mA; notes 4 and 7 IOL = 3.0 mA; note 7 IOH = -60 A; VDD = 5 V 10% IOH = -25 A IOH = -10 A
- - 2.4 0.75 VDD 0.9 VDD
0.45 0.40 - - -
V V V
1997 Dec 15
53
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
SYMBOL VOH1
PARAMETER HIGH level output voltage Port0in in external bus mode, ALE, PSEN, RST
CONDITIONS IOH = -800 A; VDD = 5 V 10% IOH = -300 A; IOH = -80 A; note 5 2.4
MIN. - - - 150 10
MAX.
UNIT V
0.75VDD 0.9VDD 50
RRST CI/O
RST pull-down resistor I/O pin capacitance test frequency = 1 MHz; Tamb = 25 C
k pF
-
Notes to the DC characteristics 1. Conditions for: a) The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns; VIL = VSS +0.5 V; VIH = VDD -0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD; the WDT is disabled (by the external RESET). 2. Conditions for: a) The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns; VIL = VSS +0.5 V; VIH = VDD -0.5 V; XTAL2 not connected; the WDT is disabled; EA = RST = VSS; Port 0 = P1.6 = P1.7 = VDD. 3. Conditions for: a) The Power-down current is measured with all output pins disconnected; XTAL2 not connected; WDT is disabled; EA = RST = XTAL1 = VSS; Port 0 = P1.6 = P1.7 = VDD. 4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address bits are stabilizing. 6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so a voltage below 0.3 VDD will be recognized as a logic 0 while an input above 0.7 VDD will be recognized as a logic 1. 7. Under steady state (non-transient) conditions, IOL must be externally limited as follows: a) Maximum IOL per port pin:10 mA. b) Maximum IOL per 8-bit port:- Port 0: 26 mA; Ports 1, 2 and 3: 15 mA. c) Maximum total IOL for all output pins: 71 mA. If IOL exceeds the test condition, VOL may exceed the related specification. d) Pins are not guaranteed to sink current greater than the listed test conditions. 8. IDD max. at other frequencies can be derived from Fig.26 where f is the external oscillator frequency in MHz; IDD max. is given in mA.
1997 Dec 15
54
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
MBC478
handbook, full pagewidth
50 I DD (mA) 40 MAX ACTIVE MODE
30
TYP ACTIVE MODE
20
10 MAX IDLE MODE TYP IDLE MODE 0 0 8 16 f (MHz) 24
Valid only within frequency specifications of device under test.
Fig.26 IDD as a function of frequency.
1997 Dec 15
55
Philips Semiconductors
Product specification
8-bit microcontrollers
21 AC CHARACTERISTICS
P83C524; P80C528; P83C528
21.1 AC Characteristics 16 MHz version See notes 1, 2 and 3 in Section 21.2; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. 16 MHZ SYMBOL External program memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tLHLL tAVLL tLLAX tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDZ tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ ALE pulse duration address set-up time to ALE address hold time after ALE time from ALE to valid instruction input time from ALE to control pulse PSEN control pulse duration PSEN time from PSEN to valid instruction input input instruction hold time after PSEN input instruction float delay after PSEN address to valid instruction input address float time to PSEN 85 8 28 - 23 143 - 0 - - - - - - 150 - - 83 - 38 208 10 - - - - - 148 - 55 350 398 238 - 103 - - - 0 2 tCK-40 tCK-55 tCK-35 - tCK-40 3 tCK-45 - 0 - - - 2 tCK-40 tCK-55 tCK-35 6 tCK-100 6 tCK-100 - 0 - - - 3 tCK-50 4 tCK-130 tCK-40 tCK-60 7 tCK-150 tCK-50 - - - - 4 tCK-100 - - 3 tCK-105 - tCK-25 5 tCK-105 10 - - - - - 5 tCK-165 - 2 tCK-70 8 tCK-150 9 tCK-165 3 tCK+50 - tCK+ 40 - - - 0 ns ns ns ns ns ns ns ns ns ns ns PARAMETER MIN. MAX. MIN. MAX. VARIABLE CLOCK UNIT
External data memory ALE pulse duration address set-up time to ALE address hold time after ALE RD pulse duration WR pulse duration RD to valid data input data hold time after RD data float delay after RD time from ALE to valid data input address to valid data input time from ALE to RD or WR time from address to RD or WR time from RD or WR HIGH to ALE HIGH data valid to WR transition data set-up time before WR data hold time after WR address float delay after RD 85 8 28 275 275 - 0 - - - 138 120 23 3 288 13 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1997 Dec 15
56
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
21.2 AC Characteristics 24 MHz version See notes 1, 2 and 3.; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. 24 MHZ SYMBOL External program memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tLHLL tAVLL tLLAX tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDZ tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ ALE pulse duration address set-up time to ALE address hold time after ALE time from ALE to valid instruction input time from ALE to control pulse PSEN control pulse duration PSEN time from PSEN to valid instruction input input instruction hold time after PSEN input instruction float delay after PSEN address to valid instruction input address float time to PSEN 43 17 17 - 17 80 - 0 - - - - - - 102 - - 65 - 17 128 10 - - - - - 118 - 55 183 210 175 - 67 - - - 0 2 tCK-40 tCK-25 tCK-25 - tCK-25 3 tCK-45 - 0 - - - 2 tCK-40 tCK-25 tCK-25 6 tCK-100 6 tCK-100 - 0 - - - 3 tCK-50 4 tCK-75 tCK-25 tCK-30 7 tCK-130 tCK-25 - - - - 4 tCK-65 - - 3 tCK-60 - tCK-25 5 tCK-80 10 - - - - - 5 tCK-90 - 2 tCK-28 8 tCK-150 9 tCK-165 3 tCK+50 - tCK+ 25 - - - 0 ns ns ns ns ns ns ns ns ns ns ns PARAMETER MIN. MAX. MIN. MAX. VARIABLE CLOCK UNIT
External data memory ALE pulse duration address set-up time to ALE address hold time after ALE RD pulse duration WR pulse duration RD to valid data input data hold time after RD data float delay after RD time from ALE to valid data input address to valid data input time from ALE to RD or WR time from address to RD or WR time from RD or WR HIGH to ALE HIGH data valid to WR transition data set-up time before WR data hold time after WR address float delay after RD 43 17 17 150 150 - 0 - - - 75 92 17 12 162 17 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes to the AC Characteristics 16 and 24 MHz versions 1. For the AC Characteristics the following conditions are valid: a) P83C52x EBx: VDD = 5 V 10%; VSS = 0 V; Tamb = 0 to +70 C; tCK min. = 63 ns b) P83C52x EFx: VDD = 5 V 10%; VSS = 0 V; Tamb = -40 to +85 C; tCK min. = 63 ns. 2. tCK min. = 1/f max. (maximum operating frequency); tCK = clock period (see section for timing symbol definitions). 3. The maximum operating frequency is limited to 16/24 MHz and the minimum to 3.5 MHz (all versions Ixx/Exx). 1997 Dec 15 57
Philips Semiconductors
Product specification
8-bit microcontrollers
22 I2C CHARACTERISTICS (BIT-LEVEL) SYMBOL SCL timing tHD;STA tLOW tHIGH tRC tFC SDA timing tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF tRD tFD Notes data set-up time data hold time repeated START set-up time STOP condition set-up time bus free time SDA RISE time SDA FALL time 250 ns 0 ns 14 tCK; note 1 14 tCK; note 1 14 tCK; note 1 1; note 4 300 ns; note 4 START condition hold time SCL LOW time SCL HIGH time SCL RISE time SCL FALL time 14 tCK; note 1 16 tCK 14 tCK; note 1 1; note 4 0.3; note 4 PARAMETER INPUT
P83C524; P80C528; P83C528
OUTPUT
I2C SPEC 4.0 4.7 4.0 1.0 0.3 250 0 4.7 4.0 4.7 1.0 0.3
UNIT s s s s s
note 2 note 2 80 tCK; note 3 note 5 0.3; note 6
note 2 note 2 note 2 note 2 note 2 note 5 0.3; note 6
ns ns s s s s s
1. At fCLK = 3.5 MHz, this evaluates to 14 x 286 ns = 4 s, i.e. the bit-level I2C interface can respond to the I2C protocol for fCLK 3.5 MHz. 2. This parameter is determined by the user software, it has to comply with the I2C specification. 3. This value gives the auto-clock pulse length which meets the I2C specification for the specified XTAL1 clock frequency range. Alternatively, the SCL pulse may be timed by software. 4. Spikes on SDA and SCL lines with a duration of less than 4 x fCLK will be filtered out. 5. The RISE time is determined by the external bus line capacitance and pull-up resistor, it must be 1 s. 6. The maximum capacitance on bus lines SDA and SCL is 400 pF.
1997 Dec 15
58
Philips Semiconductors
Product specification
8-bit microcontrollers
23 XTAL1 CHARACTERISTICS Oscillator circuitry: crystal capacitors: C1 = C2 = 20 pF (see Fig.31). Table 36 External clock drive XTAL
P83C524; P80C528; P83C528
VARIABLE CLOCK SYMBOL fCLK tCK tHIGH tLOW tr tf tCY PARAMETER MIN. clock frequency clock period HIGH time LOW time RISE time FALL time cycle time (tCY = 12 tCK) 3.5 42 17 17 - - 0.5 24 286 tCK - tLOW tCK - tHIGH 5 5 3.43 MAX. MHz ns ns ns ns ns s UNIT
24 SERIAL PORT CHARACTERISTICS See Table 37 and Fig.32. Table 37 Serial Port Timing: Shift Register Mode VDD = 5 V 10%; VSS = 0 V; Tamb = 0 C to 70 C; Load Capacitance = 80 pF 24 MHZ OSCILLATOR SYMBOL tXLXL tQVXH tXHQX tXHDX tXHDV PARAMETER MIN. Serial Port clock cycle time output data setup to clock rising edge output data hold after clock rising edge input data hold after clock rising edge clock rising edge to input data valid 0.5 283 23 0 - - - - - 283 MAX. VARIABLE OSCILLATOR MIN. 12 tCK 10 tCK-133 2 tCK-60 0 - - - - - 10 tCK-133 MAX. s ns ns ns ns
UNIT
1997 Dec 15
59
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repeated START condition START or repeated START condition STOP condition t RD t SU;STA START condition SDA (input / output) t BUF t SU;STO 0.7 VDD 0.3 VDD t SU;DAT3 t SU;DAT2
MBC482
25 TIMING DIAGRAMS
Philips Semiconductors
8-bit microcontrollers
0.7 V DD 0.3 VDD t FD t RC t FC
Fig.27 I2C interface timing.
handbook, full pagewidth
60
SCL (input / output)
P83C524; P80C528; P83C528
t HD;STA
t LOW
t HIGH
t SU;DAT1
t HD;DAT
Product specification
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
handbook, full pagewidth
t LHLL
ALE t LLPL t AVLL t LLIV t PLIV PSEN t LLAX t PLAZ PORT 0 A0 - A7 t AVIV t PXIX INSTR IN A0 - A7 t PXIZ t PLPH
PORT 2
A8 - A15
A8 - A15
MBC483 - 1
Fig.28 External program memory read cycle.
1997 Dec 15
61
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ALE t WHLH PSEN t LLDV t LLWL RD t AVLL t LLAX t RLDV t RHDX PORT 0 A0 - A7 from RI or DPL t AVWL DATA IN A0 - A7 from PCL INSTR IN t RHDZ t RLRH
handbook, full pagewidth
Philips Semiconductors
8-bit microcontrollers
62
t AVDV PORT 2
P83C524; P80C528; P83C528
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MBC485 - 1
Product specification
Fig.29 External data memory read cycle.
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ALE t WHLH PSEN t LLWL WR t QVWX t AVLL PORT 0 t LLAX t QVWH t WHQX t WLWH
Philips Semiconductors
8-bit microcontrollers
Fig.30 External data memory write cycle.
handbook, full pagewidth
63
P83C524; P80C528; P83C528
A0 - A7 from RI or DPL t AVWL
DATA OUT
A0 - A7 from PCL
INSTR IN
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MBC486 - 1
Product specification
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
2.0 V
handbook, full pagewidth
2.0 V
2.4 V test points 0.45 V 0.8 V
(a)
float
0.8 V
2.4 V
2.0 V 0.8 V
2.0 V 0.8 V
2.4 V
0.45 V
0.45 V
(b)
MBC480
AC testing inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are taken at 2.0 V for a logic 1 and 0.8 V for logic 0 see (a). The float state is defined as the point at which a Port 0 pin sinks 3.2 mA or sources 400 A at the voltage test levels see (b).
Fig.31 AC testing input, output waveform (a) and float waveform (b).
handbook, full pagewidth
t HIGH V IH1 0.8 V V IH1 0.8 V t LOW
tr V IH1 0.8 V V IH1
tf
0.8 V
t CK
MBC479
See Table 36.
Fig.32 External clock drive XTAL1.
1997 Dec 15
64
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
INSTRUCTION
handbook, full pagewidth
0
1
2
3
4
5
6
7
8
ALE t XLXL
CLOCK t XHQX t QVXH OUTPUT DATA t XHDX WRITE TO SBUF INPUT DATA t XHDV
VALID VALID VALID VALID VALID VALID VALID
SET TI
VALID
CLEAR RI
MBC475
SET RI
See Table 37.
Fig.33 Shift register mode timing waveforms.
1997 Dec 15
65
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
one machine cycle
andbook, full pagewidth
one machine cycle S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2
S1 P1 P2 XTAL1 INPUT
S2 P1 P2
S3 P1 P2
S4 P1 P2
ALE dotted lines are valid when RD or WR are active PSEN
only active during a read from external data memory only active during a write to external data memory
RD
WR
external program memory fetch
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
read or write of external data memory
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
data output or data input
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT OUTPUT
old data
new data
PORT INPUT sampling time of I/O port pins during input (including INT0 and INT1) SERIAL PORT CLOCK
MBC487 - 1
Fig.34 Instruction cycle timing.
1997 Dec 15
66
Philips Semiconductors
Product specification
8-bit microcontrollers
25.1 Timing symbol definitions
P83C524; P80C528; P83C528
Oscillator: fCLK = clock frequency tCK = clock period Timing symbols (acronyms): Each timing symbol has five characters. The first character is always a 't' (= time). the remaining four characters of the symbol (typed in subscript), depending on their relative positions, indicate the name of a signal or the logical status of that signal. the designations are as follows: A =address C = clock D = input data H = logic level HIGH I = instruction (program memory contents) L = Logic level LOW or ALE P = PSEN Q = output data R = RD signal t = time V = valid W = WR signal X = no longer a valid logic level Z = float Examples: tAVLL = time for address valid to ALE LOW tLLPL = time for ALE LOW to PSEN LOW
1997 Dec 15
67
Philips Semiconductors
Product specification
8-bit microcontrollers
26 PACKAGE OUTLINES
P83C524; P80C528; P83C528
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 40 21 MH wM (e 1)
pin 1 index E
1
20
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015AJ EIAJ EUROPEAN PROJECTION A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 15.24 0.60
L 3.60 3.05 0.14 0.12
ME 15.80 15.24 0.62 0.60
MH 17.42 15.90 0.69 0.63
w 0.254 0.01
Z (1) max. 2.25 0.089
52.50 51.50 2.067 2.028
14.1 13.7 0.56 0.54
ISSUE DATE 92-11-17 95-01-14
1997 Dec 15
68
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD y X A ZE
eE
39
29 28
40
bp b1 wM
44
1
pin 1 index
E
HE A
e
A4 A1 (A 3)
k
6
18 k 1 Lp 7 e D HD 17 ZD B vMB detail X vM A
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm inches
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.05
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07
45 o
0.180 0.020 0.01 0.165
0.630 0.630 0.695 0.695 0.048 0.057 0.021 0.032 0.656 0.656 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.12 0.590 0.590 0.685 0.685 0.042 0.040 0.013 0.026 0.650 0.650
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-25
1997 Dec 15
69
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Dec 15
70
Philips Semiconductors
Product specification
8-bit microcontrollers
27 SOLDERING 27.1 Introduction
P83C524; P80C528; P83C528
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 27.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 27.2 27.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
27.3.2.1
PLCC
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners.
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 27.2.2 REPAIRING SOLDERED JOINTS
27.3.2.2
QFP
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners.
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 27.3 27.3.1 PLCC and QFP REFLOW SOLDERING
Reflow soldering techniques are suitable for all PLCC and QFP packages. The choice of heating method may be influenced by larger PLCC or QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1997 Dec 15 71
Philips Semiconductors
Product specification
8-bit microcontrollers
27.3.2.3 Method (PLCC and QFP)
P83C524; P80C528; P83C528
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 27.3.3 REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
28 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 29 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 30 PURCHASE OF PHILIPS I2C COMPONENTS This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 15
72
Philips Semiconductors
Product specification
8-bit microcontrollers
NOTES
P83C524; P80C528; P83C528
1997 Dec 15
73
Philips Semiconductors
Product specification
8-bit microcontrollers
NOTES
P83C524; P80C528; P83C528
1997 Dec 15
74
Philips Semiconductors
Product specification
8-bit microcontrollers
NOTES
P83C524; P80C528; P83C528
1997 Dec 15
75
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/25/01/pp76
Date of release: 1997 Dec 15
Document order number:
9397 750 02916

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