View ICS307_133840.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICS307 Serially Programmable Clock Source
Description
The ICS307-01 and ICS307-02 are versatile serially programmable clock sources which take up very little board space. They can generate any frequency from 6 to 200 MHz, and have a second configurable output. The outputs can be reprogrammed on the fly, and will lock to a new frequency in 10 ms or less. Smooth transitions (in which the clock duty cycle remains roughly 50%) are guaranteed if the output divider is not changed. The devices include a PDTS pin which tri-states the output clocks and powers down the entire chip. The ICS307-02 features a default clock output at start-up and is recommended for all new designs.
Features
* Packaged as 16 pin narrow SOIC * Highly accurate frequency generation * Serially programmable: user determines the output frequency via a 3 wire interface. * Eliminates need for custom quartz * Input crystal frequency of 5 - 27 MHz * Output clock frequencies up to 200 MHz * Power Down Tri-State mode * Very low jitter * Operating voltages of 3.0 to 5.5 V * 25 mA drive capability at TTL levels * Industrial temperature available
Block Diagram
TTL 2 Shift Register 3 2 R6:R0 7
VDD GND
SCLK DATA STROBE
C1:C0 S2:S0 F1:F0
9
V8:V0 Output Buffer VCO Divider S2:S0 3 VCO Output Divider PDTS CLK1
Crystal or clock input
X1/ICLK
Reference Divider
Phase Comparator, Charge Pump, and Loop Filter
Crystal Oscillator
X2
Function Select 2 F1:F0
Output Buffer TTL
CLK2
C1:C0
MDS 307 D 1 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
Pin Assignment
ICS307 X1/ICLK NC VDD NC GND CLK2 NC SCLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC NC PDTS DATA CLK1 NC STROBE
16 pin Narrow (0.150") SOIC
Pin Description
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name X1/ICLK NC VDD NC GND CLK2 NC SCLK STROBE NC CLK1 DATA PDTS NC NC X2 Type XI P P O I I O I I XO Description Crystal connection (REF frequency). Connect to a parallel resonant crystal, or an input clock . No Connect. Connect to +3.3V or +5V. No Connect. Connect to ground. Output clock 2, determined by F0-F1. Can be reference, ref/2, CLK1/2 or off. No Connect. Serial clock. See timing diagram. Strobe to load data. See timing diagram. No Connect. Output clock 1, determined by R0-R6, V0-V8, S0-S2 and input frequency. Data Input. Serial input for three words which set the output clock(s). Powers down entire chip, tri-states CLK1 and CLK2 outputs, when low. Internal pull-up. No Connect. No Connect. Input crystal connection. Connect to a crystal, or leave unconnected for clock input.
Type: XI, XO=crystal connections, I = Input, O = output, P = power supply connection
MDS 307 D 2 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
Determining the Output Frequency
On power-up the ICS307-01 on-chip registers can have random values, so almost any frequency may be output from the part. CLK1 will always have some clock signal present, but CLK2 could possibly be OFF (low). The ICS307-02 on-chip registers are initially configured to provide a x1 output clock on both the CLK1 and CLK2 outputs. The output frequency will be the same as the input clock or crystal. This is useful if the ICS307 will provide the initial system clock at power-up. Since this feature is an advantage in most systems, the ICS307-02 is recommended for new designs. With programming, the user has full control in changing the desired output frequency to any value over the range shown in Table 1 on page 4. The output of the ICS307 can be determined by the following simple equation: (VDW+8) CLK1 frequency = Input frequency * 2 * (RDW+2)(OD) Where VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted) Reference Divider Word (RDW) = 1 to 127 (0 is not permitted) Output Divider = values on page 4
Also, the following operating ranges should be observed: (VDW+8) 55 MHz < Input frequency * 2 * (RDW+2) 200 kHz < Input Frequency (RDW+2) < 400 MHz Commercial temperature range. Industrial temperature limits are 60 MHz to 360 MHz.
To determine the best combination of VCO, reference, and output dividers, contact ICS application engineering. You may also fax this page to ICS at 408 295 9818(fax). Be sure to indicate the following: Your Name ________________ Company Name___________________ Telephone_________________ Respond by e-mail (list your e-mail address) __________________or fax number ___________________ Desired input crystal_______ or clock_______ (in MHz) Desired output frequency_______________ REF Output_______VDD = 3.3V or 5V _______ Duty Cycle: 40-60% _____ or 45-55% required____
MDS 307 D 3 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
Setting the Device Characteristics
The tables below show the settings which can be configured, in addition to the VCO and Reference dividers.
Table 1. Output Divide and Maximum Output Frequency Max. Freq. CLK1 Maximum Frequency Industrial S2 S1 S0 Output Version Divide 5 V or 3.3 V
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 10 2 8 4 5 7 3 6 40 200 50 100 80 55 135 67 36 180 45 90 72 50 120 60
Table 2. CLK2 Output
F1 0 0 1 1 F0 0 1 0 1 CLK2 REF REF/2 OFF (Low) CLK1/2
0 = Connect directy to ground 1 = Connect directly to VDD
Table 3. Output Duty Cycle Configuration
TTL 0 1 Duty cycle measured at 1.4V VDD/2 Recommended VDD 5V 3.3 V
Table 4. Crystal Load Capacitance
C1 0 0 1 1 C0 0 1 0 1 VDD = 5 V 22.3 - 0.083 f 23.1 - 0.093 f 23.7 - 0.106 f 24.4 - 0.120 f VDD = 3.3 V 22.1 - 0.094 f 22.9 - 0.108 f 23.5 - 0.120 f 24.2 - 0.135 f
Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty cycle with TTL levels. When VDD is 3.3 V, set this bit to a 1, so the 50% duty cycle is achieved at VDD/2.
Note: f is the crystal frequency, between 10 and 27 MHz. Effective load capacitance will be higher for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0.
MDS 307 D 4 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are written to the DATA pin, in this order:
C1 C0 TTL F1 F0 MSB S2 S1 S0 LSB V8 V7 V6 V5 V4 V3 V2 V1 MSB LSB V0 R6 R5 R4 R3 R2 R1 R0 MSB LSB
C1 is loaded into the port first and R0 last. R6:R0 V8:V0 S2:S0 F1:F0 TTL C1:C0 Reference Divider Word (RDW) VCO Divider Word (VDW) Output Divider Select (OD) Function of CLK2 Output Duty Cycle Setting Internal Load Capacitance for Crystal
Power up default values for ICS 307-02
0 0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
The input frequency will come from both outputs.
Programming Example
To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276, and the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2 to be OFF means that the following three bytes are sent to the ICS307: 00110001 Byte 1 10001010 Byte 2 00111011 Byte 3
As shown in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this data to the internal latch, and the CLK output will lock within 10 ms. NOTE: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will change accordingly. Although this will not damage the ICS307, it is recommended that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid unintended changes on the output clocks.
MDS 307 D 5 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
DATA
C1
C0
TTL thold
F1
*
*
*
R1
R0
tsetup SCLK
*
*
*
tw STROBE
ts
Figure 2. Timing Diagram for Programming the ICS307
AC Parameters for Writing to the ICS307
Parameter
t SETUP t HOLD tw ts
Condition Setup time. Hold time after SCLK. Data wait time. Strobe pulse width
Min 10 10 10 40
Max
Units
ns ns ns ns
External Components / Crystal Selection
The ICS307 require a 0.01F decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS307 to minimize lead inductance. A 33 terminating resistor can be used in series with the CLK1 and CLK2 outputs. A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of C should be used, where C is the value calculated from Table 4. For crystals with a specified load capacitance greater than C, additional crystal capacitors may be connected from each of the pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal caps should be = (CL -C)*2, where CL is the crystal load capacitance in pF. These external capacitors are only required for applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on either pin).
MDS 307 D 6 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
Electrical Specifications
Parameter Conditions Minimum ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature 0 Ambient Operating Temperature, Industrial I version -40 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted) Operating Voltage, VDD 3 Input High Voltage, VIH, X1/ICLK only ICLK (Pin 1) (VDD/2)+1 Input Low Voltage, VIL, X1/ICLK only ICLK (Pin 1) Input High Voltage, VIH 2 Input Low Voltage, VIL PDTS, ICS307-01 only All other inputs,-01 & -02 Output High Voltage, VOH, CMOS level IOH=-4 mA VDD-0.4 Output High Voltage, VOH IOH=-25 mA 2.4 Output Low Voltage, VOL IOL=25 mA IDD Operating Supply Current, 20 MHz crystal No Load, 100 MHz out 100MHz out,VDD=3.3V Short Circuit Current CLK1 and CLK2 outputs On-Chip Pull-up Resistor Pin 13 Input Capacitance AC CHARACTERISTICS Input Frequency, crystal input (must be fundamental) 5 Input Frequency, clock input 2 Output Frequency (See Table 1) VDD = 3.0 to 5.5V 6 6 Output Frequency (see Table 1), I version VDD = 3.0 to 5.5V Output Clock Rise Time 0.8 to 2.0V Output Clock Fall Time 2.0 to 0.8V Output Clock Duty Cycle, even output divides At duty cycle level 45 Output Clock Duty Cycle, odd output divides At duty cycle level 40 Power-up time, STROBE goes high until CLK out Absolute Maximum Clock Period Jitter Deviation from mean One Sigma Clock Period Jitter Typical Maximum 7 VDD+0.5 VDD+0.5 70 85 260 150 5.5 VDD/2 VDD/2 (VDD/2)-1 0.4 0.8 Units V V V C C C C V V V V V V V V mA mA mA k pF MHz MHz MHz MHz ns ns % % ms ps ps
0.4 26 13 70 270 4 27 50 200 180 1 1 49 to 51 3 120 50
55 60 10
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. Typical values are at 25C.
MDS 307 D 7 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com
ICS307 Serially Programmable Clock Source
Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Symbol A
A1
E
INDEX AREA
H
B
C
1
2
D A1 e C
h x 45 A L
D E e H h L
Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500
Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27
B
Ordering Information
Part/Order Number ICS307M-01 ICS307M-01T ICS307M-01I ICS307M-01IT ICS307M-02 ICS307M-02T ICS307M-02I ICS307M-02IT Marking ICS307M-01 ICS307M-01 ICS307M-01I ICS307M-01I ICS307M-02 ICS307M-02 ICS307M-02I ICS307M-02I Package 16 pin SOIC 16 pin SOIC on tape and reel 16 pin SOIC 16 pin SOIC on tape and reel 16 pin SOIC 16 pin SOIC on tape and reel 16 pin SOIC 16 pin SOIC on tape and reel Temperature 0 to 70 C 0 to 70 C -40 to 85C -40 to 85C 0 to 70 C 0 to 70 C -40 to 85C -40 to 85C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 307 D 8 Revision 042501 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126*(408) 295-9800tel *www.icst.com

▲Up To Search▲

Price & Availability of ICS307

	To Download ICS307 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .