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MITSUBISHI SEMICONDUCTOR Preliminary M69897VP 16:1 2.488 Gbps Multiplexer DESCRIPTION The M69897VP multiplexer chip is an integrated serialization SONET OC-48 (2.488 Gbps) interface device. The chip performs parallel-to-serial functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based ATM applications. The merits of SOI (Silicon-On-Insulator) technology, such as low voltage operation, low substrate noise and good compatibility with standard CMOS technology, are fully utilized in the chip design to achieve low jitter and low power operation and small package outline of 64-pin PQFP. FEATURES - Single 1.8 V power supply - Supports 2.488 Gbps (OC-48, STM-16) - 16-bit single-ended PECL interface - On-chip high-frequency PLL for clock generation - 155.52 MHz reference frequency - Low power consumption - Available in 64 PQFP - Parity check function APPLICATIONS - SONET/SDH systems - Fiber optic systems - High-speed back plane interconnect and point-to-point data links PARITY PARITYI PARIERRO CHECK 16 PDI[15:0] 155.52 Mbps 16:1 PARALLEL D-FF TO SERIAL 2 SDOP/SDON 2.488 Gbps 2 PCLKOP/ PCLKON 2 TIMING 155.52 MHz 2 2.488 GHz 2.488 GHz GENERATOR 2.488 GHz SCLKOP/ SCLKON SCLKIP/ SCLKIN 2.488 GHz PCLKIP/ PCLKIN 2 2 155.52 MHz PLL LPF_EXT1/ LPF_EXT2 SELPLL Figure 1 Functional Block Diagram 1 MITSUBISHI ELECTRIC December 2000 Table 1 Absolute Maximum Ratings PARAMETER Storage Temperature Voltage on VDD with Respect to GND Voltage on any PECL Pin ESD Rating (HBM model) MIN -65 -0.5 0 1000 TYP MAX 150 2.2 2.2 UNITS uC V V V Table 2 Recommended Operating Conditions PARAMETER Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on VDD with Respect to GND Power Consumption 1.71 1.8 260 320 MIN 0 TYP MAX 70 110 1.89 310 420 UNITS uC uC V mW mW All Outputs Unterminated. All Outputs Terminated. CONDITIONS Table 3 Differential PECL Input DC Characteristics SYMBOL VIL VIH AEV INDIFF DESCRIPTION Input Low Voltage Input High Voltage Differential Input Voltage Swing MIN GND VDD -1.2 0.2 TYP MAX VDD -1.4 VDD -0.8 1.1 UNITS V V V See Figure 12. CONDITIONS Table 4 Single-Ended PECL Input DC Characteristics SYMBOL VIL VIH AEV IN DESCRIPTION Input Low Voltage Input High Voltage Input Voltage Swing MIN GND VDD -1.1 0.4 TYP MAX VDD -1.5 VDD -0.8 1.1 UNITS V V V See Figure 12. CONDITIONS Table 5 CMOS Input DC Characteristics SYMBOL VIL VIH DESCRIPTION Input Low Voltage Input High Voltage MIN GND VDD -0.5 TYP MAX VDD -1.3 VDD UNITS V V CONDITIONS Table 6 Differential PECL Output DC Characteristics SYMBOL VOL VOH AEV OUTDIFF DESCRIPTION Output Low Voltage Output High Voltage Differential Output Voltage Swing MIN GND VDD -0.9 0.7 TYP MAX 0.1 VDD -0.8 1.1 UNITS V V V See Figure 12. CONDITIONS Table 7 Single-Ended PECL Output DC Characteristics SYMBOL VOL VOH AEV OUT DESCRIPTION Output Low Voltage Output High Voltage Output Voltage Swing MIN GND VDD -0.9 0.7 TYP MAX 0.1 VDD -0.8 1.1 UNITS V V V See Figure 12. CONDITIONS 2 MITSUBISHI ELECTRIC December 2000 Table 8 Clock Jitter Characteristics SYMBOL Tjitter F-3dB Fpeak DESCRIPTION Output Jitter Jitter Transfer (12K-20MHz) Jitter Transfer Peaking 0.1 MIN TYP MAX 0.01 10 UNITS UIrms MHz dB CONDITIONS PDI[15:0]/ PARITYI 50 1/2 M69897VP Figure 2 Single-Ended PECL Input DC Termination VDD 180 1/2 0.1 F PDI[15:0]/ PARITYI 70 1/2 M69897VP Figure 3 Single-Ended PECL Input AC Termination PCLKIP 50 1/2 PCLKIN 50 1/2 M69897VP Figure 4 Differential PECL Input DC Termination for 155.52 MHz Clock. 3 MITSUBISHI ELECTRIC December 2000 VDD 180 1/2 0.1 F PCLKIP 70 1/2 VDD 180 1/2 0.1 F PCLKIN 70 1/2 M69897VP Figure 5 Differential PECL Input AC Termination for 155.52 MHz Clock. VDD 180 1/2 100 pF SCLKIP VDD 180 1/2 100 pF SCLKIN M69897VP Figure 6 Differential PECL Input AC Termination for 2.488 GHz Clock (Used for Internal PLL off-state mode). 4 MITSUBISHI ELECTRIC December 2000 PARIERRO 50ohm M69897VP Figure 7 Single-Ended PECL Output DC Termination R1 0.1 F PARIERRO 330ohm M69897VP R2 R1xR2/(R1+R2) = 50ohm Figure 8 Single-Ended PECL Output AC Termination SCLKOP/ SDOP/ PCLKOP 50ohm SCLKON/ SDON/ PCLKON 50ohm M69897VP Figure 9 Differential PECL Output DC Termination 5 MITSUBISHI ELECTRIC December 2000 R1 SDOP/ PCLKOP 330ohm 0.1 F R2 R1 0.1 F SDON/ PCLKON 330ohm R2 M69897VP R1xR2/(R1+R2) = 50ohm Figure 10 Differential PECL Output AC Termination R1 100 pF SCLKOP 330ohm R2 R1 100 pF SCLKON 330ohm R2 M69897VP R1xR2/(R1+R2) = 50ohm Figure 11 Differential PECL Output AC Termination for 2.488 GHz Clock Output 6 MITSUBISHI ELECTRIC December 2000 VH VL Single-Ended Swing = VH - VL VH VL Differential Swing = VH - VL Figure 12 Voltage Swing Table 9 AC Characteristics SYMBOL DESCRIPTION Serial Clock Rate TDS TDH TD S 2 TDH2 Parallel Data Setup Time wrt PCLKIP Parallel Data Hold Time wrt PCLKIP Parallel Data Setup Time wrt PCLKOP Parallel Data Hold Time wrt PCLKOP Parallel Clock Input Duty Cycle Parallel Clock Output Duty Cycle Serial Clock Output to Serial Data Output Delay Serial Clock Output Rise and Fall Time Serial Data Output Rise and Fall Time Parallel Clock Input Rise and Fall Time Parallel Data Input Rise and Fall Time Parallel Data Input and Parity Input Skew 1. 20% - 80% 1 1 1 1 MIN TYP 2.488 MAX UNITS GHz ns ns ns ns 1.0 1.0 1.0 1.0 40 45 -50 100 120 1.0 2.0 1.5 60 55 50 % % ps ps ps ns ns ns PCLKIP TDS TDH PDI[15:0] Figure 13 Input Timing (SELPLL = "H") 7 MITSUBISHI ELECTRIC December 2000 PCLKOP TDS2 TDH2 PDI[15:0] Figure 14 Input Timing (SELPLL = "L") SCLKOP TSD SDOP/N D15 D14 D13 D1 D0 Figure 15 Output Timing Table 10 Input/Output Pin Assignment PIN NAME LPF_EXT1 LPF_EXT2 PDI[15:0] SCLKIP SCLKIN PCLKIP PCLKIN PARITYI SDOP SDON SCLKOP SCLKON PCLKOP PCLKON PARIERRO SELPLL NC LEVEL I/O PIN # 22 21 DESCRIPTION Single-Ended PECL Differential PECL - Loop filter pins. (See Figure 16.) I I Table 11 29 30 12 13 Received parallel data input. Serial reference clock input. ( Used for Internal PLL off-state mode only.) Reference clock input. Used for parity check. Differential serial data output. Differential PECL Single-Ended PECL Differential PECL I I 11 38 O 37 41 Differential serial clock output. Differential PECL O 40 52 51 Differential PECL Single-Ended PECL CMOS - O Differential parallel clock output. Parity error output. High: Internal PLL operating mode. No connect. Leave open. O I - 53 20 26,47,54 8 MITSUBISHI ELECTRIC December 2000 0.02 F LPF_EXT1 LPF_EXT2 Figure 16 External Loop Filte Table 11 Parity Check Condition PARITYI # of "High"s in PDI[15:0] Even Odd Even Odd PARIERRO High High Low Low High Low Low High Table 12 PDI Pin Assignment PIN NAME PDI0 PDI1 PDI2 PDI3 PDI4 PDI5 PDI6 PDI7 PIN # 55 56 57 58 59 60 61 62 PIN NAME PDI8 PDI9 PDI10 PDI11 PDI12 PDI13 PDI14 PDI15 PIN # 3 4 5 6 7 8 9 10 Table 13 Common Pin Assignment PIN NAME VDD 1 VDD 2 LEVEL 1.8 V 1.8 V 1.8 V PIN # 1, 14, 15, 17, 63 28, 31, 33, 36, 42, 44, 46, 50 DESCRIPTION Core power supply. I/O power supply. ANAVDD 25 2, 16, 18, 19, 27, 32, 34, Analog power supply. Ground. GND ANAGND GND GND 35, 39, 43, 45, 48, 49, 64 23, 24 Analog ground. 9 MITSUBISHI ELECTRIC December 2000 GND VDD2 PCLKON PCLKOP PARIERRO NC PDI0 PDI1 PDI2 PDI3 PDI4 PDI5 PDI6 PDI7 VDD1 GND 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 GND VDD2 SCLKIN SCLKIP VDD2 GND NC ANAVDD ANAGND ANAGND LPF_EXT1 LPF_EXT2 SELPLL GND GND VDD1 Figure 17 Pin Diagrams Figure 18 Package Information 10 MITSUBISHI ELECTRIC December 2000 |
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