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| 19-2216; Rev 0; 10/01 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package General Description The MAX9156 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between LVPECL and LVDS interfaces in systems that require minimum jitter, noise, power, and space. Ultra-low, 23ps p-p added deterministic jitter and 0.6psRMS added random jitter ensure reliable communication in high-speed links that are highly sensitive to timing errors, especially those incorporating clock-anddata recovery, PLLs, serializers, or deserializers. The MAX9156's switching performance guarantees a 200Mbps data rate, but minimizes radiated noise by guaranteeing 0.5ns minimum output transition time. The MAX9156 operates from a single +3.3V supply and consumes only 10mA supply current over a -40C to +85C temperature range. It is available in a tiny 6-pin SC70 package (half the size of a SOT23). Refer to the MAX9155 data sheet for a low-jitter, low-noise LVDS repeater in an SC70 package. o Tiny SC70 Package o Ultra-Low Jitter 23psp-p Added Deterministic Jitter (223-1 PRBS) 0.6psRMS Added Random Jitter o 0.5ns (min) Transition Time Minimizes Radiated Noise o 200Mbps Guaranteed Data Rate o Low 10mA Supply Current o Output Conforms to ANSI/EIA/TIA-644 LVDS Standard o High-Impedance Inputs and Outputs in Power-Down Mode Features MAX9156 Applications Digital Cross-Connects Add/Drop Muxes Network Switches/Routers Cellular Phone Base Stations DSLAMs Multidrop Buses PART MAX9156EXT-T Ordering Information TEMP. RANGE -40C to +85C PINPACKAGE 6 SC70-6 TOP MARK ABD Pin Configuration Typical Operating Circuit VCC 3.3V MAX9156 OUT+ IN+ LVPECL DRIVER ININ- 3 GND 4 IN+ OUTLVDS SIGNALS GND 2 5 VCC OUT- 1 TOP VIEW MAX9156 6 OUT+ SC70 ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package MAX9156 ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN+, IN- to GND.....................................................-0.3V to +4.0V OUT+, OUT- to GND .............................................-0.3V to +4.0V Short-Circuit Duration (OUT+, OUT-) .........................Continuous Continuous Power Dissipation (TA = +70C) 6-Pin SC70 (derate 3.1mW/C above +70C) ..............245mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C ESD Protection Human Body Model, IN+, IN-, OUT+, OUT- ....................8kV Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100 1%, |VID| = 0.05V to VCC, VCM = |VID / 2| to VCC - |VID / 2|, TA = -40C to +85C, unless otherwise noted. Typical values at VCC = +3.3V, TA = +25C.) (Notes 1, 2) PARAMETER LVPECL INPUT Differential Input High Threshold Differential Input Low Threshold Input Resistor Input Current Power-Off Input Current LVDS OUTPUT Differential Output Voltage Differential Output Voltage Offset (Common-Mode) Voltage Change in VOS for Complementary Output States Output High Voltage Output Low Voltage Differential Output Voltage Power-Off Output Leakage Current Differential Output Resistance Output Short Current POWER SUPPLY Supply Current ICC 10 15 mA VOD VOD VOS VOS VOH VOL VOD+ IOOFF RODIFF ISC IN+, IN- open VCC = 0 OUT+ = 3.6V, other output open OUT- = 3.6V, other output open 0.9 +250 -10 -10 100 Figure 2 Figure 2 Figure 2 Figure 2 1.125 250 360 0.008 1.25 0.005 1.44 1.08 +360 0.02 0.02 260 -5 -5 +450 10 10 400 -15 -15 450 25 1.375 25 1.6 mV mV V mV V V mV A mA VTH VTL RIN IIN+, IINIIN+, IINFigure 1 IN+ = 3.6V, IN- = 0 IN+ = 0, IN- = 3.6V VCC = 0, Figure 1 IN+ = 3.6V, IN- = 0 IN+ = 0, IN- = 3.6V -50 360 -10 -10 -10 -10 7 -7 1328 2.7 2.7 2.7 2.7 10 10 10 10 50 mV mV k A A SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = +3.6V or 0 VID = +50mV, OUT+ = GND VID = -50mV, OUT- = GND 2 _______________________________________________________________________________________ Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100 1%, CL = 10pF, |VID| = 0.15V to VCC, VCM = |VID / 2| to VCC - |VID / 2|, TA = -40C to +85C, unless otherwise noted. Typical values at VCC = +3.3V, TA = +25C.) (Notes 3, 4, 5) (Figures 3, 4) PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Added Deterministic Jitter (Notes 6, 11) Added Random Jitter (Notes 7, 11) Differential Part-to-Part Skew (Note 8) Differential Part-to-Part Skew (Note 9) Switching Supply Current Rise Time Fall Time Input Frequency (Note 10) SYMBOL tPHLD tPLHD tDJ tRJ tSKPP1 tSKPP2 ICCSW tTLH tTHL fMAX 0.5 0.5 100 11.3 0.66 0.64 200Mbps 223-1 PRBS data pattern fIN = 100MHz CONDITIONS MIN 1.3 1.3 TYP 2.0 2.0 23 0.6 0.17 MAX 2.8 2.8 100 2.9 0.6 1.5 18 1.0 1.0 UNITS ns ns psp-p psRMS ns ns mA ns ns MHz MAX9156 Note 1: All devices are 100% tested at TA = +25C. Limits over temperature are guaranteed by design and characterization. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VOD, and VOD. Note 3: Guaranteed by design and characterization. Note 4: Signal generator output (unless otherwise noted): frequency = 100MHz, 50% duty cycle, RO = 50, tR = 1.5ns, and tF = 1.5ns (0% to 100%). Note 5: CL includes scope probe and test jig capacitance. Note 6: Signal generator output for tDJ: VOD = 150mV, VOS = 1.2V, tDJ includes pulse (duty cycle) skew. Note 7: Signal generator output for tRJ: VOD = 150mV, VOS = 1.2V. Note 8: tSKPP1 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same supply voltage, input common-mode voltage, and ambient temperature. Note 9: tSKPP2 is the magnitude difference of any differential propagation delays between devices operating over rated conditions. Note 10: Device meets VOD DC specification and AC specifications while operating at fMAX. Note 11: Jitter added to the input signal. _______________________________________________________________________________________ 3 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package MAX9156 Typical Operating Characteristics (VCC = +3.3V, RL = 100 1%, CL = 10pF, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted. Signal generator output: frequency = 100MHz, 50% duty cycle, RO = 50, tR = 1.5ns, and tF = 1.5ns (0% to 100%), unless otherwise noted.) SUPPLY CURRENT VS. INPUT FREQUENCY MAX9156 toc01 SWITCHING SUPPLY CURRENT VS. TEMPERATURE MAX9156 toc02 OUTPUT SHORT-CIRCUIT CURRENT VS. SUPPLY VOLTAGE OUTPUT SHORT-CIRCUIT CURRENT (mA) MAX9156 toc03 21 18 SUPPLY CURRRENT (mA) 15 12 9 6 3 0 0 12.00 11.75 SUPPLY CURRENT (mA) 11.50 11.25 11.00 10.75 10.50 10.25 10.00 5.10 5.09 5.08 5.07 5.06 5.05 -40 -15 10 35 60 85 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (C) SUPPLY VOLTAGE (V) 25 50 75 100 125 150 175 200 225 250 INPUT FREQUENCY (MHz) OUTPUT LOW VOLTAGE VS. SUPPLY VOLTAGE MAX9156 toc04 OUTPUT HIGH VOLTAGE VS. SUPPLY VOLTAGE MAX9156 toc05 DIFFERENTIAL PROPAGATION DELAY VS. SUPPLY VOLTAGE DIFFERENTIAL PROPAGATION DELAY (ns) MAX9156 toc06 1.12 1.11 OUTPUT LOW VOLTAGE (V) 1.10 1.09 1.08 1.07 1.06 1.05 3.0 3.1 3.2 3.3 3.4 3.5 1.550 1.525 OUTPUT HIGH VOLTAGE (V) 1.500 1.475 1.450 1.425 1.400 1.375 1.350 2.1 tPHLD 2.0 1.9 tPLHD 1.8 1.7 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 3.6 SUPPLY VOLTAGE (V) DIFFERENTIAL PROPAGATION DELAY VS. TEMPERATURE MAX9156 toc07 TRANSITION TIME VS. SUPPLY VOLTAGE tTHL 725 TRANSITION TIME (ps) 700 675 650 625 600 575 tTLH MAX9156 toc08 2.5 DIFFERENTIAL PROPAGATION DELAY (ns) 750 2.3 2.1 tPHLD 1.9 tPLHD 1.7 1.5 -40 -15 10 35 60 85 TEMPERATURE (C) 550 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 4 _______________________________________________________________________________________ Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package MAX9156 Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100 1%, CL = 10pF, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted. Signal generator output: frequency = 100MHz, 50% duty cycle, RO = 50, tR = 1.5ns, and tF = 1.5ns (0% to 100%), unless otherwise noted.) TRANSITION TIME VS. TEMPERATURE MAX9156 toc09 DIFFERENTIAL OUTPUT VOLTAGE VS. LOAD RESISTOR DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9156 toc10 800 750 TRANSITION TIME (ps) 700 650 600 550 500 450 400 -40 -15 10 35 60 tTLH, tTHL 600 500 400 300 200 100 0 85 25 50 75 100 125 150 TEMPERATURE (C) LOAD RESISTOR () Pin Description PIN 1 2 3 4 5 6 NAME OUTGND ININ+ VCC OUT+ Ground Inverting LVPECL-Compatible Input Noninverting LVPECL-Compatible Input Power Supply. Bypass VCC to GND with a 0.01F ceramic capacitor. Noninverting LVDS Output FUNCTION Inverting LVDS Output Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium, as defined by the ANSI/ TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9156 is a 200Mbps LVDS translator intended for high-speed, point-to-point, low-power applications. The MAX9156 accepts differential LVPECL inputs and produces an LVDS output. The input voltage range includes signals from GND up to VCC, allowing interoperation with 3.3V LVPECL devices. The MAX9156 provides a high output when the inputs are open. See Table 1. Table 1. Function Table (Figure 2) INPUT, VID > 50mV < -50mV 50mV > VID > -50mV Open OUTPUT, VOD High Low Indeterminate High Note: VID = (IN+ - IN-), VOD = (OUT+ - OUT-) High = 450mV VOD 250mV Low = -250mV VOD -450mV _______________________________________________________________________________________ 5 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package MAX9156 Applications Information Supply Bypassing Bypass V CC with a high-frequency surface-mount ceramic 0.01F capacitor as close to the device as possible. match the differential characteristic impedance of the transmission line. Each line of a differential LVPECL link should be terminated through 50 to VCC - 2V or be replaced by the Thevinin equivalent. The LVDS output voltage level depends upon the differential characteristic impedance of the interconnect and the value of the termination resistance. The MAX9156 is guaranteed to produce LVDS output levels into 100. With the typical 3.6mA output current, the MAX9156 produces an output voltage of 360mV when driving a 100 transmission line terminated with a 100 termination resistor (3.6mA 100 = 360mV). For typical output levels with different loads, see the Differential Output Voltage vs. Load Resistor typical operating curve. Differential Traces Input and output trace characteristics affect the performance of the MAX9156. Use controlled-impedance differential traces. Ensure that noise couples as common mode by running the traces within a differential pair close together. Maintain the distance within a differential pair to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors The LVDS standards define signal levels for interconnect with a differential characteristic impedance and termination of 100. Interconnects with a characteristic impedance and termination of 90 to 132 impedance are allowed, but produce different signal levels (see Termination). LVPECL signals are typically specified for 50 singleended characteristic impedance interconnect terminated through 50 to VCC - 2V. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. TRANSISTOR COUNT: 401 PROCESS: CMOS Chip Information Termination For point-to-point LVDS links, the termination resistor should be located at the LVDS receiver input and 6 _______________________________________________________________________________________ Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package Test Circuits and Timing Diagrams VCC CL RIN IN+ INRIN CL OUT+ OUT50 50 OUTPULSE GENERATOR IN+ INRL OUT+ MAX9156 Figure 1. LVPECL Input Bias OUT+ Figure 3. Transition Time and Propagation Delay Test Circuit 1.25V 1.20V 1.25V 1.20V IN+ INVOD RL/2 VOS RL/2 OUT- Figure 2. DC Load Test Circuit INO (DIFFERENTIAL) IN+ tPLHD OUT- VCM = ((IN+) + (IN-))/2 VID O (DIFFERENTIAL) tPHLD O (DIFFERENTIAL) OUT+ O (DIFFERENTIAL) 80% O (DIFFERENTIAL) 80% O (DIFFERENTIAL) 20% VDIFF tTLH VDIFF = (OUT+) - (OUT-) tTHL 20% Figure 4. Transition Time and Propagation Delay Timing Diagram _______________________________________________________________________________________ 7 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package MAX9156 Package Information SC70, 6L.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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