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19-2616; Rev 0; 10/02
4-Port LVDS and LVTTL-to-LVDS Repeaters
General Description
The MAX9169/MAX9170 low-jitter, low-voltage differential signaling LVDS/LVTTL-to-LVDS repeaters are ideal for applications that require high-speed data or clock distribution while minimizing power, space, and noise. The devices accept a single LVDS (MAX9169) or LVTTL (MAX9170) input and repeat the input at four LVDS outputs. Each differential output drives 100, allowing point-to-point distribution of signals on transmission lines with 100 termination at the receiver input. The MAX9169 and MAX9170 are pin compatible with the SN65LVDS104 and SN65LVDS105, respectively, and offer improved pulse-skew performance. Ultra-low 150ps (max) pulse skew and 200psP-P (max) added deterministic jitter ensure reliable communication in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery or serializers and deserializers. The highspeed switching performance guarantees 630Mbps data rate and less than 120ps channel-to-channel skew over the 3.0V to 3.6V operating supply range. Supply current is 30mA (max) for the MAX9169, and 25mA (max) for the MAX9170. LVDS inputs and outputs conform to the ANSI EIA/TIA-644 standard. A fail-safe feature on the MAX9169 sets the output high when the input is undriven and open, terminated, or shorted. The MAX9169/MAX9170 are offered in 16-pin TSSOP and SO packages, and operate over an extended -40C to +85C temperature range. Refer to the MAX9130 data sheet for an LVDS line receiver in an SC70 package. o 150ps (max) Pulse Skew o 200psP-P (max) Added Deterministic Jitter at 630Mbps (223 - 1) PRBS Pattern o 8psRMS (max) Added Random Jitter o 120ps (max) Channel-to-Channel Skew o 630Mbps Data Rate o Conforms to ANSI EIA/TIA-644 LVDS Standard o 30mA (max) (MAX9169), 25mA (max) (MAX9170) Supply Current, a 15% Improvement vs. Competition o LVDS (MAX9169) or +5V Tolerant LVTTL/LVCMOS (MAX9170) Input Versions o Fail-Safe Circuit Sets Output High for Undriven Differential Input o Output Rated for 10pF Load o Individual Output Enables o Single 3.3V Supply o Improved Second Source of the SN65LVDS104 (MAX9169)/SN65LVDS105 (MAX9170) o 16-Pin SO and TSSOP Packages
Features
MAX9169/MAX9170
Ordering Information
PART MAX9169ESE MAX9169EUE TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 SO 16 TSSOP 16 SO 16 TSSOP INPUT LVDS LVDS LVTTL LVTTL
Applications
Point-to-Point Baseband Data Transmission Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects Network Switches/Routers Backplane Interconnect Clock Distribution
MAX9170ESE MAX9170EUE
Typical Application Circuit
LVDS
MAX9169
LVDS 100
1
100
Rx
BACKPLANE OR CABLE
MAX9130
4
100
Rx
MAX9180 MAX9130
Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.5V to +4V Inputs IN+, IN- to GND....................................................-0.5V to +4V IN, EN_ to GND ....................................................-0.5V to +6V Outputs OUT_+, OUT_- to GND.........................................-0.5V to +4V Continuous Power Dissipation (TA = +70C) 16-Pin SO (derate 8.7mW/C above +70C)................696mW 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C ESD Protection Human Body Model (MAX9169) (IN+, IN-, OUT_+, OUT_-) ..............................................16kV Human Body Model (MAX9170) (OUT_+, OUT_-) .............................................................10kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100 1%, EN_ = high, MAX9169 differential input voltage | VID | = 0.05V to 1.2V, LVDS input commonmode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, | VID | = 0.2V, VCM = 1.25V, TA = +25C for MAX9169. Typical values are at VCC = 3.3V, VIN = 0 or VCC, TA = +25C for MAX9170.) (Notes 1 and 2)
PARAMETER Differential Input High Threshold Differential Input Low Threshold Input Current (IN+ or IN-, Single Ended) Power-Off Input Current (IN+ or IN-, Single Ended) Input Current Power-Off Input Current Fail-Safe Input Resistor Input Capacitance Input High Voltage Input Low Voltage Input Current Input Capacitance (MAX9170) LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage Change in VOD Between Complementary Output States Steady-State Output Offset Voltage VOD VOD VOS Figures 3, 4, 6, 7 Figures 3, 4, 6, 7 Figures 2, 4, 5, 7, 8, 9 1.125 250 350 1.5 1.26 450 25 1.375 mV mV V SYMBOL VTH VTL IIN+, IINIINO+, IINOIIN+, IINIINO+, IINORIN1 RIN2 CIN VIH VIL IIH IIL CIN VIN = 2V to 5.5V VIN = 0 to 0.8V IN to GND (Note 3) 2.2 VIN = 0V, other input open, Figure 1 VIN = +2.4V, other input open, Figure 1 VCC = +1.5V, VIN = +2.4V, other input open, Figure 1 0.05V VID 0.6V, Figure 1 0.6V LVDS INPUTS (IN+, IN-) (MAX9169)
+5V TOLERANT LV TTL/LVCMOS INPUTS (IN, EN_)
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4-Port LVDS and LVTTL-to-LVDS Repeaters
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL = 100 1%, EN_ = high, MAX9169 differential input voltage | VID | = 0.05V to 1.2V, LVDS input commonmode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, | VID | = 0.2V, VCM = 1.25V, TA = +25C for MAX9169. Typical values are at VCC = 3.3V, VIN = 0 or VCC, TA = +25C for MAX9170.) (Notes 1 and 2)
PARAMETER Change in VOS Between Complementary Output States Peak-to-Peak Output Offset Voltage Output Voltage Fail-Safe Differential Output Voltage (MAX9169) High-Impedance Output Current Power-Off Output Current Output Short-Circuit Current Magnitude of Differential Output Short-Circuit Current Output Capacitance POWER SUPPLY DC, RL = 100, Figures 10, 13 Supply Current ICC 315MHz (630Mbps), RL = 100, Figures 10, 13 EN_ = low MAX9169 MAX9170 MAX9169 MAX9170 MAX9169 MAX9170 22 18 43 41 6.8 4.3 30 25 60 55 8.0 6.4 mA mA SYMBOL VOS VOS(P-P) VOH VOL VOD+ IOZ IOFF IOS IOSD CO CONDITIONS Figures 2, 4, 5, 7, 8, 9 Figures 8, 9 (Note 4) Figures 3, 4, 6, 7 Figures 3, 4, 6, 7 IN+, IN- open, undriven and shorted, or undriven and parallel terminated EN_ = low, VOUT_+ = +3.6V or 0, VOUT_- = +3.6V or 0 VCC = +1.5V, VOUT_+ = +3.6V or 0, VOUT_- = +3.6V or 0 VID = +50mV or -50mV, VOUT+ = 0 or VCC, VOUT- = 0 or VCC VID = +50mV or -50mV, VOD = 0 (Note 5) OUT_+ or OUT_- to GND (Note 6) 0.9 +250 -0.5 -0.5 -10 +350 0.01 0.01 5.8 5.8 3.6 +450 +0.5 +0.5 +10 10 MIN TYP 1.5 40 MAX 25 150 1.65 UNITS mV mV V mV A A mA mA pF
MAX9169/MAX9170
Disabled Supply Current
ICCZ
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4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100 1%, CL = 10pF, EN_ = high, MAX9169 differential input voltage | VID | = 0.15V to 1.2V, LVDS input common-mode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA = -40C to +85C, unless otherwise noted. Typical values are at | VID | = 0.2V, VCM = 1.25V, VCC = 3.3V, TA = +25C for MAX9169. Typical values are at VIN = 0 or VCC, VCC = 3.3V, TA = +25C for MAX9170.) (Notes 5, 7, and 8)
PARAMETER Rise Time Fall Time Added Deterministic Jitter Added Random Jitter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Pulse Skew tPLH - tPHL Pulse Skew tPLH - tPHL Channel-to-Channel Skew (Note 12) Differential Part-to-Part Skew (Note 13) Disable Time Enable Time SYMBOL tR tF tDJ tRJ tPHL tPLH tSKEW tSK(P) tSK(0) tSK(PP) tPHZ tPLZ tPZH tPZL Figures 10-15 Figures 10-15 (Note 9) (Note 10) Figures 10, 11, 13, 14 Figures 10, 11, 13, 14 Figures 10, 11, 13, 14 Figures 10, 12, 13, 15 (Note 11) MAX9169, Figures 10, 11, 12 MAX9170, Figures 13, 14, 15 MAX9169, Figures 10, 11, 12 MAX9170, Figures 13, 14, 15 High to high-Z, Figures 16-19 Low to high-Z, Figures 16-19 High-Z to high, Figures 16-19 High-Z to low, Figures 16-19 MAX9169 MAX9170 MAX9169 MAX9170 2.2 1.5 2.2 1.5 CONDITIONS MIN 0.6 0.6 TYP 0.8 0.8 110 6 3.5 2.6 3.5 2.6 40 40 25 15 0.28 0.19 11 11.8 2.3 5.8 MAX 1.2 1.2 200 8 4.2 3.2 4.2 3.2 250 150 120 100 1.2 1.2 15 15 10 10 UNITS ns ns ps ps ns ns ps ps ps ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Note 9:
Note 10:
Note 11: Note 12: Note 13:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and VOD. Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Signal generator output for IN+, IN-, or single-ended IN: VIN = 0.4 sin(4E6t) + 0.5. All input pulses are supplied by a generator having the following characteristics: tR or tF 1ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 10ns. Guaranteed by design and characterization. Signal generator output for OUT+ or OUT-: VIN = 0.4 sin(4E6t) + 0.5, EN_ = low. CL includes scope probe and test jig capacitance. Signal generator output for differential inputs IN+, IN- (unless otherwise noted): frequency = 50MHz, 49% to 51% duty cycle, RO = 50, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for single-ended input IN (unless otherwise noted): frequency = 50MHz, 49% to 51% duty cycle, RO = 50, VIH = VCC, VIL = 0V, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for MAX9169 tDJ: VOH = +1.3V, VOL = +1.1V, data rate = 630Mbps, 223 -1 PRBS, RO = 50, tR = 1.0ns and tF = 1.0ns (0% to 100%). Signal generator output for MAX9170 tDJ: VOH = VCC, VOL = 0V, data rate = 630Mbps, 223 -1 PRBS, RO = 50, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for MAX9169 tRJ: VOH = +1.3V, VOL = +1.1V, frequency = 315MHz, 50% duty cycle, RO = 50, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for MAX9170 tRJ: VOH = VCC, VOL = 0V, frequency = 315MHz, 50% duty cycle, RO = 50, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for MAX9169 tSK(P): VOH = +1.4V, VOL = +1.0V, RO = 50, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for MAX9170 tSK(P): VOH = +3.0, VOL = 0V, RO = 50, tR = 1.0ns, and tF = 1.0ns (0% to 100%). tSK(0) is the magnitude of the time difference between tPLH or tPHL of all drivers of a single device with all of their inputs connected together. tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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4-Port LVDS and LVTTL-to-LVDS Repeaters
Typical Operating Characteristics
(VCC = 3.3V, RL = 100, CL = 10pF, | VID | = 150mV, VCM = 1.25V, fIN = 50MHz, TA = +25C, unless otherwise noted.)
MAX9169 SUPPLY CURRENT vs. FREQUENCY
MAX9169/70 toc01
MAX9169/MAX9170
MAX9170 SUPPLY CURRENT vs. FREQUENCY
MAX9169/70 toc02
DIFFERENTIAL OUTPUT AMPLITUDE vs. FREQUENCY
DIFFERENTIAL OUTPUT AMPLITUDE (mV)
MAX9169/70 toc03
50 4 CHANNELS ACTIVE 40 SUPPLY CURRENT (mA) 3 CHANNELS ACTIVE 2 CHANNELS ACTIVE 30
40
4 CHANNELS ACTIVE 3 CHANNELS ACTIVE
360
SUPPLY CURRENT (mA)
30
2 CHANNELS ACTIVE
320
VCC = 3.6V
20
280 VCC = 3.3V 240 VCC = 3.0V
20 1 CHANNEL ACTIVE ALL CHANNELS DISABLED 0 0 45 90 135 180 225 270 315 FREQUENCY (MHz)
10
10
1 CHANNEL ACTIVE ALL CHANNELS DISABLED
0 0 45 90 135 180 225 270 315 FREQUENCY (MHz)
200 0 45 90 135 180 225 270 315 FREQUENCY (MHz)
TRANSITION TIME vs. TEMPERATURE
MAX9169/70 toc04
MAX9169 PROPAGATION DELAY vs. TEMPERATURE
MAX9169/70 toc05
MAX9170 PROPAGATION DELAY vs. TEMPERATURE
MAX9169/70 toc06
840 820 TRANSITION TIME (ns) 800 tr 780 760 740 720 -40 -15 10 35 60 tf
3.8 3.7 PROPAGATION DELAY (ns) 3.6 tPHL 3.5 tPLH 3.4 3.3 3.2
2.9
PROPAGATION DELAY (ns)
2.8
2.7 tPLH tPHL 2.6
2.5
2.4 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
85
TEMPERATURE (C)
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9169/70 toc07
TRANSITION TIME vs. CAPACITIVE LOAD
MAX9169/70 toc08
600
950
500
900 TRANSITION TIME (ps)
400
850 tr
300
800
200
750
tf
100 50 75 100 LOAD RESISTOR () 125 150
700 5 7 9 11 13 15 CAPACITIVE LOAD (pF)
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5
4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
Pin Description
PIN MAX9169 1 MAX9170 1 NAME FUNCTION OUT1+/OUT1- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN1 high to enable OUT1+/OUT1-. Set EN1 low to disable OUT1+/OUT1- (high-impedance mode). Integrated pulldown to GND. OUT2+/OUT2- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN2 high to enable OUT2+/OUT2-. Set EN2 low to disable OUT2+/OUT2- (high-impedance mode). Integrated pulldown to GND. OUT3+/OUT3- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN3 high to enable OUT3+/OUT3-. Set EN3 low to disable OUT3+/OUT3- (high-impedance mode). Integrated pulldown to GND. Power-Supply Voltage. Bypass with 0.1F and 0.001F capacitors to ground. Ground Noninverting Differential LVDS Input Inverting Differential LVDS Input OUT4+/OUT4- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN4 high to enable OUT4+/OUT4-. Set EN4 low to disable OUT4+/OUT4- (high-impedance mode). Integrated pulldown to GND. Inverting Differential LVDS Output Noninverting Differential LVDS Output Inverting Differential LVDS Output Noninverting Differential LVDS Output Inverting Differential LVDS Output Noninverting Differential LVDS Output Inverting Differential LVDS Output Noninverting Differential LVDS Output Data Input, 5V Tolerant LVTTL/LVCMOS. Integrated pulldown to GND. No Connection
EN1
2
2
EN2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- --
3 4 5 -- -- 8 9 10 11 12 13 14 15 16 6 7
EN3 VCC GND IN+ INEN4 OUT4OUT4+ OUT3OUT3+ OUT2OUT2+ OUT1OUT1+ IN N.C.
Table 1. MAX9169 Input/Output Functions
INPUT VID = VIN+ - VINX +50mV -50mV Open Undriven short Undriven parallel terminated EN_ Low or open High High High High High OUTPUT VOD High-Z High Low High High High
Table 2. MAX9170 Input/Output Functions
INPUT VIN X High Low Open EN_ Low or open High High High OUTPUT VOD High-Z High Low Low
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4-Port LVDS and LVTTL-to-LVDS Repeaters
Detailed Description
LVDS is a signaling method for point-to-point and multidrop data communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9169/MAX9170 are 630Mbps, four-port repeaters for high-speed, low-power applications. The MAX9169 accepts an LVDS input and has a fail-safe input circuit. The MAX9170 features a +5V tolerant single-ended LVTTL/LVCMOS input. Both devices repeat the input at four LVDS outputs. The MAX9169 detects differential signals as low as 50mV and as high as 1.2V over a |VID|/2 to 2.4V - |VID|/2 common-mode range. The MAX9170's +5V tolerant LVTTL/LVCMOS input includes circuitry to hold the decision threshold constant at +1.5V over temperature and supply voltage. The MAX9169/MAX9170 outputs use a current-steering configuration to generate a 2.5mA to 4.5mA output current. This current-steering approach induces less ground bounce and shoot-through current, enhancing noise margin and system speed performance. The outputs are short-circuit current limited and are high impedance when disabled or when the device is not powered. The MAX9169/MAX9170 current-steering output requires a resistive load to terminate the signal and complete the transmission loop. Because the devices switch the direction of current flow and not voltage levels, the output voltage swing is determined by the value of the termination resistor multiplied by the output current. With a typical 3.5mA output current, the MAX9169/MAX9170 produce a 350mV output voltage when driving a transmission line terminated with a 100 resistor (3.5mA 100 = 350mV). Logic states are determined by the direction of current flow through the termination resistor. Fail-Safe Circuitry The fail-safe feature of the MAX9169 sets the outputs high when the differential input is: * Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the outputs and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when an LVDS driver output is in high impedance. A shorted input can occur because of cable failure.
VCC
MAX9169/MAX9170
MAX9169
RIN2 COMPARATOR
VCC - 0.3V IN+ RIN1/2
OUT1+ OUT1-
RIN1/2 IN-
RECEIVER OUT4+ OUT4-
Figure 1. MAX9169 Input Fail-Safe Circuit
When the input is driven with signals meeting the LVDS standard, the input common-mode voltage is less than V CC - 0.3V and the fail-safe circuit is not activated (Figure 1). If the input is open, undriven and shorted, or undriven and parallel terminated, an internal resistor in the fail-safe circuit pulls both the inputs above VCC 0.3V, activating the fail-safe circuit and forcing the outputs high.
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the VCC pin. Use multiple parallel vias to minimize parasitic inductance.
Traces, Cables, and Connectors
The characteristics of differential input and output connections affect the performance of the MAX9169/ MAX9170. Use controlled-impedance traces, cables, and connectors with matched characteristic impedance. Ensure that noise couples as common mode by running the traces of a differential pair close together. Reduce within-pair skew by matching the electrical length of the traces of a differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between traces of a differential pair to avoid discontinuities in differen7
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4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
tial impedance. Minimize the number of vias to further prevent impedance discontinuities. Avoid the use of unbalanced cables, such as ribbon cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. date various types of interconnect. The termination resistor at the driven receiver should match the differential characteristic impedance of the interconnect and be located close to the receiver input. Use a 1% surface-mount termination resistor.
Board Layout
A four-layer PC board with separate layers for power, ground, and LVDS signals is recommended. Keep LVTTL/LVCMOS signals separated from the LVDS signals to prevent crosstalk to the LVDS lines.
Termination
The MAX9169/MAX9170 LVDS outputs are specified for a 100 load but can drive 90 to 132 to accommo-
Test Circuits and Timing Diagrams
OUT1+
MAX9169
10pF 50 VOS 50 50 10pF IN+ IN10pF 50 OUT410pF VOS 50 OUT4+ OUT1-
PULSE GENERATOR
50
Figure 2. MAX9169 Output Offset Voltage Test Circuit
8
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4-Port LVDS and LVTTL-to-LVDS Repeaters
Test Circuits and Timing Diagrams (continued)
MAX9169/MAX9170
MAX9169
OUT1+ VOD OUT1100
3.75k
0V VTEST 2.4V 3.75k 50
PULSE GENERATOR
IN+ INOUT4+ VOD 50 OUT4100 0V VTEST 2.4V 3.75k 3.75k
Figure 3. MAX9169 Differential Output Voltage Test Circuit
VCM = ((VIN+) - (VIN-)) / 2 IN0V IN+ DIFFERENTIAL VID
OUT_VOS(-) VOS(+) VOS(-)
VOH
OUT_+ VOS = | (VOS(+)) - (VOS(-)) |
VOL
VOD_+ VOD_(OUT_+) - (OUT_-) VOD = | (VOD_+) - (VOD_-) | VOD = 0V
Figure 4. MAX9169 Output DC Parameters
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4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
OUT1+
MAX9170
10pF 50 VOS 50 OUT110pF IN 50 50 10pF 50 OUT410pF VOS OUT4+
PULSE GENERATOR
Figure 5. MAX9170 Output Offset Voltage Test Circuit
MAX9170
OUT1+ VOD OUT1100
3.75k
0V VTEST 2.4V 3.75k
PULSE GENERATOR 50
IN OUT4+ VOD OUT4100 0V VTEST 2.4V 3.75k 3.75k
Figure 6. MAX9170 Differential Output Voltage Test Circuit
10
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4-Port LVDS and LVTTL-to-LVDS Repeaters
Test Circuits and Timing Diagrams (continued)
VIH IN VIL
MAX9169/MAX9170
OUT_VOS(-) VOS(+) VOS(-)
VOH
OUT_+ VOS = | (VOS(+)) - (VOS(-)) |
VOL
VOD_+ VOD_(OUT_+) - (OUT_-) VOD = | (VOD_+) - (VOD_-) | VOD = 0V
Figure 7. MAX9170 LVDS Output DC Parameters
INVID = 50mV IN+ VOS VOS(+) VOS(-) VOS(P-P) VOS(-)
1.25V
1.20V
Figure 8. MAX9169 Output Offset Voltage Waveforms
3V IN 0V VOS VOS(+) VOS(-) VOS(P-P) VOS(-)
Figure 9. MAX9170 Output Offset Voltage Waveforms
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11
4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
CL 10pF OUT1+ RL 100 OUT150 CL 10pF
MAX9169
PULSE GENERATOR
IN+ IN-
CL 10pF OUT4+ RL 100
50
CL 10pF
OUT4-
Figure 10. MAX9169 Propagation Delay and Transition Time Test Circuit
INVCM IN+ tPLH 80% 0V 20% tR tF tPHL 80% 0V 20% VOD = (VOUT_+) - (VOUT_-) 0V DIFFERENTIAL VID VCM = (VIN+) - (VIN-) 2
VOD
Figure 11. MAX9169 Propagation Delay and Transition Time Waveforms
12
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4-Port LVDS and LVTTL-to-LVDS Repeaters
Test Circuits and Timing Diagrams (continued)
INVCM = 1.2V IN+ tPLH 80% 0V 20% tR tF VOD = (VOUT_+) - (VOUT_-) tPHL 80% 0V 20% VCM = 1.2V 1.0V 1.4V
MAX9169/MAX9170
VOD
Figure 12. MAX9169 Propagation Delay and Transition Time Waveforms, tSK(p)
MAX9170
CL 10pF OUT1+ RL 100 OUT1CL 10pF
PULSE GENERATOR 50
IN
CL 10pF OUT4+ RL 100 CL 10pF OUT4-
Figure 13. MAX9170 Propagation Delay and Transition Time Test Circuit
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4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
VCC IN VCC/2 VCC/2 0V tPLH 80% 0V 20% tR tF VOD = (VOUT_+) - (VOUT_-) tPHL 80% 0V 20%
VOD
Figure 14. MAX9170 Propagation Delay and Transition Time Waveforms
3.0V IN 1.5V 1.5V 0V tPLH 80% 0V 20% tR tF VOD = (VOUT_+) - (VOUT_-) tPHL 80% 0V 20%
VOD
Figure 15. MAX9170 Propagation Delay and Transition Time Waveforms, tSK(p)
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4-Port LVDS and LVTTL-to-LVDS Repeaters
Test Circuits and Timing Diagrams (continued)
MAX9169/MAX9170
MAX9169
1.25V 1.20V 1.25V 1.20V IN+ INCL 10pF CL 10pF OUT_+ 50
50 OUT_-
1.2V
PULSE GENERATOR
EN_
50
Figure 16. MAX9169 Enable and Disable Time Test Circuit
MAX9170
CL 10pF 2.0V 0.8V CL 10pF IN 50 OUT_OUT_+ 50
1.2V
PULSE GENERATOR
EN_
50
Figure 17. MAX9170 Enable and Disable Time Test Circuit
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4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
EN_ 1.5V 1.5V OV tPHZ tPZH 3V
~1.4V
VOUT_+ WHEN VID = +50mV VOUT_- WHEN VID = -50mV 1.25V 1.25V 1.2V 1.2V VOUT_+ WHEN VID = -50mV VOUT_- WHEN VID = +50mV tPLZ 1.15V tPZL 1.15V
~1.0V
Figure 18. MAX9169 Enable and Disable Time Waveforms
EN_ 1.5V 1.5V
3V
OV tPHZ tPZH
~1.4V
VOUT_+ WHEN VIN = 2.0V VOUT_- WHEN VIN = 0.8V 1.25V 1.25V 1.2V 1.2V VOUT_+ WHEN VIN = 0.8V VOUT_- WHEN VIN = 2.0V tPLZ 1.15V tPZL 1.15V
~1.0V
Figure 19. MAX9170 Enable and Disable Time Waveforms
16
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
Pin Configurations
TOP VIEW
MAX9169/MAX9170
MAX9169
EN1 1 EN2 2 EN3 3 VCC 4 GND 5 IN+ 6 IN- 7 EN4 8 16 15 14 13 12 11 10 9 OUT1+ OUT1OUT2+ OUT2OUT3+ OUT3OUT4+ OUT4EN1 1 EN2 2 EN3 3 VCC 4 GND 5 IN 6 N.C. 7 EN4 8
MAX9170
16 15 14 13 12 11 10 9 OUT1+ OUT1OUT2+ OUT2OUT3+ OUT3OUT4+ OUT4-
TSSOP/SO
TSSOP/SO
Chip Information
TRANSISTOR COUNT: 1187 PROCESS: CMOS
______________________________________________________________________________________
17
4-Port LVDS and LVTTL-to-LVDS Repeaters MAX9169/MAX9170
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
18
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9169/MAX9170
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
16L SOIC.EPS

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