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| MWS5114 March 1997 1024-Word x 4-Bit LSI Static RAM Description The MWS5114 is a 1024 word by 4-bit static random access memory that uses the ion-implanted silicon gate complementary MOS (CMOS) technology. It is designed for use in memory systems where low power and simplicity in use are desirable. This type has common data input and data output and utilizes a single power supply of 4.5V to 6.5V. The MWS5114 is supplied in 18 lead, hermetic, dual-in-line sidebrazed ceramic packages (D suffix) and in 18 lead dualin-line plastic packages (E suffix). Features * Fully Static Operation * Industry Standard 1024 x 4 Pinout (Same as Pinouts for 6514, 2114, 9114, and 4045 Types) * Common Data Input and Output * Memory Retention for Standby Battery Voltage as Low as 2V Min * All Inputs and Outputs Directly TTL Compatible * Three-State Outputs * Low Standby and Operating Power Ordering Information 200ns MWS5114E3 MWS5114D3 MWS5114D3X 250ns MWS5114E2 MWS5114E2X MWS5114D2 300ns MWS5114E1 MWS5114D1 TEMPERATURE RANGE 0oC to +70oC 0oC to +70oC PACKAGE PDIP Burn-In SBDIP Burn-In PKG. NO. E18.3 E18.3 D18.3 D18.3 Pinout MWS5114 (PDIP, SBDIP) TOP VIEW A6 A5 A4 A3 A0 A1 A2 CS VSS 1 2 3 4 5 6 7 8 9 18 VDD 17 A7 16 A8 15 A9 14 I/O1 13 I/O2 12 I/O3 11 I/O4 10 WE OPERATIONAL MODES FUNCTION Read Write Not Selected CS 0 0 1 WE 1 0 X DATA PINS Output: Dependent on data Input High Impedance CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 1325.2 6-160 MWS5114 Functional Block Diagram A4 VDD A5 VSS MEMORY ARRAY 64 ROWS 64 COLUMNS A6 ROW SELECT A7 A8 A9 I/O1 INPUT DATA CONTROL COLUMN I/O CIRCUITS COLUMN SELECT I/O2 I/O3 I/O4 A0 A1 A2 A3 CS ENABLE WE 6-161 MWS5114 Absolute Maximum Ratings DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA Thermal Information Thermal Resistance (Typical) JA (oC/W) JC (oC/W) Plastic DIP Package . . . . . . . . . . . . . . 75 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 75 20 Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . +265oC Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS ALL TYPES PARAMETER DC Operating Voltage Range Input Voltage Range MIN 4.5 VSS MAX 6.5 VDD UNITS V V Static Electrical Specifications At TA = 0oC to +70oC, VDD = 5%, Except as Noted LIMITS MWS5114-3 MWS5114-2 (NOTE 1) TYP 75 MWS5114-1 (NOTE 1) TYP 75 CONDITIONS PARAMETER Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Leakage Current (Note 2) Operating Current (Note 3) SYMBOL IDD VO (V) - VIN (V) 0, 5 VDD (V) 5 MIN - (NOTE 1) TYP 75 MAX 100 MIN - MAX 100 MIN - MAX 250 UNITS A IOL 0.4 0, 5 5 2 4 - 2 4 - 2 4 - mA IOH 4.6 0, 5 5 -0.4 -1 - -0.4 -1 - -0.4 -1 - mA VOL - 0, 5 5 - 0 0.1 - 0 0.1 - 0 0.1 V VOH - 0, 5 5 4.9 5 - 4.9 5 - 4.9 5 - V VIL 0.5, 4.5 0.5, 4.5 - - 5 - 1.2 0.8 - 1.2 0.8 - 1.2 0.8 V VIH - 5 2.4 - - 2.4 - - 2.4 - - V IIN 0, 5 5 - 0.1 5 - 0.1 5 - 0.1 5 A IDD1 - 0, 5 5 - 4 8 - 4 8 - 4 8 mA 6-162 MWS5114 Static Electrical Specifications At TA = 0oC to +70oC, VDD = 5%, Except as Noted (Continued) LIMITS MWS5114-3 VO (V) 0, 5 VIN (V) 0, 5 VDD (V) 5 (NOTE 1) TYP 0.5 MWS5114-2 (NOTE 1) TYP 0.5 MWS5114-1 (NOTE 1) TYP 0.5 CONDITIONS PARAMETER Three-State Output Leakage Current (Note 4) Input Capacitance Output Capacitance NOTES: SYMBOL IOUT MIN - MAX 5 MIN - MAX 5 MIN - MAX 5 UNITS A CIN - - - - 5 7.5 - 5 7.5 - 5 7.5 pF COUT - - - - 10 15 - 10 15 - 10 15 pF 1. Typical values are for TA = 25oC and nominal VDD . 2. All inputs in parallel. 3. Outputs open circuited; cycle time = 1s. 4. All outputs in parallel. 6-163 MWS5114 Dynamic Electrical Specifications at TA = 0oC to +70oC, VDD = 5V 5%, Input tR, tF = 10ns; CL = 50pF and 1 TTL Load LIMITS MWS5114-3 (NOTE 1) MIN (NOTE 2) TYP MWS5114-2 (NOTE 1) MIN (NOTE 2) TYP MWS5114-1 (NOTE 1) MIN (NOTE 2) TYP PARAMETER SYMBOL MAX MAX MAX UNITS READ CYCLE TIMES (FIGURE 1) Read Cycle Access from Address Chip Selection to Output Valid Chip Selection to Output Active Output Three-State from Deselection Output Hold from Address Change tRC tAA 200 160 160 200 250 200 200 250 300 250 250 300 ns ns tCO - 110 150 - 150 200 - 200 250 ns tCX 20 100 - 20 100 - 20 100 - ns tOTD - 75 125 - 75 125 - 75 125 ns tOHA 50 100 - 50 100 - 50 100 - ns WRITE CYCLE TIMES (FIGURE 2) Write Cycle Write Write Release Address to Chip Select Setup Time Address to Write Setup Time Data to Write Setup Time Data Hold from Write NOTES: 1. Time required by a limit device to allow for the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. tWC tW tWR tACS 200 125 50 0 160 100 40 0 250 150 50 0 200 120 40 0 300 200 50 0 220 140 40 0 ns ns ns ns tAW 25 20 - 50 40 - 50 40 - ns tDSU 75 50 - 75 50 - 75 50 - ns tDH 30 10 - 30 10 - 30 10 - ns 6-164 MWS5114 tRC tAA ADDRESS CS tCO tCX tOTD tOHA ACTIVE VALID DOUT NOTE: 1. WE is high during the Read Cycle. Timing measurement reference level is 1.5V. FIGURE 1. READ CYCLE TIMING WAVEFORMS tWC ADDRESS tACS CS tWR tAW WE tW tDSU tDH DIN DON'T CARE VALID NOTE: 1. WE is low during the Write Cycle. Timing measurement reference level is 1.5V. FIGURE 2. WRITE CYCLE TIMING WAVEFORMS Data Retention Specifications at TA = 0oC to +70oC; See Figure 3 TEST CONDITIONS LIMITS ALL TYPES PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current MWS5114-3 MWS5114-2 MWS5114-1 Chip Deselect to Data Retention Time Recovery to Normal Operation Time VDD to VDR Rise and Fall Time NOTE: SYMBOL VDR IDD VDR (V) 2 2 2 VDD (V) 5 5 5 MIN 2 300 300 1 (NOTE 1) TYP 25 25 60 - MAX 50 50 125 - UNITS V A A A ns ns s tCDR tRC tR, tF 2 1. Typical Values are for TA = 25oC and nominal VDD. 6-165 MWS5114 DATA RETENTION MODE VDD 0.95 VDD VDR tCDR tF VIH VIL VDR tR VIH VIL tRC 0.95 VDD CS FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6-166 |
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