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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33883/D Rev 6.0, 01/2004
33883 H-Bridge Gate Driver IC
The 33883 is an H-bridge gate driver (also known as a full-bridge predriver) IC with integrated charge pump and independent high- and low-side gate driver channels. The gate driver channels are independently controlled by four separate input terminals, thus allowing the device to be optionally configured as two independent high-side gate drivers and two independent low-side gate drivers. The low-side channels are referenced to ground. The high-side channels are floating.
H-BRIDGE GATE DRIVER IC
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The gate driver outputs can source and sink up to 1.0 A peak current pulses, permitting large gate-charge MOSFETs to be driven and/or high Pulse Width Modulation (PWM) frequencies to be utilized. A linear regulator is incorporated, providing a 15 V typical gate supply to the low-side gate drivers. Features * VCC Operating Voltage Range from 5.5 V up to 55 V * VCC2 Operating Voltage Range from 5.5 V up to 28 V * * * * * * * CMOS/LSTTL Compatible I/O 1.0 A Peak Gate Driver Current Built-In High-Side Charge Pump Undervoltage Lockout (UVLO) Overvoltage Lockout (OVLO) Global Enable with <10 A Sleep Mode Supports PWM up to 100 kHz
DW SUFFIX CASE 751D-06 20-TERMINAL SOICW
ORDERING INFORMATION
Device MC33883DW/R2 Temperature Range (TA) -40C to 125C Package 20 SOICW
33883 Simplified Application Diagram Simplified Application Diagram
VBAT VBOOST
33883
VCC VCC2 G_EN C1 C2 MCU CP_OUT LR_OUT GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2 IN_HS1 IN_LS1 IN_HS2 IN_LS2 SRC_HS2 GATE_LS2 GND DC Motor
(c) Motorola, Inc. 2004
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CCP C1 VCC, VCC2 Undervoltage/ Overvoltage Detection VCC VCC VDD EN GND G_EN GND2 VCC2 VCC2 EN Linear Reg +5.0 V +14.5 V LR_OUT Charge Pump C1 C2 VPOS CP_OUT VDD VCC C2 VCC2 VCC2 5.5 V- 28 V VCC CCP_OUT 5.5 V - 55 V
CP_OUT CLR_OUT LR_OUT
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GND GND_A GND2
HIGH- AND LOW-SIDE CONTROL WITH CHARGE PUMP
BRG_EN IN_HS1 TSD1 Control and Logic VDD /VPOS Level Shift Pulse Generator
VCC
CP_OUT
OUT
IN Output
Driver
GATE_HS1 SRC_HS1
HIGH-SIDE CHANNEL BRG_EN IN_LS1 TSD1 Control and Logic
TSD1 Thermal Shutdown
LR_OUT
VDD /VCC Level Shift Pulse Generator IN Output
Driver
OUT
GATE_LS1
LOW-SIDE CHANNEL
GND1
BRG_EN IN_HS2 TSD2 Control and Logic VDD /VPOS Level Shift Pulse Generator
VCC
CP_OUT
OUT GATE_HS2 SRC_HS2
IN Output
Driver
HIGH-SIDE CHANNEL BRG_EN IN_LS2 TSD2 Control and Logic VDD /VCC Level Shift Pulse Generator
TSD2 Thermal Shutdown
LR_OUT
IN Output
Driver
OUT
GATE_LS2
LOW-SIDE CHANNEL
GND2
GND1 GND2
GND_A
Figure 1. 33883 Simplified Internal Block Diagram
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VCC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
G_EN SRC_HS2 GATE_HS2 IN_HS2 IN_LS2 GATE_LS2 GND2 C1 GND_A VCC2
C2
CP_OUT SRC_HS1 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 GND1 LR_OUT
TERMINAL FUNCTION DESCRIPTION
Terminal Terminal Name VCC Formal Name Supply Voltage 1 Charge Pump Capacitor Charge Pump Out Source 1 Output High Side Gate 1 Output High Side Input High Side 1 Input Low Side 1 Gate 1 Output Low Side Ground 1 Linear Regulator Output Supply Voltage 2 Analog Ground Charge Pump Capacitor Ground 2 Gate 2 Output Low Side Input Low Side 2 Input High Side 2 Gate 2 Output High Side Source 2 Output High Side Global Enable Device power supply 1. External capacitor for internal charge pump. External reservoir capacitor for internal charge pump. Source of high-side 1 MOSFET Gate of high-side 1 MOSFET. Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH). Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH). Gate of low-side 1 MOSFET. Device ground 1. Output of internal linear regulator. Device power supply 2. Device analog ground. External capacitor for internal charge pump. Device ground 2. Gate of low-side 2 MOSFET. Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH). Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH). Gate of high-side 2 MOSFET. Source of high-side 2 MOSFET. Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN logic LOW = Sleep Mode). Definition
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
C2
CP_OUT SRC_HS1 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A C1 GND2 GATE_LS2 IN_LS2 IN_HS2 GATE_HS2 SRC_HS2 G_EN
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Supply Voltage 1 Supply Voltage 2 (Note 1) Linear Regulator Output Voltage High-Side Floating Supply Absolute Voltage High-Side Floating Source Voltage High-Side Source Current from CP_OUT in Switch ON State High-Side Gate Voltage Symbol VCC VCC2 VLR_OUT VCP_OUT VSRC_HS IS VGATE_HS VGATE_HS - VSRC_HS VCP_OUT - VGATE_HS VGATE_LS VG_EN VIN VC1 VC2 Value -0.3 to 65 -0.3 to 35 -0.3 to 18 -0.3 to 65 -1.0 to 65 250 -0.3 to 65 -0.3 to 20 -0.3 to 65 -0.3 to 17 -0.3 to 35 -0.3 to 10 -0.3 to VLR_OUT -0.3 to 65 Unit V V V V V mA V V V V V V V V V VESD1 VESD2 PD RJA TJ TSTG TSOLDER 1500 130
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High-Side Gate Source Voltage High-Side Floating Supply Gate Voltage Low-Side Gate Voltage Wake-Up Voltage Logic Input Voltage Charge Pump Capacitor Voltage Charge Pump Capacitor Voltage ESD Voltage Human Body Model on All Pins (VCC and VCC2 as Two Power Supplies) (Note 2) Machine Model (Note 3) Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ 25C Thermal Resistance (Junction to Ambient) Operating Junction Temperature Storage Temperature Terminal Soldering Temperature (Note 4)
1.25 100 -40 to 150 -65 to 150 240
W C/W C C C
Notes 1. VCC2 can sustain load dump pulse of 40 V, 400 ms, 2.0 . 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 ). 3. 4. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 ). Terminal soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values for TA = 25C and min/max values for TA = -40C to 125C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
OPERATING CONDITIONS
Supply Voltage 1 for Output High-Side Driver and Charge Pump Supply Voltage 2 for Linear Regulation High-Side Floating Supply Absolute Voltage VCC VCC2 VCP_OUT 5.5 5.5 VCC+4 - - - 55 28 VCC +11 but < 65 V V V
LOGIC
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Logic 1 Input Voltage (IN_LS and IN_HS) Logic 0 Input Voltage (IN_LS and IN_HS) Logic 1 Input Current VIN = 5.0 V Wake-Up Input Voltage (G_EN) Wake-Up Input Current (G_EN) VG_EN = 14 V Wake-Up Input Current (G_EN) VG_EN = 28 V
VIH VIL IIN+
2.0 -
- -
10 0.8
V V A
200 VG_EN IG_EN - IG_EN2 - 4.5
- 5.0
1000 VCC2 500 mA V A
200
-
1.5
LINEAR REGULATOR
Linear Regulator VLR_OUT @ VCC2 from 15 V to 28 V, ILOAD from 0 mA to 20 mA VLR_OUT @ ILOAD = 20 mA VLR_OUT @ ILOAD = 20 mA, VCC2 = 5.5 V, VCC = 5.5 V VLR_OUT 12.5 VCC2 -1.5 4.0 - - - 16.5 - - V
CHARGE PUMP
Charge Pump Output Voltage, Reference to VCC VCC = 12 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC = 12 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F VCC2 = VCC = 5.5 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC2 = VCC = 5.5 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F VCC = 55 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC = 55 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F Peak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see Figure 11, page 14) Minimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages (see Figure 11, page 14) IC1 VC1min VCP_OUT 7.5 7.0 2.3 1.8 7.5 7.0 - - - - - - - - - - - - A -2.0 -1.5 - - 2.0 V - V
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values for TA = 25C and min/max values for TA = -40C to 125C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY VOLTAGE
Quiescent VCC Supply Current VG_EN = 0 V and VCC = 55 V VG_EN = 0 V and VCC = 12 V Operating VCC Supply Current (Note 5) VCC = 55 V and VCC2 = 28 V VCC = 12 V and VCC2 = 12 V IVCCop - - IVCClog - IVCC2sleep - - IVCC2op - - IVCC2log - UV UV2 OV OV2 4.0 4.0 57 29.5 - 5.0 5.0 61 31 5.0 5.5 5.5 65 35 V V V V - - 12 9.0 mA - - 5.0 5.0 mA - 5.0 A 2.2 0.7 - - mA IVCCsleep - - - - 10 10 mA A
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Additional Operating VCC Supply Current for Each Logic Input Terminal Active VCC = 55 V and VCC2 = 28 V (Note 6) Quiescent VCC2 Supply Current VG_EN = 0 V and VCC = 12 V VG_EN = 0 V and VCC = 28 V Operating VCC2 Supply Current (Note 5) VCC = 55 V and VCC2 = 28 V VCC = 12 V and VCC2 = 12 V Additional Operating VCC2 Supply Current for Each Logic Input Terminal Active VCC = 55 V and VCC2 = 28 V (Note 6) Undervoltage Shutdown VCC Undervoltage Shutdown VCC2 (Note 7) Overvoltage Shutdown VCC Overvoltage Shutdown VCC2
OUTPUT
Output Sink Resistance (Turned Off) Idischarge LSS = 50 mA , VSRC_HS = 0 V (Note 8) Output Source Resistance (Turned On) Icharge HSS = 50 mA, VCP_OUT = 20 V (Note 8) Charge Current of the External High-Side MOSFET Through GATE_HSn Terminal (Note 8) Maximum Voltage (VGATE_HS - VSRC_HS) INH = Logic 1, ISmax = 5.0 mA Notes 5. Logic input terminal inactive (high impedance). 6. 7. 8. High-frequency PWM-ing ( 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain within the package power handling rating. The device may exhibit predictable behavior between 4.0 V and 5.5 V. See Figure 3, page 10, for a description of charge current. Icharge HSS Vmax - - 18 RDS - - 22 mA - 100 200 V RDS - - 22
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values for TA = 25C and min/max values for TA = -40C to 125C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
TIMING CHARACTERISTICS
Propagation Delay High Side and Low Side CLOAD = 5.0 nF, Between 50% Input to 50% Output (Note 9) (see Figure 2) Turn-On Rise Time CLOAD = 5.0 nF, 10% to 90% (Note 9), (Note 10) (see Figure 2) Turn-Off Fall Time CLOAD = 5.0 nF, 10% to 90% (Note 9), (Note 10) (see Figure 2) tf - 80 180 tr - 80 180 ns tpd - 200 300 ns ns
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Notes 9. CLOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side. 10. Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time).
50% IN_HS or IN_LS GATE_HS or GATE_LS
t pd t pd
50%
50%
tf tr
50% 10% 90% Figure 2. Timing Characteristics 90% 10%
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33883 is an H-bridge gate driver (or full-bridge predriver) with integrated charge pump and independent high- and lowside driver channels. It has the capability to drive large gatecharge MOSFETs and supports high PWM frequency. In sleep mode its supply current is very low.
FUNCTIONAL TERMINAL DESCRIPTION Supply Voltage Terminals (VCC and VCC2)
The VCC and VCC2 terminals are the power supply inputs to the device. VCC is used for the output high-side drivers and the charge pump. VCC2 is used for the linear regulation. They can be connected together or independent with different voltage values. The device can operate with VCC up to 55 V and VCC2 up to 28 V. The VCC and VCC2 terminals have undervoltage (UV) and overvoltage (OV) shutdown. If one of the supply voltage drops below the undervoltage threshold or rises above the overvoltage threshold, the gate outputs are switched LOW in order to switch off the external MOSFETs. When the supply returns to a level that is above the UV threshold or below the OV threshold, the device resumes normal operation according to the established condition of the input terminals.
Gate High- and Low-Side Terminals (GATE_HSn and GATE_LSn)
The GATE_HSn and GATE_LSn terminals are the gates of the external high- and low-side MOSFETs. The external highand low-side MOSFETs are controlled using the IN_HSn and IN_LSn inputs.
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G_EN Terminal
The G_EN terminal is used to place the device in a sleep mode. When the G_EN terminal voltage is a logic LOW state, the device is in sleep mode. The device is enabled and fully operational when the G_EN terminal voltage is logic HIGH, typically 5.0 V.
Charge Pump Out Terminal (CP_OUT)
The CP_OUT terminal is used to connect an external reservoir capacitor for the charge pump.
Input High- and Low-Side Terminals (IN_HSn and IN_LSn)
The IN_HSn and IN_LSn terminals are input control terminals used to control the gate outputs. These terminals are 5.0 V CMOS-compatible inputs with hysteresis. IN_HSn and IN_LSn independently control GATE_HSn and GATE_LSn, respectively. During wake-up, the logic is supplied from the G_EN terminal. There is no internal circuit to prevent the external highside and low-side MOSFETs from conducting at the same time.
Charge Pump Capacitor Terminals (C1 and C2)
The C1 and C2 terminals are used to connect an external capacitor for the charge pump.
Linear Regulator Output Terminal (LR_OUT)
The LR_OUT terminal is the output of the internal regulator. It is used to connect an external capacitor.
Source Output High-Side Terminals (SRC_HSn)
The SRC_HSn terminals are the sources of the external high-side MOSFETs. The external high-side MOSFETs are controlled using the IN_HSn inputs.
Ground Terminals (GNDn and GND_A)
These terminals are the ground terminals of the device. They should be connected together with a very low impedance connection.
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Table 1. Functional Truth Table
Conditions Sleep Normal Normal Undervoltage G_EN 0 1 1 1 IN_HSn x 1 0 x IN_LSn x 1 0 x Gate_HSn 0 1 0 0 Gate_LSn 0 1 0 0 Comments Device is in Sleep mode. The gates are at low state. Normal mode. The gates are controlled independently. Normal mode. The gates are controlled independently. The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. The device is currently in fault mode. The high-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode. The device is currently in fault mode. The low-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode.
Overvoltage
1
x
x
0
0
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Overtemperature on High-Side Gate Driver Overtemperature on Low-Side Gate Driver x = Don't care.
1
1
x
0
x
1
x
1
x
0
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DEVICE DESCRIPTION Driver Characteristics
Figure 3 represents the external circuit of the high-side gate driver. In the schematic, HSS represents the switch that is used to charge the external high-side MOSFET through the GATE_HS terminal. LSS represents the switch that is used to discharge the external high-side MOSFET through the GATE_HS terminal. The same schematic can be applied to the external low-side MOSFET driver simply by replacing terminal CP_OUT with terminal LR_OUT, terminal GATE_HS with terminal GATE_LS, and terminal SRC_HS with GND. The different voltages and current of the high-side gate driver are illustrated in Figure 4. The output driver sources a peak current of up to 1.0 A for 200 ns to turn on the gate. After 200 ns, 100 mA is continuously provided to maintain the gate charged. The output driver sinks a high current to turn off the gate. This current can be up to 1.0 A peak for a 100 nF load.
IN_HS1 0 HSSpulse_IN CP_OUT
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HSS HSS DC_IN IGATE_HS HSSDC_IN Icharge HSS Idischarge LSS GATE_HS1 LSS_IN
0
0
IN_HS1 HSSpulse_IN LSS_IN
LSS
180 k 18V SRC_HS1 Idischarge LSS Icharge HSS 1.0 A Peak 100 mA Typical 0 1.0 A Peak 0 IGATE_HS 1.0 A Peak 100 mA Typical 0 -1.0 A Peak
Figure 3. High-Side Gate Driver Functional Schematic
Note GATE_HS is loaded with a 100 nF capacitor in the chronograms. A smaller load will give lower peak and DC charge or discharge currents.
Figure 4. High-Side Gate Driver Chronograms
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APPLICATION REQUIREMENTS Turn-On
For turn-on, the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: I P = Qg /t r = 80 nC/80 ns 1.0 A Where Q g is power MOSFET gate charge and t r is peak current for rise time.
Turn-Off
The peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, tf, is substituted for tr: I P = Qg /t f = 80 nC/80 ns 1.0 A In addition to the dynamic current required to turn off or on the MOSFET, various application-related switching scenarios must be considered. These scenarios are presented in Figure 5. In order to withstand high dV/dt spikes, a low resistive path between gate and source is implemented during the OFFstate.
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Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Causes increased uncontrolled turn-on of low-side MOSFET. VBAT
Flyback spike pulls down high-side source VGS. Delays turn-off of highside MOSFET.
Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Delays turn-off of low-side MOSFET.
Flyback spike pulls down high-side source VGS. Causes increased uncontrolled turn-on of high-side MOSFET.
Crss
Crss
VBAT
Crss OFF
VBAT OFF VGATE -VDRN
Crss
VBAT
GATE_HS Ciss Irss VGATE GATE_LS OFF Ciss Crss
GATE_HS ILOAD L1 Ciss Crss
GATE_HS ILOAD L1 Ciss Crss
GATE_HS ILOAD L1 Ciss Crss
L1
ILOAD
GATE_LS OFF Ciss
GATE_LS Ciss
GATE_LS Ciss
Driver Requirement: Low Resistive GateSource Path During OFF-State
Driver Requirement: Low Resistive GateSource Path During OFF-State. High Peak Sink Current Capability
Driver Requirement: High Peak Sink Current Capability
Driver Requirement: Low Resistive GateSource Path During OFF-State
Figure 5. OFF-State Driver Requirement
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Low-Drop Linear Regulator
The low-drop linear regulator is supplied by VCC2. If VCC2 exceeds 15.0 V, the output is limited to 14.5 V (typical). The low-drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT, and the +14.5 V for the charge pump, which generates the CP_OUT The low-drop linear regulator provides 4.0 mA average current per driver stage. In case of the full bridge, that means approximately 16 mA -- 8.0 mA for the high side and 8.0 mA for the low side. Note: The average current required to switch a gate with a frequency of 100 kHz is:
External Capacitors Choice
External capacitors on the charge pump and on the linear regulator are necessary to supply high peak current absorbed during switching. Figure 7 represents a simplified circuitry of the high-side gate driver. Transistors Tosc1 and Tosc2 are the oscillator-switching MOSFETs. When Tosc1 is on, the oscillator is at low level. When Tosc2 is on, the oscillator is at high level. The capacitor CCP_OUT provides peak current to the high-side MOSFET through HSS during turn-on (3).
VLR_OUT VLR-OUT
Tosc2 Tosc2 Ccp CCP C1 C1 Tosc1 Tosc1 C2 C2 CP_out CP_OUT D1 D1
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ICP = Qg * f PWM = 80 nC * 100 kHz = 8.0 mA In a full-bridge application only one high side and one low side switches on or off at the same time.
CCP_OUT Ccp_out
D2 D2
Charge Pump
The charge pump generates the high-side driver supply voltage (CP_OUT), buffered at CCP_OUT. Figure 6 shows the charge pump basic circuit without load.
Vcc VCC
(2)
VLR_OUT VLR_OUT
D1 D1
VCP_OUT CP_OUT
T1 HSS
(3)
GATE_HS
GATE_HS
Ccp CCP
C1
LSS
Osc. OSC.
A C2
Ccp_out CCP_OUT
T2
Rg Rg
High-Side MOSFET
HS MOSFET
D2 D2
(1)
SRC_HS SRC_HS
Vbat VCC
Figure 6. Charge Pump Basic Circuit When the oscillator is in low state [(1) in Figure 6], CCP is charged through D2 until its voltage reaches VCC - VD2. When the oscillator is in high state (2), CCP is discharged though D1 in CCP_OUT, and final voltage of the charge pump, VCP_OUT, is Vcc + VLR_OUT - 2VD. The frequency of the 33883 oscillator is about 330 kHz.
Terminals pins
Low-Side MOSFET MOSFET
LS
Figure 7. High-Side Gate Driver
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CCP
CCP choice depends on power MOSFET characteristics and the working switching frequency. Figure 8 contains two diagrams that depict the influence of CCP value on VCP_OUT average voltage level. The diagrams represent two different frequencies for two power MOSFETs, MTP60N06HD and MPT36N06V.
21 20.5
CCP_OUT
Figure 9 depicts the simplified CCP_OUT current and voltage waveforms. fPWM is the working switching frequency.
Oscillator Oscillator in High in high Oscillator State Oscillator state in Low in low State state
High Side High Side Turn On turn on
VCP_OUT V Cp_out
rage V Cp_out Average VCP_OUT
VCP_OUT VCcp _ out
20 kHz 20KhZ 100 kHz 100 KhZ
ICP_OUT I
Cp_out
VVcp_out (v) CP_OUT (V)
20 19.5 19 18.5 18 5 25 45 65 85
f=330kHz f = 330 kHz
ffPWM PWM
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Peak Peak Current Current
CCP(nF) Ccp (nF) MTP60N06HD (Qg=50nC) MTP60N06HD (Qg = 50 nC)
Figure 9. Simplified CCP_OUT Current and Voltage Waveforms As shown above, at high-side MOSFET turn-on VCP_OUT voltage decreases. This decrease can be calculated according to the CCP_OUT value as follows:
MTP60N06HD (Qg = 50 nC)
21.5 21
Vcp_out (V)(V) VCP_OUT
20 kHz 100 kHz
VCP_OUT =
Qg CCP_OUT
20.5 20 19.5 19 18.5 5
Where Qg is power MOSFET gate charge.
CLR_OUT
CLR_OUT provides peak current needed by the low-side MOSFET turn-on. VLR_OUT decrease is as follows:
25 45 65 85
CCP (nF) Ccp (nF) MTP36N06V (Qg = 40 nC)
Figure 8. VCP_OUT Versus CCP The smaller the CCP value is, the smaller the VCP_OUT value is. Moreover, for the same CCP value, when the switching frequency increases, the average VCP_OUT level decreases. For most of the applications, a typical value of 33 nF is recommended.
VLR_OUT =
Qg CLR_OUT
Typical Values of Capacitors
In most working cases the following typical values are recommended for a well-performing charge pump: CCP = 33 nF, CCP_OUT = 470 nF, and CLR_OUT = 470 nF These values give a typical 100 mV voltage ripple on VCP_OUT and VLR_OUT with Qg = 50 nC.
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Protection
Gate Protection The low-side driver is supplied from the built-in low-drop regulator. The high-side driver is supplied from the internal charge pump buffered at CP_OUT. The low-side gate is protected by the internal linear regulator, which ensures that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump, the voltage at CP_OUT can be up to 65 V. The high-side gate is clamped internally in order to avoid a VGS exceeding 18 V. Gate protection does not include a flyback voltage clamp that protects the driver and the external MOSFET from a flyback voltage that can occur when driving inductive load. This flyback voltage can reach high negative voltage values and needs to be clamped externally, as shown in Figure 10.
LR_OUT CP_OUT OUT M1 GATE_HS VGS < 14 V SRC_HS Dcl M2 IN Output Driver OUT GATE_LS L1 Under All Conditions Inductive Flyback Voltage Clamp VCC
Load Dump and Reverse Battery VCC and VCC2 can sustain load a dump pulse of 40 V and double battery of 24 V. Protection against reverse polarity is ensured by the external power MOSFET with the free-wheeling diodes forming a conducting pass from ground to VCC. Additional protection is not provided within the circuit. To protect the circuit an external diode can be put on the battery line. It is not recommended putting the diode on the ground line. Temperature Protection There is temperature shutdown protection per each halfbridge. Temperature shutdown protects the circuitry against temperature damage by switching off the output drivers. Its typical value is 175C with an hysteresis of 15C. dV/dt at VCC VCC voltage must be higher than (SRC_HS voltage minus a diode drop voltage) to avoid perturbation of the high-side driver. In some applications a large dV/dt at terminal C2 owing to sudden changes at VCC can cause large peak currents flowing through terminal C1, as shown in Figure 11. For positive transitions at terminal C2, the absolute value of the minimum peak current, I C1min, is specified at 2.0 A for a t C1min duration of 600 ns. For negative transitions at terminal C2, the maximum peak current, IC1max, is specified at 2.0 A for a t C1max duration of 600 ns. Current sourced by terminal C1 during a large dV/dt will result in a negative voltage at terminal C1 (Figure 11). The minimum peak voltage VC1min is specified at -1.5 V for a duration of t C1max = 600 ns. A series resistor with the charge pump capacitor (Ccp) capacitor can be added in order to limit the surge current.
Freescale Semiconductor, Inc...
IN
Output Driver
Figure 10. Gate Protection and Flyback Voltage Clamp
VCC
IC1max
t C1min
I (C1+C2)
0A
t C1max
I C1min
V(LR_OUT)
V(C1)
0V
VC1min
Figure 11. Limits of C1 Current and Voltage with Large Values of dV/dt
33883 14 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com
Freescale Semiconductor, Inc.
In the case of rapidly changing VCC voltages, the large dV/dt may result in perturbations of the high-side driver, thereby forcing the driver into an OFF state. The addition of capacitors C3 and C4, as shown in Figure 12, reduces the dV/dt of the source line, consequently reducing driver perturbation. Typical values for R3/R4 and C3/C4 are 10 and 10 nF, respectively. dV/dt at VCC2 When the external high-side MOSFET is on, in case of rapid negative change of VCC2 the voltage (VGATE_HS - VSRC_HS) can be higher than the specified 18 V. In this case a resistance in the SRC line is necessary to limit the current to 5.0 mA max. It will protect the internal zener placed between GATE_HS and SRC terminals.
VBAT VBOOST
VCC VCC2 G_EN CCP
33 nF
33883 VCC VCC2 G_EN C1 C2 IN_HS1 CP_OUT LR_OUT GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2
CCP_OUT
470 nF
Freescale Semiconductor, Inc...
CLR_OUT
470 nF
R1 50 R3
M1
R2 50 R4 C4 10 nF 10
M3
C1 C2 IN_HS1 IN_LS1 IN_HS2 IN_LS2
MCU
C3 10 nF
10
DC Motor
IN_LS1 SRC_HS2 IN_HS2 GATE_LS2 IN_LS2 GND 50 M2 50 M4
Figure 12. Application Schematic with External Protection Circuit
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product, Go to: www.freescale.com
33883 15
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
DW SUFFIX 20-TERMINAL SOICW PLASTIC PACKAGE CASE 751D-06 ISSUE H
0.25
PIN'S NUMBER
M
B
10X
10.55 10.05
20
A
2.65 2.35
0.25 0.10
20X
1
0.49 0.35 0.25
6
M
TAB
Freescale Semiconductor, Inc...
PIN 1 INDEX
18X
1.27
NOTES: 1. 2. 3.
4
A A
12.95 12.65
4.
10
11
T
7.6 7.4
5
SEATING PLANE
B
20X
0.1 T
5.
0.75 0.25
X45
6.
0.32 0.23
DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62mm.
1.0 0.4
SECTION A-A
7 0
33883 16
MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com
Freescale Semiconductor, Inc.
NOTES
Freescale Semiconductor, Inc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product, Go to: www.freescale.com
33883 17
Freescale Semiconductor, Inc.
NOTES
Freescale Semiconductor, Inc...
33883 18
MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com
Freescale Semiconductor, Inc.
NOTES
Freescale Semiconductor, Inc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product, Go to: www.freescale.com
33883 19
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
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