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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC54/74HC597A
J SUFFIX CERAMIC PACKAGE CASE 620-10
1
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch
High-Performance Silicon-Gate CMOS
The MC54/74HC597A is identical in pinout to the LS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of an 8-bit input latch which feeds parallel data to an 8-bit shift register. Data can also be loaded serially (see Function Table). The HC597A is similar in function to the HC589A, which is a 3-state device. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 516 FETs or 129 Equivalent Gates
16
16 1
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
16 1
DT SUFFIX TSSOP PACKAGE CASE 948F-01
ORDERING INFORMATION
LOGIC DIAGRAM
SERIAL DATA INPUT 14
MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT
Ceramic Plastic SOIC TSSOP
SA
A B PARALLEL DATA INPUTS C D E F G H LATCH CLOCK
15 1 2 3 4 5 6 7 12 SERIAL 9 DATA QH OUTPUT INPUT LATCH SHIFT REGISTER
PIN ASSIGNMENT
B C D E F G H GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A SA SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK SHIFT CLOCK RESET QH
SHIFT CLOCK SERIAL SHIFT/ PARALLEL LOAD RESET
11 13 10 PIN 16 = VCC PIN 8 = GND
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
(c) Motorola, Inc. 1995
1
REV 0
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C -- Ceramic DIP: - 10 mW/_C from 100_ to 125_C -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC54/74HC597A
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
TA
VIH
VIL
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 0.5 to VCC + 0.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 2.4 mA v 4.0 mA v 5.2 mA
0 0 0 0
0
50
25
20
260 300
750 500 450
+ 125
1000 600 500 400
VCC
Max
6.0
VCC V
3.0 4.5 6.0
2.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
2.48 3.98 5.48
1.9 4.4 5.9
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 2.34 3.84 5.34 1.9 44 5.9
v
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
2.20 3.70 5.20 1.9 44 5.9
v
Unit
V V V
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NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL VOL tPHL fmax CPD ICC Cin Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Power Dissipation Capacitance (Per Package)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 8) Maximum Propagation Delay, Reset to QH (Figures 3 and 8) Maximum Propagation Delay, Shift Clock to QH (Figures 2 and 8) Maximum Propagation Delay, Latch Clock to QH (Figures 1 and 8) Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 8) Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VCC or GND Iout = 0 A Vin = VCC or GND
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Propagation Delay, Serial Shift/Parallel Load to QH (Figures 4 and 8)
Vin = VIH or VIL |Iout| |Iout| |Iout|
v
Test Conditions
3
v 2.4 mA v 4.0 mA v 5.2 mA
VCC V
VCC V
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
6.0
6.0
3.0 4.5 6.0
2.0 4.5 6.0
--
- 55 to 25_C
- 55 to 25_C
Typical @ 25C, VCC = 5.0 V
0.1
0.26 0.26 0.26
160 90 30 25
160 90 30 25
160 90 30 25
175 100 40 30
0.1 0.1 0.1
10
75 27 15 13
10 15 30 50
4
Guaranteed Limit
Guaranteed Limit
v 85_C v 125_C
v 85_C v 125_C
1.0
0.33 0.33 0.33
200 130 40 30
200 130 40 30
200 130 40 30
225 110 50 40
0.1 0.1 0.1
9 14 28 45
10
95 32 19 16
40
40
MC54/74HC597A
1.0
0.40 0.40 0.40
240 160 48 40
240 160 48 40
240 160 48 40
275 125 60 50
160
110 36 22 19
0.1 0.1 0.1
8 12 25 40
10
MOTOROLA MHz Unit Unit A A pF pF ns ns ns ns ns V
MC54/74HC597A
PIN DESCRIPTIONS
DATA INPUTS A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7) Parallel data inputs. Data on these inputs is stored in the input latch on the rising edge of the Latch Clock input. SA (Pin 14) Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input it Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low. CONTROL INPUTS Serial Shift/Parallel Load (Pin 13) Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited. Reset (Pin 10) Asynchronous, Active-low shift register reset. A low level applied to this input resets the shift register to a low level, but does not change the data in the input latch. Shift Clock (Pin 11) Serial shift register clock. A low-to-high transition on this input shifts data on the Serial Data Input into the shift register and data in stage H is shifted out QH, being replaced by the data previously stored in stage G. Latch Clock (Pin 12) Latch clock. A low-to-high transition on this input loads the parallel data on inputs A-H into the input latch. OUTPUT QH (Pin 9) Serial data output. This pin is the output from the last stage of the shift register.
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
trec
tr, tf
tsu
tsu
tsu
tw
tw
tw
th
th
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Serial Shift/Parallel Load (Figure 4)
Minimum Pulse Width, Reset (Figure 3)
Minimum Pulse Width, Latch Clock and Shift Clock (Figures 1 and 2)
Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 3)
Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 6)
Minimum Hold Time, Latch Clock to Parallel Data Inputs A-H (Figure 5)
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 7)
Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 6)
Minimum Setup Time, Parallel Data inputs A-H to Latch Clock (Figure 5)
Parameter
5 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 60 35 12 10 60 35 12 10 60 35 12 10 70 40 15 13 15 10 2 2 70 40 15 13 70 40 15 13 70 40 15 13 2 2 2 2 Guaranteed Limit 1000 800 500 400 70 40 15 13 70 40 15 13 70 40 15 13 80 45 19 16 20 15 3 3 80 45 19 16 80 45 19 16 80 45 19 16 2 2 2 2 1000 800 500 400 80 45 19 16 80 45 19 16 80 45 19 16 90 50 24 20 30 25 5 4 90 50 24 20 90 50 24 20 90 50 24 20 2 2 2 2
v 85_C v 125_C
MC54/74HC597A
MOTOROLA Unit ns ns ns ns ns ns ns ns ns ns
MC54/74HC597A
FUNCTION TABLE
Inputs Serial Shift/ Parallel Load X X H L H L, H, L, H, Latch Clock L, H, Shift Clock X X L,H, X L,H, Serial Input SA X X X X X Parallel Inputs A-H X a-h a-h X X Latch Contents U a-h a-h U U Resulting Function Shift Register Contents L L U LRN SRN U Output QH L L U LRH U
Operation Reset shift register Reset shift register; load parallel data into data latch Load parallel data into data latch Transfer latch contents to shift register Contents of data latch and shift register are unchanged Load parallel data into data latch and shift register Shift serial data into shift register Load parallel data into data latch and shift serial data into shift register
Reset L L H H H
H H H
L H H X
X
X D D
a-h X a-h
a-h * a-h
a-h SRA = D; SRN SRN + 1 SRA = D; SRN SRN + 1
h SRG SRH SRG SRH
LR = latch register contents SR = shift register contents * = depends on latch clock input
a-h = data at parallel data inputs A-H D = data (L, H) at serial data input SA
U = remains unchanged X = don't care
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC597A
SWITCHING WAVEFORMS
tw tr LATCH CLOCK 90% 50% 10% tf VCC SHIFT CLOCK GND 50% GND 1/fmax tw VCC
tPLH QH 90% 50% 10% tTLH
tPHL QH tTHL
tPLH 50%
tPHL
Figure 1. (Serial Shift/Parallel Load = L)
Figure 2. (Serial Shift/Parallel Load = H)
tw RESET tPHL 50% trec SHIFT CLOCK 50%
VCC GND tw SERIAL SHIFT/ PARALLEL LOAD 50% tPLH QH 50% 50% GND tPHL
VCC
QH
Figure 3.
Figure 4.
VALID PARALLEL DATA A/H VCC 50% GND tsu LATCH CLOCK th VCC 50% GND SHIFT CLOCK SERIAL DATA INPUT SA 50%
VALID VCC GND tsu th VCC 50% GND
Figure 5.
Figure 6.
TEST POINT SERIAL SHIFT/ PARALLEL LOAD VCC 50% GND tsu SHIFT CLOCK VCC 50% GND * Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT CL*
Figure 7.
Figure 8. Test Circuit
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC54/74HC597A
EXPANDED LOGIC DIAGRAM
SERIAL DATA 14 INPUT, SA SHIFT CLOCK RESET 11 10
SERIAL SHIFT/ 13 PARALLEL LOAD LATCH CLOCK A 12 15 STAGE A D C Q D S CQ R
STAGE B B 1 D C Q D S CQ R
PARALLEL DATA INPUTS
C
2
STAGE C*
D
3
STAGE D*
E
4
STAGE E*
F
5
STAGE F*
G
6
STAGE G* STAGE H
H
7
D C
Q D S CQ R 9 QH
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC597A
TIMING DIAGRAM
SHIFT CLOCK
SERIAL DATA INPUT, SA RESET
SERIAL SHIFT PARALLEL LOAD LATCH CLOCK A
H
L
L
B
L
L
L
C
H
L
L
PARALLEL DATA INPUTS
D
L
L
L
E
H
L
H
F
H
L
H
G H
L H
L H
L H
QH RESET SHIFT REGISTER
L SERIAL SHIFT
LH
L
H
H
L
H
L
H
L
H
L
L SERIAL SHIFT
L
H
L
H
H
SERIAL SHIFT
SERIAL SHIFT
LOAD LATCH PARALLEL LOAD SHIFT REGISTER
LOAD LATCH
PARALLEL LOAD SHIFT REGISTER
PARALLEL LOAD LATCH AND SHIFT REGISTER
High-Speed CMOS Logic Data DL129 -- Rev 6
9
MOTOROLA
MC54/74HC597A
OUTLINE DIMENSIONS
-A -
16 9
J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V
-B - C L
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-T
SEATING - PLANE
N E F G D 16 PL 0.25 (0.010)
M
K M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
-A -
16 9
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
MOTOROLA
10
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC597A
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
K1
2X
L/2
16
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
11
*MC54/74HC597A/D*
EE CC EE CC EE CC EE CC
-W-
MC54/74HC597A/D MOTOROLA

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