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P89C669
80C51 8-bit microcontroller family with extended memory; 96 kB Flash with 2 kB RAM
Rev. 02 -- 13 November 2003 Product data
1. General description
The P89C669 represents the first Flash microcontroller based on Philips Semiconductors' new 51MX core. The P89C669 features 96 kbytes of Flash program memory and 2 kbytes of data SRAM. In addition, this device is equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs and byte based I2C-bus serial interface. Philips Semiconductors' 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of program memory and 8 Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits (ASICs). The P89C669 provides greater functionality, increased performance and overall lower system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P89C669 eliminates the need for software work-arounds. The increased program memory enables design engineers to develop more complex programs in a high-level language like C, for example, without struggling to contain the program within the traditional 64 kbytes of program memory. These enhancements also greatly improve C Language efficiency for code size below 64 kbytes. The P89C669 device contains a non-volatile Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. The 51MX core is described in more detail in the 51MX Architecture Reference.
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
2. Features
2.1 Key features
s Extended features of the 51MX Core: x 23-bit program memory space and 23-bit data memory space x Linear program and data address range expanded to support up to 8 Mbytes each x Program counter expanded to 23 bits x Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation x New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces s 100% binary compatibility with the classic 80C51 so that existing code is completely reusable s Up to 24 MHz CPU clock with 6 clock cycles per machine cycle s 96 kbytes of on-chip program Flash s 2 kbytes of on-chip data RAM s Programmable Counter Array (PCA) s Two full-duplex enhanced UARTs s Byte based Fast I2C serial interface (400 kbits/s)
2.2 Key benefits
s s s s s s Increases program/data address range to 8 Mbytes each Enhances performance and efficiency for C programs Fully 80C51-compatible microcontroller Provides seamless and compelling upgrade path from classic 80C51 Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs Supported by wide range of 80C51 development systems and programming tools vendors s The P89C669 makes it possible to develop applications at lower cost and with a reduced time-to-market
2.3 Complete features
s Fully static s Up to 24 MHz CPU clock with 6 clock cycles per machine cycle s 96 kbytes of on-chip Flash with In-System Programming (ISP) and In-Application Programming (IAP) capability s 2 kbytes of on-chip RAM s 23-bit program memory space and 23-bit data memory space s Four-level interrupt priority s 32 I/O lines (4 ports) s Three Timers: Timer0, Timer1 and Timer2 s Two full-duplex enhanced UARTs with baud rate generator
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Product data
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P89C669
80C51 8-bit microcontroller family with extended memory
Byte based Fast I2C-bus serial interface (400 kbits/s) Framing error detection Automatic address recognition Power control modes Clock can be stopped and resumed Idle mode Power-down mode Second DPTR register Asynchronous port reset Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules s Low EMI (inhibit ALE) s Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler) s s s s s s s s s s
3. Ordering information
Table 1: Ordering information Package Name P89C669FA P89C669BBD PLCC44 LQFP44 Description plastic leaded chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm Version SOT187-2 SOT389-1 Type number
3.1 Ordering options
Table 2: Ordering options Memory OTP P89C669FA P89C669BBD 96 kB 96 kB RAM 2048 B 2048 B -40 C to +85 C 0 C to +70 C Temperature range VDD voltage range 4.5 to 5.5 V 4.5 to 5.5 V Frequency 0 to 24 MHz 0 to 24 MHz Type number
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Product data
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P89C669
80C51 8-bit microcontroller family with extended memory
4. Block diagram
HIGH PERFORMANCE 80C51 CPU
96 kB CODE FLASH
UART 0
internal bus
2 kB DATA RAM BAUD RATE GENERATOR
PORT 3
UART 1
PORT 2
TIMER 0 TIMER 1
PORT 1
WATCHDOG TIMER
PORT 0
PCA (PROGRAMMABLE COUNTER ARRAY)
CRYSTAL OR RESONATOR
OSCILLATOR
TIMER2
I2C
002aaa405
Fig 1. Block diagram.
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P89C669
80C51 8-bit microcontroller family with extended memory
5. Functional diagram
VDD VSS
Data Bus
RXD0 TXD0 INT0 INT1 CEX3/T0 CEX4/T1 WR RD
PORT1
Address bus 0-7
T2 T2EX ECI CEX0 CEX1 CEX2 SCL SDA
PORT0
Address Bus 8-15
PORT 3
PORT2
Address Bus 16-22
P89C669
RXD1 TXD1
RST EA/VPP PSEN ALE/PROG
XTAL2 XTAL1
002aaa403
Fig 2. Functional diagram.
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Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
6. Pinning information
6.1 Pinning
6.1.1 Plastic leaded chip carrier
6 P1.4/CEX1
5 P1.3/CEX0
3 P1.1/T2EX
1 (NC/VSS)
43 P0.0/AD0
42 P0.1/AD1
41 P0.2/AD2
P1.5/CEX2 P1.6/SCL P1.7/SDA
7 8 9
40 P0.3/AD3
4 P1.2/ECI
2 P1.0/T2
44 VDD
39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA/VPP
RST 10 P3.0/RXD0 11 RXD1 12 P3.1/TXD0 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/CEX3/T0 16 P3.5/CEX4/T1 17
P89C669FA
34 TXD1 33 ALE 32 PSEN 31 P2.7/A15 30 P2.6/A14/A22 29 P2.5/A13/A21
P3.6/WR 18
P3.7/RD 19
XTAL2 20
XTAL1 21
VSS 22
(NC/VDD) 23
P2.0/A8/A16 24
P2.1/A9/A17 25
P2.2/A10/A18 26
P2.3/A11/A19 27
P2.4/A12/A20 28
002aaa404
Fig 3. PLCC44 pin configuration.
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Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
6.1.2
Plastic low profile quad flat package
44 P1.4/CEX1
43 P1.3/CEX0
41 P1.1/T2EX
39 (NC/VSS)
37 P0.0/AD0
36 P0.1/AD1
35 P0.2/AD2
P1.5/CEX2 P1.6/SCL P1.7/SDA RST P3.0/RXD0 RXD1 P3.1/TXD0 P3.2/INT0 P3.3/INT1
1 2 3 4 5 6 7 8 9
34 P0.3/AD3
42 P1.2/ECI
40 P1.0/T2
38 VDD
33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA/VPP
P89C669BBD
28 TXD1 27 ALE 26 PSEN 25 P2.7/A15 24 P2.6/A14/A22 23 P2.5/A13/A21
P3.4/CEX3/T0 10 P3.5/CEX4/T1 11
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
VSS 16
(NC/VDD) 17
P2.0/A8/A16 18
P2.1/A9/A17 19
P2.2/A10/A18 20
P2.3/A11/A19 21
P2.4/A12/A20 22
002aaa406
Fig 4. LQFP44 pin configuration.
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P89C669
80C51 8-bit microcontroller family with extended memory
6.2 Pin description
Table 3: Symbol Pin description Pin PLCC P0.0 - P0.7 43 - 36 LQFP 30 - 37 I/O Port 0: Port 0 is an open drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled LOW will source current because of the internal pull-ups. Type Description
P1.0 - P1.7 2 - 9
1 - 3, 40 - 44
I/O
2 3 4 5 6 7 8
40 41 42 43 44 1 2
I/O I I I/O I/O I/O I/O
* * * * * * * *
P1.0, T2 - Timer/Counter 2 external count input/Clock out P1.1, T2EX - Timer/Counter 2 Reload/Capture/Direction Control P1.2, ECI - External Clock Input to the PCA P1.3, CEX0 - Capture/Compare External I/O for PCA module 0 P1.4, CEX1 - Capture/Compare External I/O for PCA module 1 (with pull-up on pin) P1.5, CEX2 - Capture/Compare External I/O for PCA module 2 (with pull-up on pin) P1.6, SCL - I2C serial clock (when I2C is used, this pin is open-drain and requires external pull-up due to I2C-bus specification)
9
3
I/O
P1.7, SDA - I2C serial data (when I2C is used, this pin is open-drain and requires external pull-up due to I2C-bus specification)
P2.0 - P2.7 24 - 31
18 - 25
I/O
Port 2: Port 2 is a 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled LOW will source current because of the internal pull-ups. (See Section 9 "Static characteristics", IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR) or 23-bit addresses (MOVX @EPTR, EMOV). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @ Ri), port 2 emits the contents of the P2 Special Function Register. Note that when 23-bit address is used, address bits A16-A22 will be outputted to P2.0-P2.6 when ALE is HIGH, and address bits A8-A14 are outputted to P2.0-P2.6 when ALE is LOW. Address bit A15 is outputted on P2.7 regardless of ALE.
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P89C669
80C51 8-bit microcontroller family with extended memory
Table 3: Symbol
Pin description...continued Pin PLCC LQFP 5, 7 - 13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source current because of the internal pull-ups. Type Description
P3.0 - P3.7 11, 13 - 19
11 13 14 15 16 17 18 19 RXD1 TXD1 RST 12 34 10
5 7 8 9 10 11 12 13 6 28 4
I O I I I I O O I O I
* * * * * * * * * *
P3.0, RXD0 - Serial input port 0 P3.1, TXD0 - Serial output port 0 P3.2, INT0 - External interrupt 0 P3.3, INT1 - External interrupt 1 P3.4, T0/CEX3 - Timer0 external input/capture/compare external I/O for PCA module 3 P3.5, T1/CEX4 - Timer1 external input/capture/compare external I/O for PCA module 3 P3.6, WR - External data memory write strobe P3.7, RD - External data memory read strobe RXD1 - Serial input port 1 (with pull-up on pin) TXD1 - Serial output port 1 (with pull-up on pin)
Reset: A HIGH on this pin for two machine cycles, while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. Address Latch Enable: Output pulse for latching the LOW byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 16 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR AUXR.0. With this bit is set, ALE will be active only during a MOVX instruction. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held LOW to enable the device to fetch code from external program memory locations. If EA is held HIGH, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
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ALE
33
27
O
PSEN
32
26
O
EA/VPP
35
29
I
XTAL1
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21
15
I
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Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
Table 3: Symbol XTAL2 VSS VDD (NC/VSS)
Pin description...continued Pin PLCC 20 22 44 1 LQFP 14 16 38 39 O I I I Crystal 2: Output from the inverting oscillator amplifier. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. No Connect/Ground: This pin is internally connected to VSS on the P89C669. If connected externally, this pin must only be connected to the same VSS as at pin 22. (Note: Connecting the second pair of VSS and VDD pins is not required. However, they may be connected in addition to the primary VSS and VDD pins to improve power distribution, reduce noise in output signals, and improve system-level EMI characteristics.) No Connect/Power Supply: This pin is internally connected to VDD on the P89C669. If connected externally, this pin must only be connected to the same VDD as at pin 44. (Note: Connecting the second pair of VSS and VDD pins is not required. However, they may be connected in addition to the primary VSS and VDD pins to improve power distribution, reduce noise in output signals, and improve system-level EMI characteristics.) Type Description
(NC/VDD)
23
17
I
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P89C669
80C51 8-bit microcontroller family with extended memory
7. Functional description
7.1 Flash memory description
The P89C669 contains 96 kbytes of Flash program memory. It is organized as 12 separate blocks, each block containing 8 kbytes. The P89C669 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash byte block. In-system programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface. The P89C669 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C669 uses a +5 V VPP supply to perform the Program/Erase algorithms.
* Flash internal program memory with Block Erase. * Internal 4 kbytes Boot Flash, containing low-level in-system programming routines
and a default UART loader. User program can call these routines to perform In-Application Programming (IAP). The BootFlash can be turned off to provide access to the full 8 Mbytes memory space.
* Boot vector allows user provided Flash loader code to reside anywhere in the
Flash memory space. This configuration provides flexibility to the user.
* Default loader in BootFlash allows programming via the UART interface without the
need for a user provided loader.
* Up to 8 Mbytes of external program memory if the internal program memory is
disabled (EA = 0).
* +5 V programming and erase voltage. * Read/Programming/Erase using ISP/IAP:
- Byte Programming (20 s). - Typical quick erase times (including preprogramming time): - Block Erase (8 kbytes) in 1 second. - Full Erase (96 kbytes) in 1 second.
* * * *
Parallel programming with 87C51-like hardware interface to programmer. Programmable security for the code in the Flash. 10,000 minimum erase/program cycles for each byte. 10 year minimum data retention.
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P89C669
80C51 8-bit microcontroller family with extended memory
7.2 Memory arrangement
P89C669 has 96 kbytes of Flash (MX universal map range: 80:0000-81:7FFF) and 2 kbytes of on-chip RAM:
Table 4: Memory arrangement Size (Bytes) and MX universal memory map range P89C669 128 (7F:0000-7F:007F)
Data memory
Type DATA IDATA
Description memory that can be addressed both directly and indirectly; can be used as stack
superset of DATA; memory that can be addressed 256 indirectly (where direct address for upper half is for SFR (7F:0000-7F:00FF) only); can be used as stack superset of DATA/IDATA; memory that can be addressed 1280 indirectly using Universal Pointers (PR0,1); can be used (7F:0000-7F:04FF) as stack memory (on-chip `External Data') that is accessed via the MOVX/EMOV instructions using DPTR/EPTR 768 (00:0000-00:02FF)
EDATA
XDATA
For more detailed information, please refer to the P89C669 User Manual.
7.3 Special function registers
Special Function Register (SFR) accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
* SFR bits labeled `-', `0', or `1' can only be written and read as follows:
- `-' must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
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Table 5: Name
Special function registers Description SFR addr. Bit functions and addresses MSB E6 F6 E5 F5 E4 F4 E3 GF2 F3 E2 0 F2 E1 LSB E0 00H EXTRAM AO F1 S0BRGS DPS F0 00H BRGEN 00H[6] 00H 00H[6] XXH XXH XXH 00H[6] 00H[6] ENBOOT Reset value
Bit address E7 ACC [1] AUXR [2] AUXR1 [2] B [1] BRGCON [2] Accumulator Auxiliary Function Register Auxiliary Function Register 1 B Register Baud Rate Generator Control E0H 8EH A2H F0H 85H[3]
Bit address F7
BRGR0 [2][5] Baud Rate Generator Rate LOW 86H[3] BRGR1 [2][5] Baud Rate Generator Rate HIGH 87H[3] CCAP0H [2] CCAP1H [2] CCAP2H [2] CCAP3H [2] CCAP4H [2] CCAP0L [2] CCAP1L [2] CCAP2L [2] CCAP3L [2] CCAP4L [2] CCAPM0 [2] CCAPM1 [2] CCAPM2 [2] CCAPM3 [2] CCAPM4 [2] CCON [1] [2] CH [2] CL [2] CMOD [2] DPTR Module 0 Capture HIGH Module 1 Capture HIGH Module 2 Capture HIGH Module 3 Capture HIGH Module 4 Capture HIGH Module 0 Capture LOW Module 1 Capture LOW Module 2 Capture LOW Module 3 Capture LOW Module 4 Capture LOW Module 0 Mode Module 1 Mode Module 2 Mode Module 3 Mode Module 4 Mode PCA Counter Control PCA Counter HIGH PCA Counter LOW PCA Counter Mode Data Pointer (2 bytes) FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH DAH DBH DCH DDH DEH D8H F9H E9H D9H CIDL WDTE CPS1 CPS0 ECF CF ECOM_0 ECOM_1 ECOM_2 ECOM_3 ECOM_4 DE CR CAPP_0 CAPP_1 CAPP_2 CAPP_3 CAPP_4 DD CAPN_0 CAPN_1 CAPN_2 CAPN_3 CAPN_4 DC CCF4 MAT_0 MAT_1 MAT_2 MAT_3 MAT_4 DB CCF3 TOG_0 TOG_1 TOG_2 TOG_3 TOG_4 DA CCF2 PWM_0 PWM_1 PWM_2 PWM_3 PWM_4 D9 CCF1 ECCF_0 ECCF_1 ECCF_2 ECCF_3 ECCF_4 D8 CCF0
80C51 8-bit microcontroller family with extended memory
XXH XXH XXH XXH XXH XXH XXH 00H[6] 00H[6] 00H[6] 00H[6] 00H[6] 00H[6] 00H 00H 00H[6] 00H
Bit address DF
P89C669
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Table 5: Name DPH DPL EPL [2] EPM [2] EPH [2] I2ADR I2CON I2DAT I2CLH I2CLL I2STA IEN0 [1]
Rev. 02 -- 13 November 2003
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Special function registers...continued Description Data Pointer HIGH Data Pointer LOW Extended Data Pointer LOW Extended Data Pointer Middle Extended Data Pointer HIGH I2C I2C I2C Slave Address Register Data Register I2C Control Register Clock Generator HIGH Register SFR addr. 83H 82H FCH[3] FDH[3] FEH[3] 94H 91H 93H 96H 95H 92H A8H code.4 EA code.3 AE EC EE BE PPC PPCH FE code.2 AD ET2 ED BD PT2 PT2H FD code.1 AC ES0/ ES0R Bit address EF EC EI2C BC PS0/ PS0R PS0H/ PS0RH Bit address FF FC PI2C PI2CH FB FA PS1T PS1TH EAM F9 PS0T PS0TH ESMM F8 PS1/ PS1R PS1H/ PS1RH EIFM 00H[6] 00H[6] 00H[6] EB BB PT1 PT1H EA ES1T BA PX1 PX1H E9 ES0T B9 PT0 PT0H E8 ES1/ ES1R Bit address BF B8 PX0 PX0H 00H 00H 00H[6] code.0 AB ET1 0 AA EX1 0 A9 ET0 0 A8 EX0 00H 00H 00H F8H addr.6 addr.5 I2EN addr.4 STA addr.3 STO addr.2 SI addr.1 AA addr.0 GC CRSEL Bit functions and addresses MSB LSB Reset value 00H 00H 00H 00H 00H 00H 00H
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I2C Clock Generator LOW Register I2C Status Register Interrupt Enable 0
80C51 8-bit microcontroller family with extended memory
Bit address AF
IEN1 [1]
Interrupt Enable 1
E8H
-
IP0 [1] IP0H
Interrupt Priority Interrupt Priority 0 HIGH
B8H B7H
-
IP1 [1] IP1H MXCON [2]
Interrupt Priority 1 Interrupt Priority 1 HIGH MX Control Register
F8H F7H FFH[3]
-
P89C669
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Table 5: Name Special function registers...continued Description SFR addr. Bit functions and addresses MSB 86 AD6 96 CEX3 A6 AD14/ AD22 Bit address B7 P3 [1] PCON [2]
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LSB 85 AD5 95 CEX2/ SPICLK A5 ADA13/ AD21 B5 T1 D5 F0 84 AD4 94 CEX1/ MOSI A4 AD12/ AD20 B4 T0 POF D4 RS1 A3 AD11/ AD19 B3 INT1 GF1 D3 RS0 A2 AD10/ AD18 B2 INT0 GF0 D2 OV A1 AD9/ AD17 B1 TxD0 PD D1 F1 A0 AD8/ AD16 B0 RxD0 IDL D0 P 83 AD3 93 CEX0 82 AD2 92 ECI 81 AD1 91 T2EX 80 AD0 90 T2
Reset value
Bit address 87 P0 [1] P1 [1] Port 0 Port 1 80H 90H AD7 CEX4 Bit address 97
FFH FFH
Bit address A7 P2 [1] Port 2 A0H AD15
FFH
B6 WR SMOD0 D6 AC
Port 3 Power Control Register
B0H 87H
RD SMOD1
FFH 00H/ 10H[4]
Bit address D7 PSW [1] RCAP2H [2] RCAP2L [2] S0CON [1] S0BUF S0ADDR S0ADEN S0STAT [2] Program Status Word Timer2 Capture HIGH Timer2 Capture LOW Serial Port 0 Control Serial Port 0 Data Buffer Register Serial Port 0 Address Register Serial Port 0 Address Enable Serial Port 0 Status D0H CBH CAH Bit address 9F 98H 99H A9H B9H 8CH[3] SM0_0/ FE_0 CY
80C51 8-bit microcontroller family with extended memory
00H 00H 00H
9E SM1_0
9D SM2_0
9C REN_0
9B TB8_0
9A RB8_0
99 TI_0
98 RI_0 00H xxH 00H 00H
DBMOD_0 INTLO_0 86[3] SM1_1
CIDIS_0 85[3] SM2_1
DBISEL_ FE_0 0 84[3] REN_1 83[3] TB8_1
BR_0 82[3] RB8_1
OE_0 81[3] TI_1
STINT_0 80[3] RI_1
00H[6]
Bit address 87[3] S1CON [1] [2] S1BUF [2] S1ADDR [2] Serial Port 1 Control 80H[3] SM0_1/ FE_1 Serial Port 1 Data buffer Register 81H[3] Serial Port 1 Address Register 82H[3]
P89C669
00H XXH 00H
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 5: Name S1ADEN [2] S1STAT [2] SP SPE [2] TCON [1] T2CON [1] [2] T2MOD [2] TH0 TH1 TH2 TL0 TL1 TL2 TMOD WDTRST [2] WDCON [2]
[1] [2] [3] [4] [5] [6] Rev. 02 -- 13 November 2003
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Special function registers...continued Description Serial Port 1 Address Enable Serial Port 1 Status Stack Pointer (Stack Pointer LOW Byte) Stack Pointer HIGH Timer Control Register Timer2 Control Register Timer2 Mode Control Timer 0 HIGH Timer 1 HIGH Timer 2 HIGH Timer 0 LOW Timer 1 LOW Timer 2 LOW Timer 0 and 1 Mode Watchdog Timer Reset Watchdog Timer Control SFR addr. 83H[3] 84H[3] 81H FBH[3] Bit address 8F 88H C8H C9H 8CH 8DH CDH 8AH 8BH CCH 89H A6H 8FH[3] GATE C/T M1 M0 GATE C/T M1 M0 TF1 CF TF2 8E TR1 CE EXF2 8D TF0 CD RCLK 8C TR0 CC TCLK 8B IE1 CB EXEN2 8A IT1 CA TR2 89 IE0 C9 C/T2 T2OE 88 IT0 C8 CP/RL2 DCEN 00H 00H[6] 00H 00H 00H 00H 00H 00H 00H FFH WDPRE2 WDPRE1 WDPRE0 00H[6] 00H DBMOD_1 INTLO_1 CIDIS_1 DBISEL1 FE_1 BR_1 OE_1 STINT_1 Bit functions and addresses MSB LSB Reset value 00H 00H[6] 07H 00H
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SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Extended SFRs accessed by preceding the instruction with MX escape (opcode A5h). Power-on reset is 10H. Other reset is 00H. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any of them is written if BRGEN = 1, result is unpredictable. The unimplemented bits (labeled `-') in the SFRs are X's (unknown) at all times. `1's should NOT be written to these bits, as they may be used for other purposes in future derivatives. The reset values shown for these bits are `0's although they are unknown when read.
P89C669
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
7.4 Security bits
The P89C669 has security bits to protect users' firmware codes. With none of the security bits programmed, the code in the program memory can be verified. When only security bit 1 (see Table 6) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. EA is latched on Reset and all further programming of EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.
Table 6: EPROM security bits Bit 1 1 2 U P Bit 2 U U Bit 3 U U Protection description No program security features enabled. Flash is programmable and verifiable. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. Same as 2, also verification is disabled. Same as 3, external execution is disabled.
Security Bits[1][2]
3 4
[1] [2]
P P
P P
U P
P - programmed. U - unprogrammed. Any other combination of security bits is not defined.
8. Limiting values
Table 7: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Tamb Tstg VI II, IO P Parameter operating temperature storage temperature range input voltage on EA/VPP pin to VSS input voltage on any other pin to VSS maximum IOL per I/O pin power dissipation based on package heat transfer, not device power consumption Conditions under bias Min 0 -40 -65 0 -0.5 Max +70 +85 +150 +13 VDD + 0.5 20 1.5 Unit C C C V V mA W
[1]
The following applies to the Limiting values: a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Section 9 "Static characteristics" and Section 10 "Dynamic characteristics" of this specification is not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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9. Static characteristics
Table 8: DC electrical characteristics Tamb = 0 C to +70 C for commercial, unless otherwise specified; VDD = 4.5 V to 5.5 V unless otherwise specified. Symbol Parameter VIL VIH VIH1 VOL VOL1 VOH VOH1 LOW-level input voltage HIGH-level input voltage (ports 0, 1, 2, 3, 4, EA) HIGH-level input voltage, XTAL1, RST LOW-level output voltage, ports 1, 2, 3, 4[8] LOW-level output voltage, port 0, ALE, PSEN[7][8] HIGH-level output voltage, ports 1, 2, 3, 4 HIGH-level output voltage (port 0 in external bus mode), ALE[9], PSEN[3] Logical 0 input current, ports 1, 2, 3, 4 Logical 1-to-0 transition current, ports 1, 2, 3, 4[8] Power supply current Active mode[5] Idle mode[5] Power-down mode or clock stopped (see Figure 13 for conditions) RRST C10 Internal reset pull-down resistor Pin capacitance[10] (except EA) VDD = 5.5 V VDD = 4.5 V; IOL = 1.6 mA VDD = 4.5 V; IOL = 3.2 mA VDD = 4.5 V; IOH = -30 A VDD = 4.5 V; IOH = -3.2 mA VIN = 0.4 V 4.5 V < VDD < 5.5 V; VIN = 2.0 V
[4]
Conditions
Min -0.5
Typ[1] Max 0.2VDD - 0.1 VDD + 0.5 VDD + 0.5 0.4 0.4 -
Unit V V V V V V V
0.2VDD + 0.9 0.7VDD VDD - 0.7 VDD - 0.7 -
IIL ITL IL1 ICC
-1 [5]
20
-75 -650 10 7 + 2.7 x fosc[MHz] 4 + 1.3 x fosc[MHz] 100
A A A mA mA A
Input leakage current, port 0 0.45 < VIN < VDD - 0.3
-
40 -
-
225 15
k pF
[1] [2]
[3] [4] [5] [6] [7] [8]
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), 5 V, unless otherwise stated. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and ports 1, 3 and 4. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading >100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD - 0.7 V specification when the address bits are stabilizing. Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from `1' to `0'. The transition current reaches its maximum value when VIN is approximately 2 V for 4.5 V < VDD < 5.5 V. See Figure 10 through Figure 13 for ICC test conditions. fosc is the oscillator frequency in MHz. This value applies to Tamb = 0 C to +70 C. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. Under steady state (non-transient) conditions, IOL must be externally limited as follows: a) Maximum IOL per port pin: 15 mA b) Maximum IOL per 8-bit port: 26 mA
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c) Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. [9] ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. [10] Pin capacitance is characterized but not tested.
10. Dynamic characteristics
Table 9: AC electrical characteristics Tamb = 0 C to +70 C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Figure Parameter 4.5 V < VDD < 5.5 V Variable Min fOSC tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tAVIV1 tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tAVDV1 tLLWL tAVWL tAVWL1 5 5 5 5, 6, 7 5, 6, 7 5 5 5 5 5 5 5 5 5 6 7 6 6 6 6 6 6 6, 7 6, 7 6, 7 Oscillator frequency Clock cycle ALE pulse width Address valid to ALE LOW Address hold after ALE LOW ALE LOW to valid instruction in ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in (non-Extended Addressing Mode) Address (A16-A22) to valid instruction in (Extended Addressing Mode) PSEN LOW to address float RD pulse width WR pulse width RD LOW to valid data in Data hold after RD Data float after RD ALE LOW to valid data in Address to valid data in (non-Extended Addressing Mode) Address (A16-A22) to valid data in (Extended Addressing Mode) ALE LOW to RD or WR LOW Address valid to WR or RD LOW (non-Extended Addressing Mode) Address (A16-A22) valid to WR or RD LOW (Extended Addressing Mode) 0 tCLCL - 15 0.5tCLCL - 15 0.5tCLCL - 15 0.5tCLCL - 12 1.5tCLCL - 20 0 3tCLCL - 20 3tCLCL - 20 0 1.5tCLCL - 10 2tCLCL - 5 tCLCL - 10 clock[4] Max 24 2tCLCL - 30 1.5tCLCL - 35 0.5tCLCL - 5 2.5tCLCL - 30 1.5tCLCL - 34 8 2.5tCLCL - 40 tCLCL - 15 4tCLCL - 35 4.5tCLCL - 30 3.5tCLCL - 35 1.5tCLCL + 20 0 105 105 0 52 78 31 8 42 41.5 26 5 5 fOSC = 24 Min MHz[4] Max 53 27 15 74 28 8 64 26 131 157 110 82 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Data Memory
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Table 9: AC electrical characteristics...continued Tamb = 0 C to +70 C for commercial unless otherwise specified. Formulae including tCLCL assume oscillator signal with 50/50 duty cycle.[1][2][3] Symbol Figure Parameter 4.5 V < VDD < 5.5 V Variable Min tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tXHDV
[1] [2] [3] [4]
Unit fOSC = 24 MHz[4] Max 0 30 4 4 173 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min 5 9 135 9 16 16 250 198 26 0 -
clock[4] Max 0 0.5tCLCL + 10 tCLCL - tCLCX tCLCL - tCHCX 4 4 5tCLCL - 35
7 7 7 6 6, 7 9 9 9 9 8 8 8 8 8
Data valid to WR transition Data hold after WR Data valid to WR HIGH RD LOW to address float RD or WR HIGH to ALE HIGH HIGH time LOW time Rise time Fall Time Serial port clock cycle time Output data set-up to clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
0.5tCLCL - 15 0.5tCLCL - 11 3.5tCLCL - 10 0.5tCLCL - 11 16 16 6tCLCL 5tCLCL - 10 0 -
External Clock
Shift Register
Output data hold after clock rising edge tCLCL - 15
Parameters are valid over operating temperature range unless otherwise specified. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.
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Table 10: Symbol tHD;STA tLOW tHIGH tRC tFC tSU;DAT1 tSU;DAT2 tSU;DAT3 tHD;DAT tSU;STA tSU;STO tBUF tRD tFD
[1] [2] [3] [4]
I2C-bus interface characteristics Parameter START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time Data set-up time SDA set-up time SDA set-up time Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time SDA fall time before repeated START condition before STOP condition Conditions Input 7tCLCL 8tCLCL 7tCLCL 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 7tCLCL 7tCLCL 7tCLCL 1 s 300 ns Output > 4.0 s > 4.7 s > 4.0 s < 0.3 s > 10tCLCL - tRD > 1 s > 4tCLCL > 4tCLCL - tFC > 4.7 s > 4.0 s > 4.7 s < 0.3 s
Parameters are valid over operating temperature range unless otherwise specified. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.
10.1 Explanation of AC symbols
Each timing symbol has five characters. The first character is always `t' ( = time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A -- Address C -- Clock D -- Input data H -- Logic level HIGH I -- Instruction (program memory contents) L -- Logic level LOW, or ALE P -- PSEN Q -- Output data R -- RD signal t -- Time V -- Valid W -- WR signal X -- No longer a valid logic level Z -- Float
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80C51 8-bit microcontroller family with extended memory
Examples: tAVLL -- Time for address valid to ALE LOW. tLLPL -- Time for ALE LOW to PSEN LOW.
10.2 Timing diagrams
tLHLL ALE
tLLPL tLLIV tPLIV
tPLPH
PSEN tAVLL tLLAX PORT 0 A0-A7
tPLAZ tPXIX INSTR IN tAVIV1 tAVIV
tPXIZ
A0-A7
PORT 2
P2.0-P2.7 OR A8-A15 OR A16-A22,P2.7
P2.0-P2.7 OR A8-A15
002aaa150
Fig 5. External program memory read cycle.
ALE tWHLH PSEN tLLDV tLLWL RD tLLAX tAVLL PORT 0 tAVWL A0-A7 tAVWL1 tAVDV1 tAVDV P2.0-P2.7 OR A8-A15
P2.0-P2.7 OR A8-A15 OR A16-A22,P2.7
tRLRH
tRLAZ
tRLDV tRHDX DATA in
tRHDZ INSTR IN
A0-A7 FROM PCL
PORT 2
002aaa151
Fig 6. External data memory read cycle.
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ALE tWHLH PSEN tLLWL WR tLLAX tAVLL PORT 0 A0-A7 tQVWX tQVWH DATA OUT tAVWL1 tAVWL PORT 2
P2.0-P2.7 OR A8-A15 OR A16-A22,P2.7
tWLWH
tWHQX INSTR IN
A0-A7 FROM PCL
P2.0-P2.7 OR A8-A15
002aaa153
Fig 7. External data memory write cycle.
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK tXHQX
tQVXH OUTPUT DATA 0 WRITE TO SBUF
1
2 tXHDX
3
4
5
6
7
tXHDV INPUT DATA VALID CLEAR RI VALID VALID VALID VALID VALID VALID
SET TI
VALID
SET RI
002aaa155
Fig 8. Shift register mode timing.
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VDD -0.5 V 0.45 V
0.7 VDD 0.2 VDD -0.1 V tCHCX tCHCL tCLCX tCLCL tCLCH
002aaa160
Fig 9. External clock drive.
11. Test information
VDD ICC RST VDD VDD P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VDD
002aaa161
Fig 10. ICC test condition, active mode (all other pins are disconnected).
VDD ICC RST VDD VDD P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS
002aaa162
Fig 11. ICC test condition, idle mode (all other pins are disconnected).
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VDD -0.5 V 0.45 V
0.7 VDD 0.2 VDD -0.1 V tCHCL tCLCX tCLCL tCHCX tCLCH
002aaa163
Fig 12. Clock signal waveform for ICC tests in active and idle modes (tCLCH = tCHCL = 5 ns).
VDD ICC RST VDD VDD P0 EA (NC) XTAL2 XTAL1 VSS
002aaa164
Fig 13. ICC test condition, power-down mode (all other pins are disconnected, VDD = 2.0 V to 5.5 V).
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12. Package outline
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
eD y X A ZE
eE
39
29 28
bp
40
b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 Lp detail X
1
pin 1 index
E
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A A3 D(1) E(1) e eD eE HD bp b1 max. min.
mm 4.57 4.19 0.51 0.25 0.01 3.05 0.53 0.33 0.81 0.66
HE
k
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
ZD(1) ZE(1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.63 0.59 0.63 0.59
45 o
0.180 inches 0.02 0.165
0.021 0.032 0.656 0.656 0.05 0.12 0.013 0.026 0.650 0.650
0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 01-11-14
Fig 14. SOT187-2.
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LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm
SOT389-1
c
y X
A 33 34 23 22 ZE
e E HE wM bp 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X L Lp A A2 A1 pin 1 index (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.45 0.30 c 0.20 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.14 0.85 1.14 0.85 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT389-1 REFERENCES IEC 136E08 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 02-06-07
Fig 15. SOT389-1.
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13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
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* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
13.5 Package related soldering information
Table 11: Package[1] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, USON, VFBGA Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable Reflow[2] suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4] HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[8],
[1] [2]
suitable not WQCCN..L[8] recommended[5][6] not recommended[7] not suitable
suitable suitable suitable not suitable
PMFP[9],
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 12299
Product data
Rev. 02 -- 13 November 2003
29 of 33
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[3]
[4]
[5] [6] [7] [8]
[9]
9397 750 12299
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 13 November 2003
30 of 33
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
14. Revision history
Table 12: Rev Date 02 01 20031113 20030508 Revision history CPCN Description Product data (9397 750 12299); ECN 853-2422 01-A14403 of 6 November 2003
*
Figure 6 "External data memory read cycle." on page 22; adjusted drawing.
Product data (9397 750 11359); ECN 853-2422 29812 of 14 April 2003
9397 750 12299
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 13 November 2003
31 of 33
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
15. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Licenses
Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 12299
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 13 November 2003
32 of 33
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
Contents
1 2 2.1 2.2 2.3 3 3.1 4 5 6 6.1 6.1.1 6.1.2 6.2 7 7.1 7.2 7.3 7.4 8 9 10 10.1 10.2 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Complete features . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Plastic leaded chip carrier . . . . . . . . . . . . . . . . 6 Plastic low profile quad flat package. . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 11 Flash memory description . . . . . . . . . . . . . . . 11 Memory arrangement . . . . . . . . . . . . . . . . . . . 12 Special function registers . . . . . . . . . . . . . . . . 12 Security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 18 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Explanation of AC symbols. . . . . . . . . . . . . . . 21 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 22 Test information . . . . . . . . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29 Package related soldering information . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 32 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
(c) Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 November 2003 Document order number: 9397 750 12299

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