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| Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET FEATURES * 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance PHP130N03LT, PHB130N03LT SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 75 A g s RDS(ON) 6 m (VGS = 5 V) RDS(ON) 5 m (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB130N03LT is supplied in the SOT404 surface mounting package. PINNING PIN 1 2 3 tab gate drain1 source drain DESCRIPTION SOT78 (TO220AB) tab SOT404 tab 2 1 23 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C; VGS = 5 V Tmb = 100 C; VGS = 5 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 30 30 13 75 75 240 187 175 UNIT V V V A A A W C 1 It is not possible to make connection to pin 2 of the SOT404 package. January 1998 1 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET ESD LIMITING VALUE SYMBOL PARAMETER VC Electrostatic discharge capacitor voltage, all pins CONDITIONS PHP130N03LT, PHB130N03LT MIN. - MAX. 2 UNIT kV Human body model (100 pF, 1.5 k) THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT 60 50 0.8 K/W K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS V(BR)GSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C IG = 1 mA VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175C Forward transconductance VDS = 25 V; ID = 25 A Gate-source leakage current VGS = 5 V; VDS = 0 V; Tj = 175C Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 75 A; VDD = 24 V; VGS = 5 V MIN. 30 27 10 1 0.5 20 TYP. MAX. UNIT 1.5 5 4.5 40 0.02 0.05 92 10 36 45 120 225 100 3.5 4.5 7.5 5000 1150 500 2 2.3 6 5 11 1 10 10 500 60 170 300 135 V V V V V V m m m S A A A A nC nC nC ns ns ns ns nH nH nH pF pF pF VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Resistive load Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz January 1998 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP130N03LT, PHB130N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 75 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 25 V TYP. MAX. UNIT 0.85 1.0 100 0.6 75 240 1.2 A A V ns C AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. 500 UNIT mJ Drain-source non-repetitive ID = 75 A; VDD 15 V; unclamped inductive turn-off VGS = 5 V; RGS = 50 ; Tmb = 25 C energy 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating ID (A) 140 120 100 80 60 40 20 Current Derating Limited by package 0 20 40 60 80 100 Tmb / C 120 140 160 180 0 0 20 40 60 80 100 120 140 160 180 Tmb / C Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V January 1998 3 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP130N03LT, PHB130N03LT 1000 Drain current, ID (A) S/ ID 7506-30 RDS(ON) / mOhm 10 3 9506-30 100 RD S(O = N) VD 8 tp = 10 us 100 us DC 1 ms 10 ms 100 ms 3.5 4 5 6 6 4 2 10 1 1 10 Drain-source voltage, VDS (V) 100 0 0 20 40 ID / A 60 80 100 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Zth / (K/W) 1E+00 Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS ID / A 100 9506-30 0.5 1E-01 0.2 0.1 0.05 1E-02 0.02 0 1E-03 1E-07 80 60 Tj / C = 175 25 P D tp D= tp T t 40 T 20 1E-05 1E-03 t/s 1E-01 1E+01 0 0 1 2 VGS / V 3 4 5 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID / A 6 3.5 5 3 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj gfs / S 100 BUK9506-30 100 9506-30 80 80 60 VGS / V = 2.8 60 Tj / C = 25 40 2.6 2.4 2.2 40 175 20 20 0 0 2 4 VDS / V 6 8 10 0 0 20 40 ID / A 60 80 100 Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V January 1998 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP130N03LT, PHB130N03LT a 2 30V TrenchMOS 10000 C / pF 9506-30 Ciss 1.5 1 1000 Coss Crss 0.5 0 -100 -50 0 50 Tj / C 100 150 200 100 0.1 1 VDS / V 10 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V VGS(TO) / V max. 2 typ. 1.5 min. 1 BUK959-60 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz VGS / V 2.5 5 9506-30 4 VDS / V = 6 3 24 2 0.5 1 0 -100 -50 0 50 Tj / C 100 150 200 0 0 20 40 QG / nC 60 80 100 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Sub-Threshold Conduction Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 75 A; parameter VDS IF / A 1E-01 100 9506-30 1E-02 2% typ 98% 80 1E-03 60 Tj / C = 175 40 25 1E-04 20 1E-05 0 0 0.5 1 VSDS / V 1.5 2 1E-05 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj January 1998 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHP130N03LT, PHB130N03LT 120 110 100 90 80 70 60 50 40 30 20 10 0 WDSS% + L VDS VGS 0 RGS T.U.T. R 01 shunt VDD -ID/100 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) January 1998 6 Rev 1.300 |
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