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Product Features
Operating Frequency up to 150 MHz Low-Noise Phase-Locked Loop Clock Distribution to meet 133 MHz Registered DIMM Synchronous DRAM module specifications for server/workstation/PC applications Allows Clock Input to have Spread Spectrum modulation for EMI reduction Zero Input-to-output delay: Distribute One Clock Input to one bank of five and one bank of four outputs, with separate output enables Low jitter: Cycle-to-Cycle jitter 75ps max. On-chip series damping resistor at clock output drivers for low noise and EMI reduction Operates at 3.3V VCC Package: Plastic 24-pin TSSOP (L)
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PI6C2509-133
Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs
Product Description
The PI6C2509-133 is a quiet, low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing 5 clocks for the first bank, and an additional 4 clocks for the second bank. This clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.
Logic Block Diagram
1G 2G CLK_IN FB_IN AVCC 4 PLL 2Y[0:3] 5
Product Pin Configuration
AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FB_OUT 24 1 23 2 22 3 4 24-Pin 21 20 5 L 19 6 18 7 17 8 16 9 15 10 14 11 13 12 CLK_IN AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FB_IN
1Y[0:4]
FB_OUT
1
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06/01/99
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PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs
Functional Table
Input Control X(1)G L H Outputs X(1)Y[0:3] L CLK _IN FB_O UT CLK _IN CLK _IN
Note: 1. X is either 1 or 2
Pin Functions
Pin Name CLK_IN FB_IN 1G 2G FB_OUT 1Y[0:4] 2Y[3:0] Pin No. 24 13 11 14 12 3,4,5,8,9 16,17, 20, 21 23 1 2,10,15,22 6,7,18,19 Type I I I I O O O De s cription Clock input. CLK_IN allows spread spectrum. Feedback input. FB_IN provides the feedback signal to the internal PLL. Output bank enable. When 1G is LOW, outputs 1Y[0:4] are disabled to a logic low state. When 1G is HIGH, all outputs 1Y[0:4] are enabled. Output bank enable. When 2G is LOW, outputs 2Y[0:3] are disabled to a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled. Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs 1Yx, 2Yx. Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. Analog power supply. AVCC can be also used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK_IN. is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply. Ground.
AVCC AGND VCC GND
Power Ground Power Ground
2
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06/01/99
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PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs
DC Specifications
Absolute maximum ratings over operating free-air temperature range.
Symbol VI VO VI_DC IO_DC Power TSTG
Parame te r Input voltage range Output voltage range DC input voltage DC output current Maximum power dissipation at TA = 55C in still air Storage temperature
M in.
M ax. VCC + 0.5 +5.0 100 1.0
Units
- 0.5
V
mA W C
- 65
150
Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parame te r ICC CI CO
Te s t Conditions VI = VCC or GND; IO = 0(1) VI = VCC or GND VO = VCC or GND
VCC 3.6V 3.3V
M in.
Typ.
M ax. 10
Units A pF
4 6
Note: 1. Continuous output current Recommended Operating Conditions
Symbol VCC VIH VIL VI TA
Parame te r Supply voltage High level input voltage Low level input voltage Input voltage O perating free- air temperature
M in. 3.0 2.0
M ax. 3.6
Units
0.8 0.0 0 VCC 70
V
C
Electrical characteristics over recommended operating free-air temperature range
Pull Up/Down Currents of PI6C2509-133, VCC = 3.0V
Symbol IOH Parame te r Pull- up current Pull- up current Pull- down current Pull- down current Condition VOUT = 2.4V VOUT = 2.0V VOUT = 0.8V VOUT = 0.55V 19 13 M in. M ax. - 13.6 - 22 mA Units
IOL
3
PSXXXX
06/01/99
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PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs
AC Specifications
Timing requirements over recommended ranges of supply voltage and operating free-air temperature.
Symbol FCLK Parame te r Input clock frequency Input clock duty cycle Stabilization time after power up M in. 25 40 M ax. 150 60 1 Units MHz % ms
Switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL=30pF
Parame te r tphase error, with and without Spread Spectrum Jitter, cycle- to- cycle with and without Spread Spectrum Skew, at 133 MHz Duty cycle tr, rise- time, 0.4V to 2.0V tf, fall- time, 2.0V to 0.4V From CLK_IN at 133 MHz Any Output or FB_OUT in CLKn at 133 MHz Any Y or FB_OUT Any Y or FB_OUT 45 50 1.0 1.1 To FB_IN Output or FB_OUT in CLKn+1 VCC = 3.3V 0.3V, 0-70C M in. 150 75 Typ. M ax. +150 +75 150 55 % ns ps Units
Note: These switching parameters are guaranteed, but not production tested.
Package Mechanical Information
Plastic 24-pin Thin Shrink Small-Outline Package (L package).
24
.169 .177
4.3 4.5
1
.303 .311 7.7 7.9
SEATING PLANE .047 Max 1.20 .004 .008 0.45 0.75 .018 .030 0.09 0.20
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006 0.05 0.15
.252 BSC 6.4
Ordering Information
Part Numbe r PI6C2509- 133 Ope rating Fre que ncy Range 25 MHz - 150 MHz Orde ring P/N PI6C2509- 133L
X.XX X.XX
DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
4
PSXXXX 06/01/99

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