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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2510-133 Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Features * * Description The PI6C2510-133 is a "quiet," low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable. This clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground. * * * * * * Operating Frequency up to 150 MHz Low-Noise Phase-Locked Loop Clock Distribution that meets 133 MHz Registered DIMM Synchronous DRAM modules for server/workstation/PC applications Allows Clock Input to have Spread Spectrum modulation for EMI reduction Zero Input-to-Output delay: Distribute one Clock Input to one Bank of Ten outputs, with an output enable. Low jitter: Cycle-to-Cycle jitter 75ps max. On-chip series damping resistor at clock output drivers for low noise and EMI reduction Operates at 3.3V VCC Packaging(Pb-free & Green available): - 24-pin TSSOP (L) Block Diagram Pin Configuration AGND VCC Y0 Y1 Y2 GND GND Y3 Y4 VCC G FB_OUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK_IN AVCC VCC Y9 Y8 GND GND Y7 Y6 Y5 VCC FB_IN G 10 Y[0:9] FB_OUT CLK_IN FB_IN AVcc PLL 24-Pin L Functional Table Inputs G L H Outputs Y[0:9] L CLK_IN FB_OUT CLK_IN CLK_IN 1 PS8383B 09/14/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2510-133 Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Pin Functions Pin Name CLK_IN FB_IN G Pin Numbe r 24 13 11 Type I I I De s cription Reference Clock input. CLK_IN allows spread spectrum. Feedback input. FB_IN provides the feedback signal to the internal PLL Output bank enable. When G is LOW, outputs Y[0:9] are disabled to a logic low state. When G is HIGH, all outputs Y[0:9] are enabled. Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs Y[0:9]. Clock outputs. These outputs provide low- skew copies of CLK_IN . Each output has an embedded series- damping resistor. Analog power supply. AVCC can be also used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK_IN buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. FB_OUT 12 O Y[0:9] 3 , 4 , 5 , 8 , 9 , 15 16,17,20,21 O AVCC 23 Power AGND 1 Ground VCC 2,10,14,22 Power Power supply GND 6,7,18,19 Ground Ground 2 PS8383B 09/14/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2510-133 Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs DC Specifications Absolute maximum ratings over operating free-air temperature range. Symbol VI VO VI_DC IO_DC Power TSTG Input voltage range Output voltage range DC input voltage DC output current Parame te r M in. M a x. VCC + 0.5 +5.0 100 1.0 Units - 0.5 V mA W oC Maximum power dissipation at TA = 55oC in still air Storage temperature - 65 150 Note: Stress beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Parame te r ICC CI CO Te s t Conditions VI = VCC or GND; IO = 0 VI = VCC or GND VO=VCC or GND VCC 3.6V 3.3V M in. Typ. M ax. 10 Units A pF 4 6 Recommended Operating Conditions Symbol VCC VIH VIL VI TA Supply voltage High level input voltage Low level input voltage Input voltage Operating free- air temperature 0.0 0 Parame te r M in. 3.0 2.0 0.8 VCC 70 oC M a x. 3.6 Units V Electrical characteristics over recommended operating free-air temperature range Pull Up/Down Currents of PI6C2510-133, VCC = 3.0V Symbol IOH Parame te r Pull- up current Pull- up current Pull- down current Pull- down current Condition VOUT = 2.4V VOUT = 2.0V VOUT = 0.8V VOUT = 0.55V 19 13 M in. M a x. - 13.6 - 22 mA Units IOL 3 PS8383B 09/14/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2510-133 Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs AC Specifications Timing requirements over recommended ranges of supply voltage and operating free-air temperature. Symbol FCLK Parame te r Input clock frequency Input clock duty cycle Stabilization Time after power up M in. 25 40 M a x. 150 60 1 Units MHz % ms Switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL=30pF Parame te r tphase error, with and without spread spectrum Jitter, cycle- to- cycle, with and without spread spectrum Skew, at 133 MHz Duty cycle tr, rise- time, 0.4V to 2.0V tf, fall- time, 2.0V to 0.4V Note: These switching parameters are guaranteed, but not production tested. From CLK_IN at 133 MHz Any Output or FB_OUT in CLKn at 133 MHz Any Y or FB_OUT To FB_IN Output or FB_OUT in CLKn + 1 VCC = 3.3V 0.3V, 0-70C M in. -150 Typ. M ax. +150 Units -75 +75 ps 150 Any Y or FB_OUT 45 50 1.0 1.1 55 % ns 4 PS8383B 09/14/04 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2510-133 Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs Packaging Mechanical: 24-pin TSSOP (L) 24 .169 .177 4.3 4.5 .004 .008 0.09 0.20 1 .303 .311 7.7 7.9 0.45 0.75 .047 1.20 Max .018 .030 SEATING PLANE .252 BSC 6.4 .0256 BSC 0.65 .007 .012 0.19 0.30 .002 .006 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS Ordering Information Ordering Code PI6C2510-133L PI6C2510-133LE Package Code L L Package Type 24-pin TSSOP Pb-free & Green, 24-pin TSSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 5 PS8383B 09/14/04 |
Price & Availability of PI6C2510-133
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