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RFD16N05, RFD16N05SM
Data Sheet July 1999 File Number
2267.5
16A, 50V, 0.047 Ohm, N-Channel Power MOSFETs
The RFD16N05 and RFD16N05SM N-channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA09771.
Features
* 16A, 50V * rDS(ON) = 0.047 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFD16N05 RFD16N05SM PACKAGE TO-251AA TO-252AA BRAND F16N05 F16N05
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD16N05SM9A.
G
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD16N05, RFD16N05SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD16N05, RFD16N05SM, 50 50 16 Refer to Peak Current Curve 20 Refer to Figure 5 72 0.48 -55 to 175 300 260 UNITS V V A V W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC MIN 50 2 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 40V, ID 16A, RL = 2.5 Ig(REF) = 0.8mA (Figure 13) TO-251 and TO-252 TYP 14 30 55 30 900 325 100 MAX 4 1 25 100 0.047 65 125 80 45 2.2 2.083 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(10) Q(TH) CISS COSS CRSS RJC RJA
VGS = 20V ID = 16A, VGS = 10V (Figure 9) VDD = 25V, ID = 8A, RL = 3.125, VGS = 10V, RGS = 25 (Figure 13)
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse test: pulse width 250s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr ISD = 16A ISD = 16A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
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RFD16N05, RFD16N05SM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER
Unless Otherwise Specified
20
1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 ID, DRAIN CURRENT (A)
16
12
8
4
0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TENPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 ZJC, NORMALIZED THERMAL IMPEDANCE 0.5 0.2 PDM 0.1 0.1 0.05 0.02 0.01 t1
SINGLE PULSE
0.01 10-5
t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100 ID, DRAIN CURRENT (A)
SINGLE PULSE TJ = MAX RATED TC = 25oC IDM, PEAK CURRENT (A)
200
VGS = 20V VGS = 10V
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
100s
100
= I25
175 - TC 150 TC = 25oC
10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) VDSS(MAX) = 50V 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
10ms 100ms DC 100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5
10-4
10-3 10-2 10-1 t, PULSE WIDTH (s)
100
101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RFD16N05, RFD16N05SM Typical Performance Curves
100 IAS, AVALANCHE CURRENT (A)
Unless Otherwise Specified (Continued)
50 VGS = 20V ID, DRAIN CURRENT (A) 40 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 6V 20 VGS = 10V VGS = 8V VGS = 7V
STARTING TJ = 25oC
30
10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 1 0.01 1 0.1 tAV, TIME IN AVALANCHE (ms) 10
10 VGS = 4.5V 0 0
VGS = 5V
1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V)
4
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
50
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -55oC 25oC 175oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 16A
40
2.0
30
1.5
20
1.0
10
0.5
0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
0 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0
VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
2.0
ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.5
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
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RFD16N05, RFD16N05SM Typical Performance Curves
1600 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS CISS 800 COSS 400 CRSS 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25
Unless Otherwise Specified (Continued)
VDS , DRAIN TO SOURCE VOLTAGE (V) 50 VDD = BVDSS 37.5 VDD = BVDSS 7.5 10 VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1200
25 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.125 IG(REF) = 0.8mA VGS = 10V 0 I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (ms)
5
12.5
2.5
0
80 --------------------I G ( ACT )
I G ( REF )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
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RFD16N05, RFD16N05SM Test Circuits and Waveforms
VDS RL VDD VDS VGS = 20V VGS
+
(Continued)
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) IG(REF) 0 VGS = 10V
DUT IG(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORM
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RFD16N05, RFD16N05SM PSPICE Electrical Model
.SUBCKT RFD16N05 2 1 3 ; rev 10/31/94
CA 12 8 1.788e-10 CB 15 14 1.875e-10 CIN 6 8 8.33e-10
DPLCAP 5 LDRAIN RSCL1 RSCL2 + 51 5 51 ESG + 6 8 VTO 6 + 21 MOS1 RIN CIN 8 RSOURCE 7 LSOURCE 3 SOURCE 16 ESCL 50 RDRAIN 11 EBREAK MOS2 17 18 + DBODY DBREAK
DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 64.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1
GATE
10
DRAIN 2
LDRAIN 2 5 1e-9 LGATE 1 9 4.56e-9 LSOURCE 3 7 4.13e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 0.4e-3 RGATE 9 20 3.0 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 21.5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
1 LGATE
9
20
EVTO + 18 8
RGATE
S1A 12 13 8 S1B CA EGS + 6 8
S2A 14 13 S2B 13 CB + EDS 5 8 14 IT 15 17 RBREAK 18 RVTO 19 VBAT +
VBAT 8 19 DC 1 VTO 21 6 0.82 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/94,7))} .MODEL DBDMOD D (IS = 2.5e-13 RS = 7.1e-3 TRS1 = 3.04e-3 TRS2 = -10e-6 CJO = 1.12e-9 TT = 5.6e-8) .MODEL DBKMOD D (RS = 2.51e-1 TRS1 = -6.57e-4 TRS2 = 1.66e-6) .MODEL DPLCAPMOD D (CJO = 6.1e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.96 KP = 16.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -7.19e-7) .MODEL RDSMOD RES (TC1 = 5.45e-3 TC2 = 1.66e-5) .MODEL RSCLMOD RES (TC1 = 1.25e-3 TC2 = 17e-6) .MODEL RVTOMOD RES (TC1 = -5.15e-3 TC2 = -4.83e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.25 VOFF= -3.25) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.25 VOFF= -5.25) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.56 VOFF= 5.56) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.56 VOFF= 0.56) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
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RFD16N05, RFD16N05SM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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