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V54C365324V
Clock Frequency (tCK) CAS Latency Cycle Time (tCK) Access Time (tAC )
V54C365324V 200/183/166/143 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 2M X 32 SDRAM 4 BANKS X 512Kbit X 32
PRELIMINARY
-5
200 3 5 5
-55
183 3 5.5 5.5
-6
166 3 6 6
-7
143 3 7 6
-8
125 3 8 6
Unit
MHz clocks ns ns
Features
s JEDEC Standard 3.3V Power Supply s The V54C365324V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 2, 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave s DQM 0-3 for Byte Masking s Auto & Self Refresh s 2K Refresh Cycles/32 ms s Burst Read with Single Write Operation
Description
The V54C365324V is a 67,108, 864 bits synchronous high data rate DRAM organized as 4 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.
V54C365324V Rev. 1.2 August 2001
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V54C365324V
PIN CONFIGURATION
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VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V54C365324V Rev. 1.2 August 2001
86 Pin TSOP (II) (400mil x 875mil) (0.5mm Pin pitch)
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
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V54C365324V
DQMi
Column Decoder
RAS CAS WE DQMi
Timing Register
Row Decoder
Row Address Buffer Column Address Counter Latency & Burst Length CLK Programming Register A0-A10, BA0, BA1 Column Address Buffer Row Addresses
Refresh Counter
Address
A0-A7 Column Addresses
V54C365324V Rev. 1.2 August 2001
3
Output Buffer
CLK CKE CS
Sense Amplifier
DQMi Bank0 512K x 32 Bank1 512K x 32 Bank2 512K x 32 Bank3 512K x 32
Input Buffer
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Block Diagram
Write Control Logic MUX
DQ0-DQ31
V54C365324V
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Pin
CLK CKE
Signal Pin Description
Name
Clock Input Clock Enable
Input Function
System clock input. Active on the positive rising edge to sample all inputs Activates the CLK signal when high and deactivates the CLK when low. CKE low initiates the power down mode, suspend mode, or the self refresh mode Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMi Latches row addresses on the positive edge of CLK with RAS low. Enables row access & precharge Latches column addresses on the positive edge of CLK with CAS low. Enables column access Enables write operation During a bank activate command, A0-A10 defines the row address. During a read or write command, A0-A7 defines the column address. In addition to the column address A10 is used to invoke auto precharge BA define the bank to be precharged. A10 is low, auto precharge is disabled during a precharge cycle, If A10 is high, all bank will be precharged, if A10 is low, the BA0, BA1 is used to decide which bank to precharge Selects which bank to activate. Data inputs/output are multiplexed on the same pins Makes data output Hi-Z. Blocks data input when DQM is active Power Supply. +3.3V 0.3V/ground Provides isolated power/ground to DQs for improved noise immunity
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE A0-A10
Write Enable Address
BA0, BA1 DQ0-DQ31 DQMi VDD/VSS VDDQ/VSSQ NC
Bank Select Data Input/Output Data Input/Output Mask Power Supply/Ground Data Output Power/Ground No Connection
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V54C365324V
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VCC and VCCQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 s is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
V54C365324V Rev. 1.2 August 2001
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A9 0 1 A6 0 0 0 0 1 1 1 A5 0 0 1 1 0 1 1
Address Input for Mode Set (Mode Register Operation)
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus (Ax)
Write Burst Length
Test Mode
CAS Latency
BT
Burst Length
Mode Register
Write Burst Length
Length Burst Single Bit
Test Mode
A8 0 A7 0 Mode Mode Reg Set
Burst Type
A3 0 1 Type Sequential Interleave
CAS Latency
A4 0 1 0 1 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve Reserve
Burst Length
Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 Sequential 0 1 0 1 0 1 0 1 1 2 4 8 Reserve Reserve Reserve Full Page Interleave 1 2 4 8 Reserve Reserve Reserve Reserve
Power On and Initialization
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table.
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V54C365324V
Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies with an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages.
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 200 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command.
Burst Length and Sequence:
Burst Starting Address Length (A2 A1 A0) 2 4 xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 0, 1, 2, 3, Sequential Burst Addressing (decimal) 0, 1 1, 0 1, 2, 3, 0, 3 4 5 6 7 0 1 2 2, 3, 0, 1, 4 5 6 7 0 1 2 3 3 0 1 2 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 0, 1, 2, 3, Interleave Burst Addressing (decimal) 0, 1 1, 0 1, 0, 3, 2, 3 2 1 0 7 6 5 4 2, 3, 0, 1, 4 5 6 7 0 1 2 3 3 2 1 0 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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8 Full Page
V54C365324V Rev. 1.2 August 2001
Read and Write Operation
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes.
Cn, Cn+1, Cn+2,.....
not supported
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V54C365324V
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, A8, to determine whether the chip restores or not after the operation. If A8 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two clocks for CAS latencies 3. If A8 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command.
DQM has two functions for data I/O read and write operations. During reads, when it turns to "high" at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). DQM is used for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31.
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL).
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE "high". One clock delay is required for mode entry and exit.
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DQM Function Suspend Mode Power Down
V54C365324V Rev. 1.2 August 2001
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. With A8 being low, the BA is used select bank to precharge. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3. Writes require a time delay twr from the last data out to apply the precharge command.
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the I/O pins before the Burst Stop Command is registered will be written to the memory.
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V54C365324V
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70 C Storage temperature range ................-55 to 150 C Input/output voltage.................. -0.3 to (VCC+0.3) V Power supply voltage .......................... -0.3 to 4.6 V Power dissipation ............................................. 1 W Data out current (short circuit) ...................... 50 mA
*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operation and Characteristics
TA = 0 to 70 C; VSS = 0 V; VCC,VCCQ = 3.3 V 0.3 V
Limit Values Parameter
Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < V OUT < VCC)
Note: 1. All voltages are referenced to VSS. 2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
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V54C365324V Rev. 1.2 August 2001
Symbol
VIH VIL VOH VOL II(L) IO(L)
min.
2.0 - 0.3 2.4 - -5
max.
Vcc+0.3 0.8 - 0.4 5
Unit
V V V V A A
Notes
1, 2 1, 2 3 3
-5
5
8
V54C365324V
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters are measured with continuous data stream during read access and all DQ toggling.
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Symbol
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6 Notes:
V54C365324V Rev. 1.2 August 2001
Operating Currents (TA = 0 to 70C, VCC = 3.3V 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Max. Parameter & Test Condition
1 bank operation Operating Current tRC = tRCMIN., tRC = tCKMIN. Active-precharge command cycling, without Burst Operation Precharge Standby Current in Power Down Mode CS =VIH , CKE VIL(max) Precharge Standby Current in Non-Power Down Mode CS =VIH , CKE VIL(max) Active Standby Current in Power-down mode Active Standby Current in non Power-down mode Burst Operating Current tCK = min Read/Write command cycling Auto Refresh Current tCK = min Auto Refresh command cycling Self Refresh Current Self Refresh Mode, CKE=0.2V tCK = min. tCK = Infinity tCK = min. tCK = Infinity CKE VIL(max), tck = min CKE VIL(max), tck = infinity CKE S V IL(max), tck = min CKE S VIL(max), tck = infinity CL = 3 CL = 2
-5
250
-55
240
-6
230
-7
210
-8
190
Unit
mA
Note
3
2
2
2
2
2
mA
3
2 35
2 35
2 35
2 35
2 35
mA mA
3
15
15
15
15
15
mA
3 3 60 50 340 200 200
3 3 60 50 320 200 190
3 3 60 50 310 180 180
3 3 60 50 280 180 160
3 3 60 50 250 180 150
mA mA mA mA mA 3, 4
mA
3
2 L-Power 400
2 400
2 400
2 400
2 400
mA A
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V54C365324V
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# Clock and Clock Enable
1 tCK 2 tCK 3 tAC 4 5 6 tCH tCL tT
AC Characteristics (1,2,3)
TA = 0 to 70C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns
Limit Values -5 Symbol Parameter -55 -6 -7 -8
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock Cycle Time CAS Latency = 3 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time
5 10
- -
5.5 10
- -
6 10
- -
7 10
- -
8 10
- -
ns ns
- -
200 100
- -
200 100
- - `
166 100
- -
143 100
- -
125 100
MHz MHz
- - 2.5 2.5 1
5 7 - - 10
- - 2.5 2.5 1
5.5 7 - - 10 2.5 2.5 1
6 7 - - 10
- - 2.5 2.5 1
6 7 - - 10
- - 3 3 1
6 7 - - 10
ns ns ns ns ns
2 3
Setup and Hold Times
7 8 9 10 11 12 13 14 tCS tAS tDS tCKS tCH tAH tDH tCKH Command Setup Time Address Setup Time Data In Setup Time CKE Setup Time Command Hold Time Address Hold Time Data In Hold Time CKE Hold Time 2 2 2 2 1 1 1.5 1 - - - - - - - - 2 2 2 2 1 1 1.5 1 - - - - - - - - 2 2 2 2 1 1 1.5 1 - - - - - - - - 2 2 2 2 1 1 1.5 1 - - - - - - - - 2.5 2.5 2.5 2.5 1 1 1.5 1 - - - - - - - - ns ns ns ns ns ns ns ns 4 4 4 4 4 4 4 4
Common Parameters
15 16 17 18 19 tRCD tRAS tRC tRP tRRD tCCD tRCS tSB Row to Column Delay Time Row Active Time Row Cycle Time Row Precharge Time Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period Mode Register Set-up time Power Down Mode Entry Time 15 40 60 15 10 - 100K - - - 16 45 63 17 11 - 100K - - - 16 48 66 18 12 - 100K - - - 16 48 70 21 14 - 100K - - - 16 48 72 24 16 - 100K - - - ns ns ns ns ns 5 5 5 5 5
20 21 22
1 10 0
- - 5
1 11 0
- - 5.5
1 12 0
- - 6
1 14 0
- - 7
1 16 0
- - 8
CLK ns ns
Refresh Cycle
23 24 tREF tSREX Refresh Period (2048 cycles) Self Refresh Exit Time - 32 - 32 - 32 - 32 - 32 ms 6
2 CLK + tRC
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V54C365324V
TA = 0 to 70C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns
Limit Values -5 # Symbol Parameter -55 -6 -7 -8
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Read Cycle
25 27 tOH tHZ tDQZ 28
AC Characteristics (1,2,3) (Continued)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.5 CAS Latency = 3 CAS Latency = 2 DQM Data Out Disable Latency - - 2
- 5 7 -
2.5 - - 2
- 5.3 7 -
2.5 - - 2
- 5.5 7 -
2.5 - - 2
- 5.5 7 -
2.5 - - 2
- 6 7 -
ns ns
CLK
Write Cycle
29 tWR Write Recovery Time CAS Latency = 3 CAS Latency = 2 DQM Write Mask Latency 5 10 0 - - - 5.5 10 0 - - - 6 10 0 - - - 7 10 0 - - - 8 10 0 - - - ns ns CLK
30
tDQW
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet. 2. AC timing tests have VIL = 0.8V and V IH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown in Figure 1.
tCK VIH CLK VIL
+ 1.4 V 50 Ohm
tT
tCS COMMAND tCH 1.4V
Z=50 Ohm
tAC tLZ tOH tAC
I/O 50 pF
1.4V
OUTPUT tHZ
Figure 1.
3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered.
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V54C365324V
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Timing Diagrams
1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a Full Page Burst Write Operation 8.2 Termination of a Full Page Burst Write Operation
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2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
CAS latency = 2
tCK2, I/O's
CAS latency = 3
tCK3, I/O's
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(CAS latency = 3)
T0 CLK ADDRESS COMMAND
: "H" or "L" Bank A Activate
READ A
V54C365324V Rev. 1.2 August 2001
1. Bank Activate Command Cycle
T1
T
T
T
T
T
..........
Bank A Row Addr.
Bank A Col. Addr.
..........
Bank B Row Addr.
Bank A Row Addr.
tRCD
NOP NOP Write A with Auto Precharge .......... Bank B Activate
tRRD
NOP Bank A Activate
tRC
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
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4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
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T0 CLK COMMAND
READ A CAS latency = 2
3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, I/O's
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
DQM
tDQZ
tDQW
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
I/O's
: "H" or "L"
DOUT A0 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
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V54C365324V
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3
T0 CLK
tDQW
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T0 CLK DQM COMMAND
NOP CAS latency = 2
4.2 Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2)
T1 T2 T3 T4 T5 T6 T7 T8
tDQW tDQZ
1 Clk Interval BANK A ACTIVATE
NOP
NOP
READ A
WRITE A
NOP
NOP
NOP
Must be Hi-Z before the Write Command
tCK2, I/O's
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
T1
T2
T3
T4
T5
T6
T7
T8
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
CAS latency = 2
tCK1, I/O's
CAS latency = 3
DOUT A0
DOUT A1 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
tCK2, I/O's
: "H" or "L"
DOUT A0
DIN B0
DIN B1
DIN B2
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V54C365324V
6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
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T0 CLK COMMAND
NOP
5. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
I/O's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval
I/O's
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
V54C365324V Rev. 1.2 August 2001
16
V54C365324V
7. Burst Write with Auto-Precharge Burst Length = 2, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
CILETIV LESOM
T0 CLK COMMAND
NOP CAS latency = 2
6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, I/O's
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data must be removed from the I/O's at least one clock cycle before the Read dataAPpears on the outputs to avoid data contention.
COMMAND
BANK A ACTIVE
NOP
NOP
WRITE A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
tWR
CAS latency = 2 DIN A0 DIN A1
tRP
I/O's
CAS latency = 3
tWR
* *
tRP
I/O's
DIN A0
DIN A1
Bank can be reactivated after trp
*
Begin Autoprecharge
V54C365324V Rev. 1.2 August 2001
17
V54C365324V
CILETIV LESOM
T0 CLK COMMAND
READ A CAS latency = 2
7.2 Burst Read with Auto-Precharge Burst Length = 4, CAS latency = 1, 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DOUT A0
DOUT A1
* *
t RP
DOUT A3
DOUT A2
t RP
DOUT A2 DOUT A3
tCK3, I/O's
DOUT A0
DOUT A1
Bank can be reactivated after tRP
*
Begin Autoprecharge
V54C365324V Rev. 1.2 August 2001
18
V54C365324V
8.2 Termination of a Full Page Burst Write Operation (CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
CILETIV LESOM
(CAS latency = 2, 3)
T0 CLK COMMAND
READ A CAS latency = 2
8.1 Termination of a Full Page Burst Read Operation
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
tCK3, I/O's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
The burst ends after a delay equal to the CAS latency.
COMMAND
CAS latency = 2,3
NOP
WRITE A
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
I/O's
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
V54C365324V Rev. 1.2 August 2001
19
V54C365324V
Package Diagram
86 TSOPII-400F
11.760.20 0.4630.008
22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.61 ) 0.024 0.20 -0.03
+0.10 0.10 0.004
0.125+0.075 -0.035 0.005+0.003 -0.001
0.21 0.008
0.05 0.002
1.00 0.039
0.10 0.004
1.20 MAX 0.047
0.50 0.0197
0.05 MIN 0.010
V54C365324V Rev. 1.2 August 2001
20
( 0.50 ) 0.020
#1
#43
0.45~0.75 0.018~0.030
10.16 0.400
CILETIV LESOM
#86 #44
Unit:
Milimeter Inches
Unit : Millimeters
0~8C 0.25 TYP 0.010
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
V54C365324V
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
CILETIV LESOM
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
CENTRAL, NORTHEASTERN & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029
(c) Copyright 2000, MOSEL VITELIC Inc.
8/00 Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
CILETIV LESOM
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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