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| SL74LS86 Quad 2-Input Exclusive OR Gate This device contains four independent 2-input Exclusive-OR gates. It performs the Boolean functions Y=A B=AB+AB in positive logic. ORDERING INFORMATION SL74LS86N Plastic SL74LS86D SOIC TA = 0 to 70 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs A PIN 14 =VCC PIN 7 = GND L L H H B L H L H Output Y L H H L SLS System Logic Semiconductor SL74LS86 MAXIMUM RATINGS * Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 7.0 5.5 -65 to +150 Unit V V V C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL IOH IOL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Ambient Temperature Range 0 Parameter Min 4.75 2.0 0.8 -0.4 8.0 +70 Max 5.25 Unit V V V mA mA C DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Test Conditions VCC = min, IIN = -18 mA VCC = min, IOH = -0.4 mA VCC = min, IOL = 4 mA VCC = min, IOL = 8 mA IIH High Level Input Current VCC = max, VIN = 2.7 V VCC = max, VIN = 7.0 V IIL IO ICC Low Level Input Current Output Short Circuit Current Supply Current Total with outputs high Total with outputs low VCC = max, VIN = 0.4 V VCC = max, VO = 0 V (Note 1) VCC = max -20 2.7 0.4 0.5 40 0.2 -0.8 -100 10 15 A mA mA mA mA Min Max -1.5 Unit V V V Note 1: Not more than one output should be shorted at a time, and duration should not exceed one second. System Logic Semiconductor SLS SL74LS86 AC ELECTRICAL CHARACTERISTICS (TA=25C, VCC = 5.0 V, CL = 15 pF, RL = 2 k, t r =15 ns, tf = 6.0 ns) Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay, Input A or B to Output Y (Other input low) Propagation Delay, Input A or B to Output Y (Other input low) Propagation Delay, Input A or B to Output Y (Other input high) Propagation Delay, Input A or B to Output Y (Other input high) Min Max 23 17 30 22 Unit ns ns ns ns Figure 1. Switching Waveforms Figure 2. Switching Waveforms NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 3. Test Circuit SLS System Logic Semiconductor |
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