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| DM9095 Twisted-Pair Medium Attachment Unit General Description The DM9095 twisted-pair Media Attachment Unit (TPMAU) is designed to allow Ethernet connections to use existing Twisted-pair wiring plants through an Ethernet Attachment Unit Interface (AUI). The DM9095 provides the electrical interface between the AUI and the twisted-pair wire. The DM9095's functions include level-shifted data pass-through from one transmission media to another, collision detection, transmitting predistortion generation, receiving squelch function, selectable signal-quality-error (SQE) test generation, a linkintegrity strapping option, and automatic correction of polarity reversal on the twisted pair input. The DM9095 also includes LED drivers for transmit, receive, jabber, collision, reversed polarity detect and link status. The DM9095 is an advanced CMOS device available in 28-pin PLCC packages. Block Diagram DO + DO - AUI Data Receiver Jabber AUI Data Squelch TP Pre-Distortion Driver TPO + DTPO + DTPO TPO- MD0 MD1 MD2 DI + DI - Operation Mode Selection AUI Current Driver Collision Current Driver Link Integrity LI- Loopback Control Auto-Polarity Detection TP Data Receiver TP Data Squelch AP CI + CI - Collision Control TPI + TPI - OSC1 Crystal Oscillator LED Drivers RLED CLED XLED JLED 1 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Features * Compatible with or exceeds IEEE 802.3 standards for AUI and 10BASE-T interfaces * Internal pre-distortion generator for TP driver * Smart squelch circuitry on all received data * Selectable heartbeat function * Selectable line-integrity test with LED indication * LED indicator for transmit, receive, jabber, and collision * Advanced analog CMOS process using single 5V supply * Lower TP threshold option for long length application * Selectable auto-polarity detection and correction function with LED indication * Automatic AUI/RJ45 selection * Power-down mode * Full ESD protection Pin Configuration : DM9095L MDO GND VDD TPI+ 27 DO+ 28 LIDI+ DICI+ CIVDD AP 5 6 7 8 9 10 11 12 13 14 15 16 17 26 25 24 23 22 4 3 2 1 TPI- DO- MD1 MD2 GND TPODTPODTPO+ TPO+ DM9095L 21 20 19 18 VDD OSC1 CLED GND RLED Final Version: DM9095-DS-F02 August 21, 2000 XLED JLED 2 DM9095 Twisted-Pair Medium Attachment Unit Pin Description Pin No. 1 2 3 4 5 Pin Name GND DO+ DOMD0 LII I/O I Ground Transmitter input. A balanced differential line receiver input pair from the AUI circuit that receives 10 Mbits/s Manchester-encoded data and applies the data to the TP cable. Operation mode selection pin. Pulled high internally. Link-Integrity enable. The pin is a dual function pin that determines whether the link integrity function should be realized. When this pin, which is internally pulled-high, is configured as an input pin and tied low, the link integrity test function is enabled. While configured as an output pin, the pin drives low for link-fail state and drives high for link-pass state. The output pin can drive an LED status indicator, as in Figure 3(b) (page 6). 6 7 8 9 DI+ DICI+ CIO O Receiver outputs. A balanced output current driver pair to the AUI transceiver cable with the 10 Mbits/s Manchester-encoded data received from the twisted-pair of the network. Collision outputs. Balanced differential line driver outputs which send a 10MHz oscillation signal to the Manchester encoder/decoder in the event of a collision, jabber interrupt, or heartbeat test. +5V Power Supply Auto Polarity. This pin is a dual function pin which determines if the auto-polarity function should be enabled. The function is enabled if the pin is HIGH. The pin is also capable of driving an LED if the function is enabled. Jabber indicator. Normally off. It indicates a time-out transmission onto TP network. It turns on if the watchdog timer has timed out and the twisted-pair driver has been disabled. Crystal pin. This pin is a 20MHz frequency-reference terminal for internal chip timing. Ground Description 10 11 VDD AP I/O 12 JLED O 13 OSC1 I 14 GND - 3 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Pin Description (continued) Pin No. 15 Pin Name LCED I/O O Description Collision indicator. Normally off. It indicates a collision has been detected by the MAU. It turns on the LED if a collision occurs. Receive Indicator. Normally on. It indicates a reception from the TP network is in progress. When LI- is disabled, RLED will turn off if the MAU receives a packet. When LI- is enabled, RLED will turn off as long as the link is broken. Transmit indicator. Normally on. It indicates that a transmiwwion onto the TP network is in progress by turning off. +5V Power Supply TP driver outputs. These four outputs provide the TP drivers with pre-distortion capability. The TPO+ /TPO- outputs generate 10Mbits/s Manchester-encoded data. The DTPO+ /DTPOoutputs are one-half bit time delayed and inverted with respect to TPO+ /TPO-. Ground Operation mode selection pin. Pulled high internally Operation mode selection pin. Pulled high internally TP Receive input. A differential receiver tied to the receive transformer pair of the twisted-pair wire. The receive pair of the twisted-pair medium is driven with 10Mbits/s Manchester-encoded data. + 5V Power Supply 16 RLED O 17 XLED O 18 19 20 21 22 23 24 25 26 27 VDD TPO+ DTPO+ DTPOTPOGND MD2 MD1 TPITPI+ O O I I I 28 VDD O Final Version: DM9095-DS-F02 August 21, 2000 4 DM9095 Twisted-Pair Medium Attachment Unit Overview The DM9095 provides the interface between an AUI and a TP wire. The receive, transmit, and collision detection functions of the DM9095 are designed to meet the IEEE 802.3 10BASE-T draft standard. The receive section transfers 10Mbits/s Manchester-encoded data from the twisted-pair to the AUI, while the transmit section transfers data from the AUI cable to the TP wire. The collisiondetection function sends a 10MHz square wave onto the AUI_CI circuits after sensing data being simultaneously transmitted and received. In addition to the these functions, there are three optional operating functions. Enabling the link-integrity function causes a pulse to be transmitted in the absence of data transmission. The Receiver recognized link-integrity pulses and connects the twisted-pair link. The linkintegrity pin can be configured as an input or as an output. When the link-integrity pin is configured as an input, the function is enabled for proper setting. When the linkintegrity pin is configured as an output, the function is enabled and the status of the link is indicated. If the heartbeat function is enabled, it allows the SQE-test sequence to be transmitted to the DTE after every successful transmission on the TP wire. The option also enables normal or extended line length to be selected. When standard TP squelch levels are implemented, normal line length is used. When the TP squelch thresholds are lowered, extended line length is used. The device also contains an auto-polarity function which can be determined if the receive twisted-pair has been wired with polarity reversal. If the twisted-pair is wired with polarity reversal, the device automatically corrects for this error condition. Also, the auto-polarity function can be used with an LED to display the polarity of the receive twisted-pair wire. When power-down mode is set, the device shuts down, and the supply current is reduced to less than 10A. The DM9095 automatically pulls AUI-DI, AUI_CI, and AUI-DO into high impedance state if the twisted-pair link is not connected. The function is used to provide the Encoder/Decoder chip to use coaxial MAU. The DM9095 also includes four drivers capable of driving four LEDs to indicate the status of the receive, transmit, collision, and jabber functions. Also, when configured correctly, two additional LEDs can display auto-polarity and link-integrity status. 5 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Figure 3 (a). Typical System Application for External TPMAU in Mode 5 (Where Link Integrity Test is enabled, Auto-polarity is disabled. LI- is input pin) Final Version: DM9095-DS-F02 August 21, 2000 6 DM9095 Twisted-Pair Medium Attachment Unit DM9095 Figure 3 (b). Typical System Application for Internal TPMAU in Mode 6 (Where Link Integrity Test is enabled and Auto Polarity Function is enabled. LI- is output pin) 7 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Note: 1. Possible filters are the Pulse Engineering Inc. Figure 5. Example of Transmit Circuit Final Version: DM9095-DS-F02 August 21, 2000 8 Figure 4. Typical Loading Conditions for DI and CI DM9095 Twisted-Pair Medium Attachment Unit Function Description Transmit Functions Collision Functions The DM9095 receives transmit data from DO + /DO - and transfers it to the TP network. The input must be transformer-coupled to the AUI circuit. The receiver is able to pass differential signals as small as 300mV peak and as large as 1315mV. DC biasing is provided with internal common-mode, the common-mode is set to nominal 2.5V. An internal analog delay line is used to generate the predistortion signals at DTPO + and DTPO -. The DTPO + / DTPO - signal delays 50ns after TPO + / TPO -. A delay lock loop, referenced to the crystal clock, is used to generate the internal delay line. All TP output driver pins are driver low as a result of any of the following: there is an AUI IDL pulse of at least 200ns duration; the output driver is jabbered; the link-integrity option is enabled and there is a link failure; or an IDL pulse is not detected at the end of a packet and the input dose not exceed the detection threshold of 500ns 100ns. When the driver detects that it has finished sending an IDL pulse onto the TP, a timer of not more than 500ns is started. While this timer is active, activity on the DO + / DO - inputs is ignored. Receive Functions The TP receiver is connected to a band-limiting filter, whose input is transformer-coupled to the twisted-pair TPI + / TPI pins. The receiver is able to resolve differential signals as small as 350mV peak. Common-mode input voltage is provided with internal common-mode, with the commonmode set to nominal 2.5V. The receiver squelch circuit prevents noise on the twisted-pair cable from falsely triggering the receiver in the absence of true data. The receiver will not be activated for signals at the buffer input having a peak amplitude below 300mV, a continuous frequency below 2 MHz, or a single cycle duration within the pass band of the receive filter. This driver differentially drives a current onto the load connected between the DI + and DI - pins. The current through the load results in an 0.6V and 1.2V, measured output voltage between differentially between the two pins. As in figure 4, it shows the typical loading for DI + / DI - driver. When the driver detects that it has finished sending an IDL pulse onto the AUI, a timer of not more than 500ns is started. While this timer is active, activity on the TPI + / TPI - inputs is ignored, A collision state exists whenever there are valid inputs to the DM9095 from the network and from the DTE simultaneously and the device is not in a link-integrity failure state. The DM9095 reports collisions to the AUI by sending a 10 MHz signal over the CI + / CI - pair. The collision report signal is output no more than 9 BT after the chip detects a collision. If TPI + / TPI - become active while there is activity on the DO + / DO - pair, the loopback data on TPI + / TPI - switches from transmit data to receive data within 13 BT 3 BT. If a collision condition exits with TPI + / TPI - having gone idle while DO + / DO - are still active, SQE continues for 7 BT2 BT. If a collision condition exits with DO + / DO - having gone idle while TPI + / TPI- are still active, SQE may continue for up to 9 BT. Jabber Functions Jabber is a self-interrupt function that keeps a damaged node from continously transmitting onto the network. The chip contains a nominal window of 50ms, during which time a normal data link frame can be transmitted. If a frame length exceeds this duration, the jabber function inhibits transmission and sends a collision signal on the CI + / CI - pair. When activity on the DO + / DO - pair has ceased, the chip continues to present the CSO signal to the CI + / CI - pair for 0.5s 50%. The transmission of link-integrity pulses from the TP drivers is not inhibited when the DM9095 is jabbed and the link integrity function is enabled. SQE Test Functions When the DO + / DO - pair has gone idle after a successful transmission and the heartbeat function is enabled, the chip presents the CSO signal to the CI + / CI - pair. After a successful transmission onto the network media, the chip presents the CSO signal within 11 BT5 BT of the end of activity on the DO + / DO - pair. The CSO signal is presented for 10 BT5 BT, after which the chip presents an IDL on the CI + / CI - pair and returns to the idle state. and the AUI driver discharges the current stored on the inductive load. 9 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Link Integrity Functions In the absence of receive traffic, the twisted-pair receiver on the chip can detect periodic link-integrity pulse is a 100ns high signal with pre-distortion followed by a return to idle. The chip provides a link-integrity reception window, during which a link pulse is expected in the absence of receive traffic. The link-integrity window nominally opens 6.5ms after the receipt of a link-integrity pulse or the end of a data frame. The window closes nominally 104ms after the receipt of a link-integrity pulse or the end of a data frame. If a link pulse is received before the link-integrity reception window opens, it is ignored. If no link-integrity pulse is received while the link-integrity reception window is open, there is a link failure. The RLED indicator is turned off, and the chip's transmit, loopback, and receive functions are disabled. If a link-integrity pulse or receive traffic is received while the link-integrity reception window is open, the timers involved are reset. Once the DM9095 has detected a link failure, one of two events must occur before the DM9095 re-enables transmission and reception of data. The first possible event is the reception of two consecutive link-integrity pulses that both fall within the link-integrity reception window and are separated by at least a nominal 6.5ms. The second possible event is the reception of a data packet from the twisted pair. With either of these events, the TPMAU enters a wait state and continues to disable loopback, transmit, and receive functions. This continues until the DM9095 determines that there is no traffic going in either the transmit or receive direction and then enters the idle state. When the link integrity function is enabled, the DM9095 also transmits link-integrity pulses onto the transmit twisted-pair link. In the absence of transmit traffic, a link-integrity pulse is transmitted at a nominal rate of once per 16ms. Link-integrity pulses continue to be transmitted when the part is jabbed by the watchdog timer or there is link-integrity failure. Auto-Polarity Detection and Correction Functions The DM9095 can determine if the receive twisted pair has been wired with a polarity reversal. If so, the DM9095 automatically corrects for this error condition, when the correction function is enabled. Also, the AP pin itself can be connected to an LED to display the status of the polarity of the receive twisted pair. When enabled, the DM9095 powers up the function in the normal state and determines if the receive wires are reversed. The DM9095 examines either the IDL pulse at the end of each receive packet or the link pulse when the link integrity function is enabled and uses this information to sense the polarity. If the DM9095 determines that the incoming IDL pulse is of the proper polarity, it remains in normal state. If the DM9095 detects two consecutive reverse IDL pulses or two reverse link pulses, it enters reverse state. If the DM9095 determines that the polarity of the link is reversed, it internally corrects for the polarity, ensuring that all follow-on packets are sent up the AUI with the correct polarity. Automatic AUI and RJ45 Connector Selection Functions The chip provides the designer of a 10BASE-T Ethernet interface card with the ability to design a card without having to provide a switch or jumper array to change between AUI and twisted-pair connections. The DM9095 provides automatic changeover whenever the external cable connection is changed. When the link integrity function is enabled and twisted-pair cable is disconnected, all incoming receive signals disappear and the device places the CI + / CI - and DI + / DI - outputs in their high-impedance state. In addition, DO + / DO - inputs are high-impedance inputs. Power-Down Mode Function The power-down function is ideal for embedded, laptop computer applications. In power-down mode, the chip pulls within 10uA. When the device is reactivated from power-down mode, normal transceiver operation will resume after the 3.2ms calibration sequence is completed. Power-On Reset Function The DM9095 uses a power-on reset sequence to place itself into a known digital state, to allow the analog sections to stabilize, and to calibrate the internal delay line. Depending on the power-down condition, initialization requires the following lengths of time: Power-on reset: 3.2 ms Power-down mode: 3.2 ms Final Version: DM9095-DS-F02 August 21, 2000 z z 10 DM9095 Twisted-Pair Medium Attachment Unit Crystal Oscillator An external TTL-Level clock can be applied to the OSC1 pin which is crystal oscillator input. A resistor should be added in series with the clock source to limit the amplitude of the voltage swing seen by the pin. A 500 resistor works well in most cases. LED Status Functions The LED drivers require an external resistor in series with the LED, which is in turn connected to VDD. The driver pulls the pin low to light the LED and can sink up to 15mA of drive current from the resistor with an output impedance of less than 50 . The DM9095 provides three types LED drivers, as follows. Output LED Drivers: The LED outputs XLED, RLED, JLED, and CLED are output LED drivers. These signals are used for status information only. XLED drives high when the DM9095 is transmitting a packet. XLED is not asserted if the DM9095 has detected a jabber function or is in a link-fail state. RLED drives high when the DM9095 is receiving a packet. RLED is not asserted when the DM9095 is in a link-fail state. JLED drives low when the DM9095 has detected a jabber condition. CLED drives low when the DM9095 has detected a collision condition. Sampled LED Driver: The AP pin is used to set the configuration of the DM9095 and drive the LED status indicators. Every 26ms, the pin is configured as an input pin for 6.5* s. During this time, it is sampled by the DM9095. Outside the sampling window, the driver is placed in an output state and used to drive the LED indicators. AP is driven low to indicate that a reversed twisted pair has been detected on the receive circuit and corrected. If AP is tied low, DM9095 disables the auto-polarity function; when AP is pulled high externally, the function is enabled. Input / Output LED Driver: LI-pin is an input/output pin, depending on the mode selection. When configured as an input pin, LI-controls the link integrity test option. If LI- is connected to GND, the link Mode 0 1 2 3 4 5 6 7 11 integrity function is enabled. If LI- is connected to VDD or left floating (internal pull-high), the link integrity function is disabled. When configured as an output pin, the pin drives low for link-fail state and drives high for link-pass state. The output pin can drive an LED status indicator. Power There are six power connections to the DM9095, including three VDD and three GND connections. Pins 1 and 28 are used for analog supplies, including squelch circuits, receiver, and the internal delay circuit. Pins 10 and 14 are used for digital circuits, the I/O buffer, the control logic for analog circuits, and the crystal oscillator circuit. Pins 18 and 23 are used for the Twisted Pair driver output buffer. Operating Modes The mode selection pins are used to select one of eight operating modes. These modes are summarized in the table below. The modes referred to in the table are the following: Heartbeat: A Yest means that the heartbeat function is enabled; A No means the heartbeat function is disabled. Line Length: "Extended" indicates that TP receive squelch thresholds have been lowered to 300mV for use with longer line lengths; Normal indicates that the standard 10BASE-T TP receive squelch threshold of 450mV will be used. LI-: The LI- pin can be configured to be an input pin, whereby the link-integrity function can be enabled or disabled. The LI- pin can also be configured as an output pin to indicate the status of the link, where the link-integrity is enabled. MD0 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD2 0 1 0 1 0 1 0 1 Heartbeat No No No Yes Yes Yes Mode Description Line Length LIApplication Extended I Long wire TP Normal I Normal wire TP Normal O LI pin LED output Poer-down mode Extended I Long wire TP Normal I Normal wire TP Normal O LI pin LED output Power-down mode Final Version: DM9095-DS-F02 August 21, 2000 z z z DM9095 Twisted-Pair Medium Attachment Unit AC Electrical Characteristics Symbol Transmit Timing tTD tTLB tTPDY tTOFF tTIDL Transmit delay from DO to TPO to DI Parameter Min. Typ. Max. Unit Loopback delay from DO DTPO - to TPO + and DTPO + to TPO - delay DO + high to idle time TPO + high to idle time Receive Timing tRD tROFF tRIDL Receive delay from TPI TPI + high to idle time DI + high to idle time to DI Collision Timing tCB tCE tCLB tCIDL tCPH tCP Jabber Timing tJMT tJCB tJU Maximum transmit time for TPO Time from Jabber to enable CI Unjab time Collision turn-on time Collision turn-off time Loopback delay when switching from DO CI + high to idle time Collision high-pulse width Collision period to TPI 0 0 900 900 1600 350 50 100 60 120 ns ns ns ns ns ns output Final Version: DM9095-DS-F02 August 21, 2000 0 0 47 200 250 200 500 53 ns ns ns ns 350 ns 0 200 250 500 ns ns 350 ns 1000 250 40 80 45 0 250 50 55 900 ms ns ms 450 750 12 DM9095 Twisted-Pair Medium Attachment Unit AC Electrical Characteristics (continued) Symbol Link Integrity Timing tLP tLPWT tLPWD Transmitted link integrity pulse period Link integrity pulse width for TPO + Link integrity pulse width for DTPO 8 80 40 16 100 50 24 120 60 ms ns ns Parameter Min. Typ. Max. Unit Heartbeat Timing tHD tHCS LED Timing tXSET tXOFF tXON tROFF tRON tRLFSET tRLFOFF tRLFON tCSET tCON tJSET tJON XLED turn-off time XLED off time XLED minimum on time RLED off time RLED minimum on time RLED turn-off time for link fail RLED off time for link fail RLED on time for link success CLED turn-on time CLED nominal on time JLED turn-on time JLED on time 250 10 0.5 1.5 10 20 10 750 s *s ms *s ms 90 4 90 4 50 10 110 8 110 8 150 *s ms ms ms ms ms Heartbeat turn-on time Heartbeat active time for CI 600 1600 1500 ns ns output 13 500 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Timing Waveforms Final Version: DM9095-DS-F02 August 21, 2000 14 DM9095 Twisted-Pair Medium Attachment Unit 15 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Timing Waveforms (continued) Final Version: DM9095-DS-F02 August 21, 2000 16 DM9095 Twisted-Pair Medium Attachment Unit Timing Waveforms (continued) Figure 10. Transmitted link integrity pulse timing 17 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Timing Waveforms (continued) Final Version: DM9095-DS-F02 August 21, 2000 18 DM9095 Twisted-Pair Medium Attachment Unit Timing Waveforms (continued) 19 Final Version: DM9095-DS-F02 August 21, 2000 DM9095 Twisted-Pair Medium Attachment Unit Package Information PLCC 28L Outline Dimensions unit: inch/mm Note: 1. Dimension D & E do not include resin fin. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. Final Version: DM9095-DS-F02 August 21, 2000 20 DM9095 Twisted-Pair Medium Attachment Unit Ordering Information Part Number DM9095L Pin Count 28 Package PLCC DAVICOM's terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms. Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM deserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that re the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5798858 WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Taipei Sales & Marketing Office: 8F, No. 3, Lane 235, Bao-chiao Rd., Hsin-tien, Taipei, Taiwan, R.O.C. TEL: 886-2-29153030 FAX: 886-2-29157575 Email: sales@davicom.com.tw Davicom USA Sunnyvale, California 1135 Kern Ave., Sunnyvale, CA94085, U.S.A. TEL: 1-408-7368600 FAX: 1-408-7368688 Email: sales@davicom8.com 21 Final Version: DM9095-DS-F02 August 21, 2000 |
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