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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4068B gates 8-input NAND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 8-input NAND gate DESCRIPTION The HEF4068B provides the 8-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4068B gates Fig.2 Pinning diagram. Fig.1 Functional diagram. HEF4068BP(N): 14-lead DIL; plastic (SOT27-1) HEF4068BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4068BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram. FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification 8-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In O HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 95 40 30 80 35 30 60 30 20 60 30 20 195 85 65 165 70 60 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4068B gates TYPICAL EXTRAPOLATION FORMULA 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 53 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 700 fi + (foCL) x VDD2 2900 fi + (foCL) x 7200 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 |
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