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HSP45240/883
February 1998
Address Sequencer
Description
The Intersil HSP45240/883 is a high speed Address Sequencer which provides specialized addressing for functions like FFTs, 1-D and 2-D filtering, matrix operations, and image manipulation. The sequencer supports block oriented addressing of large data sets up to 24 bits at clock speeds up to 40MHz. Specialized addressing requirements are met by using the onboard 24 x 24 crosspoint switch. This feature allows the mapping of the 24 address bits at the output of the address generator to the 24 address outputs of the chip. As a result, bit reverse addressing, such as that used in FFTs, is made possible. A single chip solution to read/write addressing is also made possible by configuring the HSP45240 as two 12-bit sequencers. To compensate for system pipeline delay, a programmable delay is provided on 12 of the address outputs. The HSP45240 is manufactured using an advanced CMOS process, and is a low power fully static design. The configuration of the device is controlled through a standard microprocessor interface and all inputs/outputs, with the exception of clock, are TTL compatible.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Block Oriented 24-Bit Sequencer * Configurable as Two Independent 12-Bit Sequencers * 24 x 24 Crosspoint Switch * Programmable Delay on 12 Outputs 9* Multi-Chip Synchronization Signals * Standard P Interface * 100pF Drive on Outputs * DC to 40MHz Clock Rate
Applications
* 1-D, 2-D Filtering * Pan/Zoom Addressing * FFT Processing * Matrix Math Operations
Ordering Information
PART NUMBER HSP45240GM-25/883 HSP45240GM-33/883 HSP45240GM-40/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 68 Ld PGA 68 Ld PGA 68 Ld PGA PKG. NO.
Block Diagram
STARTOUT ADDVAL DONE BLOCKDONE 12 REG STARTIN START CIRCUITRY SEQUENCE GENERATOR 24 CROSS-POINT SWITCH OUT12-23 OEH 12 DELAY 1-8 OUT0-11 OEL PROCESSOR INTERFACE BUSY
DLYBLK
D0-6, CS, A0, WR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2816.3
9-16
HSP45240/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output Voltage Applied. . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 37.1 10.1 Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.35W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8,388
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 2.6 -10 -10 3.0 MAX 0.8 0.4 +10 +10 0.8 500 UNITS V V V V A A V V A
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HlGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Clock lnput High Clock Input Low Standby Power Supply Current Operating Power Supply Current Functional Test
SYMBOL VlH VIL VOH VOL II
IO
TEST CONDITIONS VDD = 5.5V VDD = 4.5V IOH = -400A VDD = 4.5V (Note 2)
IOL = +2.0mA VCC = 4.5V (Note 2)
VIN = VCC or GND VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VCC = 5.5V VCC = 4.5V VIN = VCC or GND VCC = 5.5V, Outputs Open f = 33MHz VCC = 5.5V (Note 3) (Note 4)
VIHC VILC
ICCSB
ICCOP
1, 2, 3 7, 8
-55 TA 125 -55 TA 125
-
99 -
mA
FT
NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 3mA/MHz. 4. Tested as follows: t = 1MHz, VIH = 2.6, VIL = 0.4, VOH 1.5V, VOL < 1.5V, VIHC = 3.4V, and VILC = 0.4V.
9-17
HSP45240/883
TABLE 2. AC ELECTRICAL SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUP 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9,10,11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -25 (25MHz) MIN 39 15 15 17 0 5 0 18 18 39 15 0 MAX 18 18 -33 (33MHz) MIN 30 12 12 16 0 5 0 14 14 30 12 0 MAX 16 16 -40 (40MHz) MIN 25 10 10 14 0 5 0 12 12 25 10 0 MAX 14 14 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Clock Period Clock Pulse Width High Clock Pulse Width Low Setup Time D0-6 to WR High Hold Time D0-6 from WR Low Setup Time A, CS to WR Low Hold Time A, CS from WR High Pulse Width for WR Low Pulse Width for WR High WR Cycle Time Set-up Time STARTIN, DLYBLK, to Clock High Hold Time STARTlN, DLYBLK, to Clock High Clock to Output Prop. Delay on OUT0-23 Clock to Prop. Delay, on STARTOUT, BLKDONE, DONE, ADVAL, and BUSY Output Enable Time (Note 6) RST Low Time NOTES:
SYMBOL tCP tCH tCL tDS tDH tAS tAH tWRL tWRH tWP tIS tlH tPDO tPDS
tEN tRST
9, 10, 11 9, 10, 11
-55 TA 125 -55 TA 125
-
22
-
20
-
15
ns ns
2 Clock Cycles
5. AC Testing: VCC = 4.5V and 5.5V, inputs are driven at 3.0V for Logic "1" and 0.0V for a Logic "0". Input and output timing measurements are made at 1.5V for both a logic "1" and "`0". CLK is driven at 4.0V and 0V and measured at 2.0V. 6. Transition is measured at 200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF. TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS -25 (25MHz) NOTES 7 TEMPERATURE TA = 25 MIN MAX 10 -33 (33MHz) MIN MAX 10 -40 (40MHz) MIN MAX 10 UNITS pF
PARAMETERS Input Capacitance
SYMBOL CIN
TEST CONDITIONS VCC = Open, f = 1MHz, All measurements are referenced to device GND. VCC = Open, f = 1MHz, All measurements are referenced to device GND.
Output Capacitance
COUT
7
TA = 25
-
10
-
10
-
10
pF
Output Disable
tOEZ
7, 8
-55 TA 125
-
22
-
20
-
15
ns
9-18
HSP45240/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) -25 (25MHz) NOTES 7, 8 7, 8 TEMPERATURE -55 TA 125 -55 TA 125 MIN MAX 5 5 -33 (33MHz) MIN MAX 5 5 -40 (40MHz) MIN MAX 3 3 UNITS ns ns
PARAMETERS Output Rise Time Output Fall Time NOTES:
SYMBOL tOR tOF
TEST CONDITIONS
7. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 8. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
9-19
HSP45240/883 Burn-In Circuit
L OEH DLY BLK OEL START VCC OUT BLOCK GND DONE OUT1 OUT2 NC
K
NC
NC
START ADD IN VAL BUSY
DONE OUTO
VCC
NC
OUT3
J
RST
VCC GND
GND
OUT4
H
CLK
OUT5
VCC
G
CS
A0
OUT6 OUT7
F E
WR D6
GND D5
GND OUT9
OUT8 VCC
D
D4
D3
OUT10 OUT11
C
D2
D1
GND OUT12
B
D0
NC
OUT22 OUT21 GND OUT18 OUT17 GND OUT14
NC
NC
A 1
GND 2
OUT23 3
VCC 4
OUT20 OUT19 5 6
VCC 7
OUT16 OUT15 OUT13 8 9 10 11
PGA PIN A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B3 B4 B5 B6 B7 B8 NOTES:
PIN NAME GND OUT23 VCC OUT20 OUT19 VCC OUT16 OUT15 OUT13 D0 OUT22 OUT21 GND OUT18 OUT17 GND
BURNIN SIGNAL GND VCC/2 VCC VCC/2 VCC/2 VCC VCC/2 VCC/2 VCC/2 F8 VCC/2 VCC/2 GND VCC/2 VCC/2 GND
PGA PIN B9 C1 C2 C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10
PIN NAME OUT14 D2 D1 GND OUT12 D4 D3 OUT10 OUT11 D6 D5 OUT9 VCC WRB GND GND
BURNIN SIGNAL VCC/2 F10 F9 GND VCC/2 F12 F11 VCC/2 VCC/2 F7 F13 VCC/2 VCC F4 GND GND
PGA PIN F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J10 J1 1 K3 K4 K5
PIN NAME OUT8 CSB A0 OUT6 OUT7 CLK GND OUTS VCC RSTB VCC GND OUT4 OELB START1NB ADVALB
BURNIN SIGNAL VCC/2 F5 F6 VCC/2 VCC/2 F0 GND VCC/2 VCC F14 VCC GND VCC/2 F12 F6 VCC/2
PGA PIN K6 K7 K8 K9 K11 L2 L3 L4 LS L6 L7 L8 L9
PIN NAME BUSYB DONEB OUT0 VCC OUT3 OEHB DLYBLK STARTOUTB VCC BLOCKDONEB GND OUT1 OUT2
BURNIN SIGNAL VCC/2 VCC/2 VCC/2 VCC VCC/2 F13 F11 VCC/2 VCC VCC/2 GND VCC/2 VCC/2
9. VCC /2 (2.7V 10%) used for outputs only. 10. 47 (20%) resistor connected to all pins except VCC and GND. 11. VCC = 5.5 0.5V. 12. 0.1F (min) capacitor between VCC and GND per position. 13. F0 = 100kHz 10%, F1 = F0/2, F2 = F1/2....., F11 = F10/2, 40% -60% Duty Cycle. 14. Input voltage limits: VIL = 0.8V max., VIH = 4.5V 10%.
9-20
HSP45240/883 Die Characteristics
DIE DIMENSIONS: 186 mils x 222 mils x 19 1mils METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kA WORST CASE CURRENT DENSITY: 1.8 x 105A/cm2 GLASSIVATION: Type: Nitrox Thickness: 10kA
Metallization Mask Layout
HSP45240/883
OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 GND OUT15 OUT14 OUT13 GND GND VCC VCC
D0 D1 D2 D3 D4 D5
OUT12 GND OUT11 OUT10 VCC OUT9 OUT8
D6 GND WR A0 CS GND CLK VCC RST OUT4 GND OUT3 GND OUT7 OUT6 VCC OUT5
OEL
ADDVAL
BUSY
OUT0
BLOCKDONE
STARTIN
STARTOUT
DLYBLK
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
9-21
DONE
OUT1 VCC
OUT2
OEH
VCC
GND

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