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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MCM67M618B
64K x 18 Bit BurstRAM Synchronous Fast Static RAM
With Burst Counter and Self-Timed Write
The MCM67M618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high-performance, secondary cache for the MC68040 and PowerPCTM microprocessors. It is organized as 65,536 words of 18 bits, fabricated using Motorola's high-performance silicon-gate BiCMOS technology. The device integrates input registers, a 2-bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 - A15), data inputs (DQ0 - DQ17), and all control sigDQ9 nals, except output enable (G), are clock (K) controlled through posiDQ10 VCC tive-edge-triggered noninverting registers. VSS Bursts can be initiated with either transfer start processor (TSP) or DQ11 transfer start cache controller (TSC) input pins. Subsequent burst DQ12 addresses are generated internally by the MCM67M618B (burst DQ13 sequence imitates that of the MC68040) and controlled by the burst DQ14 address advance (BAA) input pin. The following pages provide more VSS detailed information on burst controls. VCC Write cycles are internally self-timed and are initiated by the rising DQ15 edge of the clock (K) input. This feature eliminates complex off-chip DQ16 write pulse generation and provides increased flexibility for incoming DQ17 signals. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 - DQ8 (the lower bits), while UW controls DQ9 - DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. * * * * * * * * * * Single 5 V 5% Power Supply Fast Access Times: 9/10/12 ns Max Byte Writeable via Dual Write Strobes Internal Input Registers (Address, Data, Control) Internally Self-Timed Write Cycle TSP, TSC, and BAA Burst Control Pins Asynchronous Output Enable Controlled Three-State Outputs Common Data Inputs and Data Outputs High Board Density 52-PLCC Package 3.3 V I/O Compatible
FN PACKAGE PLASTIC CASE 778-02
PIN ASSIGNMENT
A6 A7 E UW LW TSC TSP BAA K G A8 A9 A10 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A5 A4 A3 A2 A1 A0 VSS VCC A15 A14 A13 A12 A11 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0
PIN NAMES
A0 - A15 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock BAA . . . . . . . . . . . . Burst Address Advance LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Upper Byte Write Enable TSP, TSC . . . . . . . . . . . . . . . . Transfer Start E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 - DQ17 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground All power supply and ground pins must be connected for proper operation of the device.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 7/15/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM67M618B 1
BLOCK DIAGRAM (See Note)
BURST LOGIC BAA K Q1 BINARY COUNTER LOAD D1 D0 Q0 A0 INTERNAL ADDRESS 16 64K x 18 MEMORY ARRAY
A1
TSC TSP
A1 EXTERNAL ADDRESS A15 - A0 ADDRESS REGISTERS
A0 A15 - A2
16
18
9
9
UW LW
WRITE REGISTER
DATA-IN REGISTERS
E
ENABLE REGISTER 9 9
OUTPUT BUFFER
G DQ0 - DQ8 DQ9 - DQ17 9 9
NOTE: All registers are positive-edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed using the new external address. Alternatively, a TSP-initiated two cycle WRITE can be performed by asserting TSP and a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE GRAPH (See Note)
0,0 A1, A0 = 1,1
0,1 1,0
NOTE: The external two values for A1 and A0 provide the starting point for the burst sequence graph. The burst logic advances A1 and A0 as shown above.
MCM67M618B 2
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E H H L L L X X X X TSP L X L H H H H H H TSC X L X L L H H H H BAA X X X X X L L H H LW or UW X X X L H L H L H K L-H L-H L-H L-H L-H L-H L-H L-H L-H Address N/A N/A External Address External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected G L H X X I/O Status Data Out High-Z High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Ambient Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 1.6 - 10 to + 85 0 to +70 - 55 to + 125 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MCM67M618B 3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20.0 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20.0 ns) for I 20.0 mA.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) MCM67M618B-9 MCM67M618B-10 MCM67M618B-12 Symbol Ilkg(I) Ilkg(O) ICCA Min -- -- -- Max 1.0 1.0 TBD Unit A A mA
CMOS Standby Supply Current (Device Deselected, Freq = 0, VCC = Max, All Inputs Static at CMOS Levels Vin VSS + 0.2 V or VCC - 0.2 V) Clock Running (Device Deselected, Freq = Max, VCC = Max, All Inputs Toggling at CMOS Levels Vin VSS + 0.2 V or VCC - 0.2 V) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA)
ISB2 ISB4 VOL VOH
-- -- -- 2.4
TBD TBD 0.4 3.3
mA mA V V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible 68040 and PowerPC bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ 4 6 Max 5 8 Unit pF pF
MCM67M618B 4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 3, and 4)
MCM67M618B-9 Parameter P Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol S bl tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tTSVKH tDVKH tWVKH tBAVKH tEVKH tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX Min 15 -- -- 6 3 0 -- 3 5 5 2.5 Max -- 9 5 -- -- -- 6 6 -- -- -- MCM67M618B-10 Min 16.6 -- -- 6 3 0 -- 3 5 5 2.5 Max -- 10 5 -- -- -- 7 7 -- -- -- MCM67M618B-12 Min 20 -- -- 6 3 0 -- 3 6 6 2.5 Max -- 12 6 -- -- -- 7 7 -- -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 7 6 6 5 Notes N
Hold Times:
0.5
--
0.5
--
0.5
--
ns
7
NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high for the setup and hold times. 3. All read and write cycle timings are referenced from K or G. 4. G is a don't care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 6. Transition is measured 500 mV from steady-state voltage. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever TSP or TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled.
OUTPUT Z0 = 50 RL = 50 VL = 1.5 V
Figure 1.Test Load
MOTOROLA FAST SRAM
MCM67M618B 5
READ CYCLES
t KHKH
t KHTSX
MCM67M618B 6
t KHKL t KLKH t KHTSX t TSVKH t KHAX A1 t KHWX t WVKH A2 t KHEX t BAVKH t KHBAX t KHQV t GLQV (BAA SUSPENDS BURST) t GHQZ Q(A1) SINGLE READ t KHQV t KHQX2 Q(A2) Q(A2 + 1) Q(A2 + 2) BURST READ (BURST WRAPS AROUND TO ITS INITIAL STATE) Q(A2 + 3) Q(A2) Q(A2 + 1) t KHQZ
K
t TSVKH
TSP
TSC
t AVKH
ADDRESS
LW, UW
t EVKH
E
BAA
G
t GLQX
DATA OUT
Q(A2 + 2)
MOTOROLA FAST SRAM
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address.
WRITE CYCLES
t KHKH
K t KHKL t KHTSX t KLKH
t TSVKH
MOTOROLA FAST SRAM
t TSVKH t KHTSX TSC STARTS NEW BURST t KHAX A1 W IS IGNORED FOR FIRST CYCLE WHEN TSP INITIATES BURST A2 A3 t WVKH t KHWX t KHEX t BAVKH t KHBAX BAA SUSPENDS BURST t DVKH D(A1) t GHQZ D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) t KHDX SINGLE WRITE BURST WRITE (WITH A SUSPENDED CYCLE) NEW BURST WRITE
TSP
TSC
t AVKH
A
LW, UW
t EVKH
E
BAA
G
D
D(A3 + 2)
Q
Q(An - 1)
Q(An)
MCM67M618B 7
BURST READ
COMBINATION READ/WRITE CYCLE (E Low, TSC High)
tKHKH K tKHKL tKLKH
tTSVKH TSP
tKHTSX
tAVKH ADDRESS A1
tKHAX A2 A3
tWVKH LW, UW
tKHWX
tBAVKH BAA
tKHBAX
G tDVKH D(A2) tKHQX1 tGHQZ tGLQX tKHQX2 tKHDX tGLQV
tKHQV DATA IN
DATA OUT
Q(A1)
Q(A3)
Q(A3 + 1)
Q(A3 + 2)
READ
WRITE
BURST READ
MCM67M618B 8
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
DATA BUS DATA ADDRESS BUS ADDRESS CLOCK MPC604 (PowerPCTM) ADDR SYSCLK K CACHE CONTROL LOGIC K G ADDR DATA
MCM67M618BFN9 TSC W BAA TSP
TS CONTROL
512K Byte Burstable, Secondary Cache Using Four MCM67M618BFN9s with a 66 MHz MPC604 PowerPCTM Figure 2.
MOTOROLA FAST SRAM
MCM67M618B 9
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number Full Part Numbers -- MCM67M618BFN9
67M618B XX
XX
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns) Package (FN = PLCC)
MCM67M618BFN10
MCM67M618BFN12
MCM67M618B 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE 52-LEAD PLCC CASE 778-02 B -N- Y BRK D Z -L- -M- 0.007 (0.18) U
M
T L-M
M
S
N
S S
0.007 (0.18)
T L-M
N
S
W D
52 1
X V VIEW D-D 0.007 (0.18) 0.007 (0.18)
M
G1 0.010 (0.25)
S
T L-M
S
N
S
A Z R
T L-M T L-M
S
N N
S
M
S
S
E C G G1 0.010 (0.25)
S
J VIEW S T L-M N
0.004 (0.100) -T- SEATING
PLANE
S
S
H K1
0.007 (0.18)
M
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.710 0.730 0.040 --- MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 18.04 18.54 1.02 ---
K VIEW S
F
0.007 (0.18)
M
T L-M
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
MOTOROLA FAST SRAM
MCM67M618B 11
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 303-675-2140 or 1-800-441-2447 MfaxTM : RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 - US & Canada ONLY 1-800-774-1848 INTERNET : http: / / motorola.com/sps JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office; 4-32-1, Nishi-Gotanda; Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MCM67M618B 12
MCM67M618B/D MOTOROLA FAST SRAM

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