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| Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 DESCRIPTION The SA702 triple modulus (Divide By 64/65/72) low power ECL prescaler is used in synthesizer systems to achieve low phase lock time, broad operating range, high reference frequency and small frequency step sizes. The minimum supply voltage is 2.7V and is compatible with the CMOS UMA1005 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the QUBiC process. The circuit will be available in an 8-pin SO package with 150 mil package width and in 8-pin dual in-line plastic package. FEATURES * Low voltage operation * Low current consumption * Operation up to 1.1GHz * ESD hardened APPLICATIONS PIN CONFIGURATION N, D Package 1 2 3 4 8 7 6 5 IN GND MC1 OUT IN VC C MC2 OUT * Cellular phones * Cordless phones * RF LANs * Test and measurement * Military radio * VHF/UHF mobile radio * VHF/UHF hand-held radio ORDERING INFORMATION DESCRIPTION 8-Pin Plastic Dual In-Line Package (DIP) 8-Pin Plastic Small Outline (SO) package (Surface-mount) TEMPERATURE RANGE -40 to +85C -40 to +85C ORDER CODE SA702N SA702D DWG # 0404B 0174C ABSOLUTE MAXIMUM RATINGS SYMBOL VCC VIN IO TSTG TA JA Supply voltage Voltage applied to any other pin Output current Storage temperature range Operating ambient temperature range Thermal impedance D package N package PARAMETER RATING -0.3 to +7.0 -0.3 to (VCC + 0.3) 10 -65 to +125 -55 to +125 158 108 UNITS V V mA C C C/W June 17, 1993 2 853-1709 10044 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 BLOCK DIAGRAM OUT OUT Q D Q D Q D Q D Q D Q Q D Q Q D Q Q D MC1 MODULUS CONTROL LOGIC MC2 IN IN June 17, 1993 3 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 DC ELECTRICAL CHARACTERISTICS The following DC specifications are valid for TA = 25C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1. SYMBOL VCC ICC VOH VOL VIH VIL VIH VIL IIH IIL IIH IIL PARAMETER Power supply voltage range Supply current Output high level Output low level MC1 input high threshold MC1 input low threshold MC2 input high threshold MC2 input low threshold MC1 input high current MC1 input low current MC2 input high current MC2 input low current VMC1 = VCC = 6V VMC1 = 0V, VCC = 6V VMC2 = VCC = 6V VMC2 = 0V, VCC = 6V -100 -100 2.0 -0.3 2.0 -0.3 0.1 -30 0.1 -30 50 TEST CONDITIONS MIN fIN = 1GHz, input level = 0dBm No load IOUT = 1.2mA VCC-1.4 VCC-2.6 VCC 0.8 VCC 0.8 50 2.7 4.5 LIMITS TYP MAX 6.0 V mA V V V V V V A A A A UNITS AC ELECTRICAL CHARACTERISTICS These AC specifications are valid for fIN = 1GHz, input level = 0dBm, VCC = 3.0V and TA = 25C; unless otherwise stated. Test circuit Fig. 1. SYMBOL VIN fIN RID VO tS tH tPD PARAMETER Input signal amplitude1 Input signal frequency Differential input resistance Output voltage Modulus set-up time1 Modulus hold time1 Propagation time 10 TEST CONDITIONS MIN 1000pF input coupling Direct coupled input2 1000pF input coupling DC measurement VCC = 5.0V VCC = 3.0V 5 1.6 1.2 5 0 0.05 0 LIMITS TYP MAX 2.0 1.1 1.1 VP-P GHz GHz k VP-P VP-P ns ns ns UNITS NOTES: 1. Maximum limit is not tested, however, it is guaranteed by design and characterization. 2. For fIN < 50MHz, minimum input slew rate of 32V/s is required. DESCRIPTION OF OPERATION The SA702 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for MC1 (Modulus Control) to be set high and MC2 input to be set low in which case the circuit comprises a divide by 64. For divide by 65 the MC1 singal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. For divide by 72, MC2 is set high configuring the prescaler to divide by 4 and the counter to divide by 18. A truth table for the modulus values is given below: Table 1. Modulus 64 65 72 72 MC1 1 0 0 1 MC2 0 0 1 1 reduced input current. CMOS and low voltage interface capability are allowed. The prescaler input is differential and ECL compatible. The output is differential ECL compatible. For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output. The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tPD relative to the input. The rising edge of the output occurs at the count 32 with delay tPD. The MC1 and MC2 inputs are TTL compatible threshold inputs operating at a June 17, 1993 4 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 AC TIMING CHARACTERISTICS COUNT IN 64 65 1 32 63 64 1 MC (2:1) (00) (XX) (01) OUT OUT tP tS SWITCH FROM /65 TO /64 tH D COUNT IN 64 65 1 32 62 63 64 71 72 1 (00) MC (XX) (10) OUT tP tS SWITCH FROM /65 TO /72 tH D June 17, 1993 5 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 IN IN 50 50 R1 50 C1 1000pF C2 1000pF R2 50 IN IN VCC C3 0.1F MC2 VCC GND MC2 MC1 MC1 OUT OUT R4 2.2k C5 5pF OUT OUT R3 2.2k C4 5pF Figure 1. SA702 Test Circuit FREQUENCY (MHz) 0 200 -5 MINIMUM INPUT POWER (dBm) 400 600 800 1000 1200 -10 -40C VCC = 3.0V -20 25C 85C -15 -25 -30 -35 -40 Figure 2. Minimum Input Power vs Frequency and Temperature June 17, 1993 6 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 FREQUENCY (MHz) 0 200 -5 MINIMUM INPUT POWER (dBm) -10 -15 TA = 25C -20 -25 -30 -35 -40 2.7V 3.0V 6.0V 400 600 800 1000 1200 Figure 3. Minimum Input Power vs Frequency and VCC 6 85C 5.5 25C 5 ICC (mA) 4.5 -40C 4 3.5 3 2.7 3 VCC (V) 6 7 Figure 4. Supply Current vs Supply Voltage and Temperature With No Load June 17, 1993 7 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 j1 j0.5 j2 VCC = 3V j0.2 j5 TA = 25C 0 0.2 0.5 1 2 5 50 INPUT R3 4 L4 6nH 300 -j0.2 600 -j5 C2 0.4pF R1 3000 C1 0.9pF EQUIVALENT INPUT IMPEDANCE 900 -j0.5 1200 -j2 -j1 Figure 5. Typical N Package Input Impedance j1 j0.5 j2 j0.2 j5 VCC = 3V TA = 25C L4 3nH 0 0.2 0.5 1 2 5 50 INPUT R3 2 C2 0.2pF 300 -j0.2 600 -j5 R1 3000 C1 0.9pF EQUIVALENT INPUT IMPEDANCE 900 -j2 -j0.5 1200 -j1 Figure 6. Typical D Package Input Impedance June 17, 1993 8 |
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