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| DECO SM5865CM NIPPON PRECISION CIRCUITS INC. D/A Converter for Digital Audio OVERVIEW The SM5865CM is a 24-bit input D/A converter LSI for high-quality digital audio equipment. It comprises newly developed DEM (dynamic element matching) circuits, 3rd-order noise shaper and 31-level quantizer to realize super low total harmonic distortion and wide dynamic range. Also, the device is widely reduced residual quantization noise up to high-frequency bandwidth in the audio band so the order of the required final-stage analog lowpass filter can be reduced, making it ideal for application with high-frequency sampling format. The output stage employs differential current outputs for highaccuracy analog signals, with appropriate lowpass filtering of the output signal. This device can be used in combination with an 8-times oversampling digital filter of SM5847AF and others like that for the compatibility with 192kHz sampling format. PINOUT (Top view) DVSS DI BCKI WCKI IWSL RSTN TSTN TO DVDD CKI CKDVN CVSS 1 24 AVSSA RA IOUTA VBA N.C. AVDDA AVDDB RB IOUTB VBB N.C. S M 5 8 6 5 CM 12 13 FEATURES I I AVSSB I I I I I ORDERING INFORMATION Device SM5865CM Package 24-pin SSOP 0.10 0.10 0.8 0.36 0.10 0.10 0.12 M 10.05 0.20 10.20 0.30 0.15 - 0.05 + 0.10 5.40 0.20 7.80 0.30 +0.20 1.90-0.10 1.80 Mono-channel D/A converter LSI High performance * 0.00030 % (-110.5dB) typ. THD + N * 117 dB typ. Dynamic range * 120 dB typ. S/N Input interface * 20 or 24-bit word length * MSB first, right-justified format * 8 or 4 times oversampling at fs = 16/32/44.1/48/ 88.2/96/176.4/192 kHz System clock frequency * 192/256/384/512/768/1024 fs Single 5 V operating supply voltage 24-pin SSOP package Molybdenum-gate CMOS process PACKAGE DIMENSIONS (Unit: mm) Weight: 0.23g 24-pin SSOP 0.50 0.20 0 10 NIPPON PRECISION CIRCUITS--1 SM5865CM BLOCK DIAGRAM TO 8 TSTN 7 RSTN 6 IWSL 5 WCKI 4 BCKI 3 DI 2 Input interface 9 DVDD CKI CKDVN CVSS 10 11 12 Divider Timing control Interpolation 1 DVSS Noise shaper Noise shaper AVSSB 13 24 31 Level DEM DAC 31 Level DEM DAC 31 Level DEM DAC 31 Level DEM DAC AVSSA 15 VBB 16 IOUTB 17 RB 18 AVDDB 19 AVDDA 21 VBA 22 IOUTA 23 RA NIPPON PRECISION CIRCUITS--2 SM5865CM PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IP : Pull-up input Name DVSS DI BCKI WCKI IWSL RSTN TSTN TO DVDD CKI CKDVN CVSS AVSSB N. C. VBB IOUTB RB AVDDB AVDDA N. C. VBA IOUTA RA AVSSA I/O - I I I Ip Ip Ip O - I Ip - - - O O I - - - O O I - Digital ground Data input Bit clock input Word clock input Input data word length select. 24-bit when HIGH, and 20-bit when LOW. System reset. Reset when LOW. Test pin. Tie HIGH or leave open for normal operation. Test output Digital supply System clock input System clock frequency divider ratio select. 1 when HIGH (no division), and 2 when LOW (half of the input frequency). System clock ground Analog ground B Leave open for no connection or connect with ground 1/2 supply output B Inverse-phase analog output B Built-in resistor connection B Analog supply B Analog supply A Leave open for no connection or connect with ground 1/2 supply output A In-phase analog output A Built-in resistor connection A Analog ground A Description NIPPON PRECISION CIRCUITS--3 SM5865CM SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB Parameter Supply voltage range Input voltage range1 Storage temperature range Power dissipation 1. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN. Also applicable during supply switching. Symbol DVDD, AVDDA, AVDDB VIN Tstg PD Rating -0.3 to 7.0 DVSS - 0.3 to DVDD + 0.3 -55 to 125 250 Unit V V C mW Recommended Operating Conditions DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB Parameter Supply voltage range Symbol DVDD, AVDDA, AVDDB DVDD - AVDDA, DVDD - AVDDB, AVDDA - AVDDB, DVSS - AVSSA, DVSS - AVSSB, AVSSA - AVSSB, DVSS - CVSS, AVSSA - CVSS, AVSSB - CVSS Topr Rating 4.5 to 5.5 Unit V Supply voltage variation 0.1 V Operating temperature range -40 to 85 C NIPPON PRECISION CIRCUITS--4 SM5865CM DC Electrical Characteristics Recommended operating conditions, unless otherwise specified. Rating Parameter Symbol Condition min fCKI = 11.2896 MHz DVDD, AVDDA, AVDDB supply current1 IDD fCKI = 16.9344 MHz fCKI = 24.576 MHz fCKI = 36.864 MHz CKI HIGH-level input voltage CKI LOW-level input voltage CKI input voltage HIGH-level input voltage2 LOW-level input voltage2 HIGH-level output voltage3 LOW-level output voltage3 CKI HIGH-level input current CKI LOW-level input current LOW-level input current4 HIGH-level input leakage current5 LOW-level input leakage current5 HIGH-level input leakage current4 1. 2. 3. 4. 5. VIHC VILC VINAC VIH VIL VOH VOL IIHC IILC IIL2 IIH1 IIL1 IIH2 IOH = -1 mA IOL = 1 mA VIN = DVDD VIN = 0 V VIN = 0 V VIN = DVDD VIN = 0 V VIN = DVDD AC coupling - - - - 0.7 x DVDD - 1.0 2.4 - DVDD - 0.4 - 30 30 - - - - typ 7 10 15 21 - - - - - - - 60 60 5 - - - max 11 14 19 26 - 0.3 x DVDD - - 0.5 - 0.4 120 120 15 1.0 1.0 1.0 mA mA mA mA V V Vp-p V V V V A A A A A A Unit No output load, NPC-standard input data pattern. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN. Pin TO. Pins CKDVN, IWSL, RSTN, TSTN. Pins DI, BCKI, WCKI. NIPPON PRECISION CIRCUITS--5 SM5865CM AC Electrical Characteristics System clock Input (CKI) Rating Parameter CKI clock frequency HIGH-level clock pulsewidth LOW-level clock pulsewidth Symbol min fCKI tCWH tCWL 5 5 5 typ - - - max 60 - - MHz ns ns Unit 1/f CKI CKI t CWL t CWH VIHC 0.5DVDD VILC Internal System Clock Rating Parameter Internal system clock frequency Symbol fSYS Condition min 5 typ - max 46 MHz Unit Internal system clock frequency is the same as the CKI clock frequency when CKDVN = HIGH. Internal system clock frequency is half the CKI clock frequency when CKDVN = LOW. Reset Input (RSTN) Rating Parameter Symbol Condition min At power ON RSTN LOW-level pulsewidth tRSTN After power ON 1 100 typ - - max - - s ns Unit NIPPON PRECISION CIRCUITS--6 SM5865CM Serial input (BCKI, DI, WCKI) Rating Parameter BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth BCKI pulse cycle DI setup time DI hold time WCKI edge to first BCKI rising edge Last BCKI rising edge to WCKI edge Symbol min tBCWH tBCWL tBCY tDS tDH tWB tBW 10 10 22 5 5 10 10 typ - - - - - - - max - - - - - - - ns ns ns ns ns ns ns Unit BCKI t BCWH DI t DS WCKI t WB t BW t DH t BCY t BCWL 1.5V 1.5V 1.5V Group Delay Rating Parameter Group delay1 Symbol Tgd Condition min - typ - max 2/fsi s Unit 1. fsi is the input sampling rate of SM5865CM. For example, fsi is 384kHz when this LSI is used in combination with an 8-times oversampling digital filter of which input sampling rate is 48kHz. NIPPON PRECISION CIRCUITS--7 SM5865CM AC Analog Characteristics Measurement Conditions External 8fs digital filter External operational amplifier Supply voltage : NPC SM5847AF : JRC NJM5534D SM5865CM : DVDD = AVDDA = AVDDB = 5V, DVSS = AVSSA = AVSSB = CVSS = 0V SM5847AF NJM5534D : + 3.3V : 15V : 25 C : 48kHz sampling (fs), 24-bit data : 24.576MHz (= 512fs), (64fs noise shaper operation) : Audio Precision System Two (RMS mode) : THD + N : D.R : S/N 22HzHPF, 20kHzLPF (FLP-A20K) 22HzHPF, 22kHzLPF, A-weight (FIL-AWT) 22HzHPF, 22kHzLPF, A-weight (FIL-AWT) Ambient temperature Input data of SM5847AF System clock Audio analyzer Measurement filter condition Measurement circuits diagram : See next page. Analog Characteristics Rating Parameter Output level1 Total harmonic distortion Dynamic range Signal-to-noise ratio Gain drift Symbol Vout THD + N D.R S/N G.D Condition min 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, -60 dB 1 kHz, 0/- dB 1.28 - 111 117 - typ 1.33 0.00030 (- 110.5dB) 117 120 10 max 1.38 0.00060 (- 104.4dB) - - - Vrms % dB dB ppm/C Unit 1. Vout is the output level of the first I-V conversion stage. NIPPON PRECISION CIRCUITS--8 Measurement circuit VCC C3 220p 6 VDD 75 + 1 AVSSA RA IOUTA VBA N.C. 19 2 VCC GND 3 C2 330p 7 5 VDD R6 4.7k 3 GND VEE GND R7 4.7k 2 6 R2 820 U3 4 1 8 NJM5534D VEE R4 620 C4 220p GND 18 17 16 15 14 13 C6 0.1 VEE 6 C7 470 20 21 3 U1 4 1 8 NJM5534D VCC 22 23 GND 2 R3 620 R1 820 GND DVSS 24 C1 330p 75 DI 2 DI BCKI 3 BCKI WCKI 4 WCKI VDD 5 IWSL 6 RSTN AVDDA OUT 2Vrms J1 + C5 4.7 R5 470 C9 100 RB IOUTB VBB N.C. AVSSB C8 0.1 7 TSTN AVDDB SM5865CM 8 TO GND 9 DVDD GND CKI 10 CKI 11 CKDVN 12 CVSS U2 4 1 8 NJM5534D NIPPON PRECISION CIRCUITS--9 GND IC1 SM5865CM SM5865CM Dynamics Characteristics (under Measurement Conditions in page 8) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k d B r A +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10k 20k 30k 40k 50k Hz 60k 70k 80k 90k 100k Figure 1. 0dB input FFT (1) (1kHz notchfilter 32768point 8average) Figure 2. 0dB input FFT (2) (1kHz notchfilter 32768point 8average) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k d B -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 10 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 3. -60dB input FFT (32768point 8average) Figure 4. THD + N vs. Frequency 1 -70 0.5 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 d -92.5 B -95 r A -97.5 -100 -102.5 0.2 0.1 0.05 0.02 % 0.01 0.005 0.002 0.001 0.0005 -105 -107.5 -110 -112.5 -115 -117.5 -120 -120 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0 0.0002 0.0001 -60 -110 -100 -90 -80 -70 -60 dBFS -50 -40 -30 -20 -10 +0 Figure 5. THD + N(%) vs. Amplitude Figure 6. THD + N (dB) vs. Amplitude +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d +0.1 B +0 r A -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 10 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0 d B r A 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 7. Linearity Figure 8. Evaluation Board Frequency Response NIPPON PRECISION CIRCUITS--10 SM5865CM FUNCTIONAL DESCRIPTION Analog Outputs IOUTA, IOUTB The SM5865CM input data in-phase signal is processed by noise shaper A and 31-level DEM-DAC with current output on differential output A, and input data reverse-phase signal is processed by noise shaper B and 31level DEM-DAC with current output on differential output B. Differential outputs A and B also have separate in-phase and reverse-phase outputs: A in-phase output and B reverse-phase output are connected internally and output on IOUTA, and B in-phase output and A reverse-phase output are connected internally and output on IOUTB. The IOUTA and IOUTB current outputs are I/V converted by external circuit and then input to a differential input op-amp to obtain the final analog signal. RA, RB Internal resistors are connected between IOUTA and RA pins and between IOUTB and RB pins, which serve as the op-amp feedback resistors. The feedback resistors have a resistance of 4.7k. The I/V converter output gain can be adjusted by connecting external resistors in parallel or serial with the internal resistors. Note, however, that the internal resistance can vary from device to device by 10%, and if external resistors are used, the output level changes depending on the difference between each resistor ratio. If the I/V converter gain is increased, a dynamic range higher even than that given in "Analog Characteristics (page 8)" can be obtained. In-phase output A RA IOUTA Data input Noise shaper A 31 Level DEM DAC Inverse-phase output A In-phase output B RB IOUTB Noise shaper B 31 Level DEM DAC Inverse-phase output B Figure 9. Analog outputs NIPPON PRECISION CIRCUITS--11 SM5865CM VBA, VBB A 0.5VDD signal is output from VBA, VBB using a resistor divider network. Using these pins allows the use of the SM5865CM to replace the pin-compatible SM5865BM product. RA 31 Level DEM DAC 31 Level DEM DAC IOUTA VBA SM5865CM RB 31 Level DEM DAC 31 Level DEM DAC IOUTB VBB Figure 10. VBA, VBB Audio Data Input (DI, BCKI, WCKI, IWSL) I Input data format The audio data is input in MSB-first, 2s-complement, 24-bit/20-bit serial format. The input word bit length is selected by IWSL, 24-bit when HIGH, and 20-bit when LOW. I Jitter-free function The SM5865CM serial input data from DI synchronize with the word clock (WCKI) and are read into the first register stage, and those also synchronize with the clock derived from divided system clock and are read into the next register stage. This word clock and the system clock are always phase compared. When a phase shift was detected, the comparison result is used to perform input timing adjustment in the system clock. Therefore this process enable internal calculations not to be affected by generated large jitter on the word clock or changing the sampling rate during inputting data. System Clock Divider (CKDVN) The SM5865CM has a built-in clock frequency divider. The divider enables the internal system clock to operate at half the input frequency, for example when the external system clock input frequency is high. System Reset (RSTN) The device should be reset in the following cases. I I At power ON When the system clock CKI stops, or other abnormalities occur. The device is reset by applying a LOW-level pulse on RSTN. NIPPON PRECISION CIRCUITS--12 SM5865CM Theoretical Quantization Noise Reduction The SM5865CM employs a 3rd-order 31-level quantized noise shaper to widely reduce quantization noise in the audio band to the high frequency bandwidth. The theoretical quantization noise level at 16fs to 96fs operation is shown in figure 11. 0 10 20 30 40 50 Quantization noise (dB) 60 70 80 90 100 110 120 130 140 150 160 170 180 0 0.5 1 1.5 2 2.5 3 3.5 4 24-bit, fs quantization noise level 20-bit, fs quantization noise level 16-bit, fs quantization noise level 0 dB sine wave equivalent white noise level 16fs 24fs 32fs 48fs 64fs 96fs Frequency (fs) Figure 11. Theoretical quantization noise level NIPPON PRECISION CIRCUITS--13 SM5865CM Internal Oversampling Operation The SM5865CM accepts data output from an 8-times or 4-times oversampling digital filter, and oversampled internally again up to the noise shaper operating rate. The internal oversampling factor is determined automatically from the system clock input frequency and the input sampling frequency. This internal oversampling factor (n) must be an integer satisfying the conditions shown in table 1. Table 1. Operating conditions Parameter fWCKI and fCKI compulsory conditions1 CKDVN = HIGH CKDVN = LOW f CKI = f WCKI x 8 x n where n = 1, 2, 3, ... f CKI = f WCKI x 16 x n where n = 1, 2, 3, ... Noise shaper operating frequency f CKI f ns = f WCKI x n = ---------8 f CKI f ns = f WCKI x n = ---------16 1. fWCKI = word clock frequency, fCKI = input system clock frequency, n = internal oversampling factor Word clock input WCKI SM5865CM System clock input CKI System clock divider select CKDVN Figure 12. Clock-related inputs NIPPON PRECISION CIRCUITS--14 SM5865CM System Clock Frequencies Table 2 shows some possible combinations for the circuit configuration shown in figure 13. fs Interpolating filter (8-times/4-times) fWCKI SM5865CM fCKI Figure 13. Circuit configuration Table 2. System clock frequencies (CKDVN = HIGH) fs 16 kHz 16 kHz 16 kHz 32 kHz 32 kHz 32 kHz 32 kHz 32 kHz 44.1 kHz 44.1 kHz 44.1 kHz 44.1 kHz 44.1 kHz 48 kHz 48 kHz 48 kHz 48 kHz 48 kHz 88.2 kHz 88.2 kHz 88.2 kHz 88.2 kHz 96 kHz 96 kHz 96 kHz 176.4 kHz 176.4 kHz 192 kHz System clock frequency1 fCKI 6.144 MHz (384fs) 8.192 MHz (512fs) 12.288 MHz (768fs) 6.144 MHz (192fs) 8.192 MHz (256fs) 12.288 MHz (384fs) 16.384 MHz (512fs) 24.576 MHz (768fs) 8.4672 MHz (192fs) 11.2896 MHz (256fs) 16.9344 MHz (384fs) 22.5792 MHz (512fs) 33.8688 MHz (768fs) 9.216 MHz (192fs) 12.288 MHz (256fs) 18.432 MHz (384fs) 24.576 MHz (512fs) 36.864 MHz (768fs) 16.9344 MHz (192fs) 22.5792 MHz (256fs) 33.8688 MHz (384fs) 45.1584 MHz (512fs) 18.432 MHz (192fs) 24.576 MHz (256fs) 36.864 MHz (384fs) 33.8688 MHz (192fs) 45.1584 MHz (256fs) 36.864 MHz (192fs) Noise shaper operating rate 48fs 64fs 96fs 24fs 32fs 48fs 64fs 96fs 24fs 32fs 48fs 64fs 96fs 24fs 32fs 48fs 64fs 96fs 24fs 32fs 48fs 64fs 24fs 32fs 48fs 24fs 32fs 24fs Internal factor (8fs input) 6 8 12 3 4 6 8 12 3 4 6 8 12 3 4 6 8 12 3 4 6 8 3 4 6 3 4 3 CKDVN Internal factor (4fs input) 12 16 24 6 8 12 16 24 6 8 12 16 24 6 8 12 16 24 6 8 12 16 6 8 12 6 8 6 1. When CKDVN = LOW, the system clock frequency fCKI is halved, so the values shown are half the input frequency required for the same sampling rate and internal factors. NIPPON PRECISION CIRCUITS--15 SM5865CM TIMING DIAGRAMS 192fs System Clock Input Timing 1 / 8fs WCKI CKI BCKI (1)20bit * DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (3)24bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 384fs System Clock Input Timing 1 / 8fs WCKI CKI BCKI (1)20bit * DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (3)24bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 *: Data can be input at any period within the word clock cycle. NIPPON PRECISION CIRCUITS--16 SM5865CM 256fs System Clock Input Timing 1 / 8fs WCKI CKI BCKI (1)20bit * DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (3)24bit * DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BCKI (4)24bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 512fs System Clock Input Timing 1 / 8fs WCKI CKI BCKI (1)20bit * DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (3)24bit * DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BCKI (4)24bit DI MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 *: Data can be input at any period within the word clock cycle. NIPPON PRECISION CIRCUITS--17 SM5865CM TYPICAL APPLICATIONS Input Interface Circuit XTI DOL DOR SM5847AF WCKO BCKO DI WCKI BCKI CKI SM5865CM CKI DI WCKI BCKI SM5865CM NIPPON PRECISION CIRCUITS--18 SM5865CM Analog Output Circuits Analog Output Circuit 1 RA 31 Level DEM DAC 31 Level DEM DAC IOUTA SM5865CM RB 31 Level DEM DAC 31 Level DEM DAC IOUTB Analog Output Circuit 2 RA 31 Level DEM DAC 31 Level DEM DAC IOUTA SM5865CM RB 31 Level DEM DAC 31 Level DEM DAC IOUTB Note that the output analog characteristics and other specifications are not guaranteed for particular formats or application circuits. Note that NPC has no responsibility for patents related to application circuits in these datasheets. NIPPON PRECISION CIRCUITS--19 SM5865CM NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales@npc.co.jp NC0019AE 2000.12 NIPPON PRECISION CIRCUITS--20 NIPPON PRECISION CIRCUITS INC. |
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