View TDA9209_152863.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA9209
150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS INCLUDING CUT-OFF INPUTS AND VIDEO DETECTION
FEATURE
s s s s
s s
s
s
s s
s
s s s
s s s s
150 MHZ PIXEL RATE 2.7 ns RISE AND FALL TIME I2C BUS CONTROLLED GREY SCALE TRACKING VERSUS BRIGHTNESS OSD MIXING NEGATIVE FEED-BACK FOR DC COUPLING APPLICATION INTERNAL POSITIVE FEED-BACK FOR LCD APPLICATION 0.5~4.5 V DACs FOR BLACK LEVEL RESTORATION (AC-COUPLING APPLICATION) OR CUT-OFF CONTROLS (FOR DC-COUPLING APPLICATION USING THE ST AMPLIFIERS TDA9533/9530) BEAM CURRENT ATTENUATION (ABL) PEDESTRAL CLAMPING ON OUTPUT STAGE POSSIBILITY OF LIGHT OR DARK GREY OSD BACKGROUND OSD INDEPENDENT CONTRAST CONTROL ADJUSTABLE BANDWIDTH INPUT BLACK LEVEL CLAMPING WITH BUILT-IN CLAMPING PULSE STAND-BY MODE 5 V TO 8 V POWER SUPPLY SYNC CLIPPING FUNCTION (SOG) VIDEO DETECTION
SHRINK DIP24 (Shrink Plastic Package) ORDER CODE: TDA9209
DESCRIPTION The TDA9209 is an I2C Bus controlled RGB preamplifier designed for Monitor application, able to mix the RGB signals coming from any OSD device. The usual Contrast, Brightness, Drive and Cut-Off Controls are provided. In addition, it includes the following features: - OSD contrast, - Bandwidth adjustment, - Grey background, - Internal back porch clamping pulse generator.
The RGB incoming signals are amplified and shaped to drive any commonly used video amplifiers without intermediate follower stages. Even though encapsulated in a 24-pin package only, this IC allows any kind of CRT Cathode coupling : - AC coupling with DC restore, - DC coupling with Feed-back from Cathodes, - DC coupling with Cut-Off controls of the Video amplifier (ST Amplifiers TDA9533/9530). As for any ST Video pre-amplifier, the TDA9209 is able to drive a real load without any external interface. One of the main advantages of ST devices is their ability to sink and source currents while most of the devices from our competitors have problems to sink large currents. These driving capabilities combined with an original output stage structure suppress any static current on the output pins and therefore reduce dramatically the power dissipation of the device. Extensive integration combined with high performance and advanced features make the TDA9209 one of the best choice for any CRT Monitor in the 14" to 17" range. Perfectly matched with the ST Video Amplifiers TDA9530/33, these 2 products offer a complete solution for high performance and cost-optimized Video Board Application. Version 4.2
March 2000
1/22
1
TDA9209
1 - PIN CONNECTIONS
IN1 ABL IN2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BLK HSYNC or BPCP CO1/FB1 OUT1 VCCP OUT2 GNDP OUT3 CO3/FB3 CO2/FB2 SDA SCL
GNDL
IN3 GNDA
VCCA
AV OSD1 OSD2 OSD3 FBLK
2 - PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol IN1 ABL IN2 GNDL IN3 GNDA VCCA AV OSD1 OSD2 OSD3 FBLK SCL SDA CO2/FB2 CO3/FB3 OUT3 GNDP OUT2 VCCP OUT1 CO1/FB1 HSYNC BPCP BLK Red Video Input ABL Input Green Video Input Logic Ground Blue Video Input Analog Ground Analog VCC (5V) Active Video Output Red OSD Input Green OSD Input Blue OSD Input Fast Blanking SCL SDA Green Cut-off Output/Feedback Input Blue Cut-off Output/Feedback Input Blue Video Output Power Ground Green Video Output Power VCC (5 V to 8 V) Red Video Output Red Cut-off Output/Feedback Input HSYNC BPCP Blanking Input Description
2/22
TDA9209
3 - BLOCK DIAGRAM
BLK FBLK 12 Output Clamp Pulse (OCL) Drive Output Stage 21 OUT1 22 CO1/FB1 Clamp VCCP 20
TDA9209
VREF IN1 1
24
Contrast
IN2 3
Green Channel
19 OUT2 15 CO2/FB2 17 OUT3 16 CO3/FB3 Cut-off 8bits
IN3 5 ABL 2 BPCP Contrast/8bit
Blue Channel
Brightness Drive 8bits 3x8bits Latches I2C Bus Decoder D/A
18
GNDP
GNDL
4
IC OSD Cont. 4bits
Output DC Level 4bits
GNDA 6 VCCA 7 AV 8 23 HSYNC or BPCP 14 13 SDA SCL
VREF 9 OSD1 10 OSD2 11 OSD3
see Figure 12 for complete BPCP and OCL generation diagram
4 - FUNCTIONAL DESCRIPTION
4.1 RGB Input The three RGB inputs have to be supplied through coupling capacitors (100 nF). The maximum input peak-to-peak video amplitude is 1 V. The input stage includes a clamping function. The clamp uses the input serial capacitor as a "memory capacitor". To avoid a discharge of the serial capacitor during the line (due to leakage current), the input voltage is referenced to the ground. The clamp is gated by an internally generated "Back Porch Clamping Pulse" (BPCP). Register 8 allows to choose the way to generate this BPCP (see Figure 1). When bit 0 is set to 0, the BPCP is synchronized on the trailing or leading edge of HSYNC (Pin 23) (bit 1 = 0: trailing edge, bit 1 = 1: leading edge).
3/22
TDA9209
Additionally, the IC automatically works with either positive or negative HSYNC pulses. - When bit 0 is set to 1, BPCP is synchronized on the leading edge of the blanking pulse BLK (Pin 24). One can use a positive or negative blanking pulse by programming bit 0 in Register 9 (See I 2C Table 3). - BPCP width can be adjusted with bit 2 and 3 (see Register 8, I2C table 2). - If the application already provides the Back Porch Clamping Pulse, bit 4 must be set to 1 (providing a direct connection between Pin 23 and internal BPCP). 4.2 Synchro Clipping Function This function is available on channel 2 (Green Channel). When using the Sync On Green (SOG) (Synchro pulse included in the green channel inFigure 1.
R8b0=0 and R8b1=0 HSYNC/BPCP (Pin23)
put) the synchro clipping function must be activated (bit 7 set to 1 in register 9) in order to keep the right green output levels and avoid unbalanced colours. 4.3 Blanking Input The Blanking pin (FBLK) is TTL compatible. The Blanking pulse can be: - positive or negative - line or Composite-type (but not Frame-type). 4.4 Contrast Adjustment (8 bits) The contrast adjustment is made by controlling simultaneously the gain of the three internal amplifiers through the I2C bus interface. Register 1 allows the adjustment in a range of 48 dB.
Internal BPCP R8b0=0 and R8b1=1 HSYNC/BPCP (Pin23) Internal BPCP
R8b0=1 BLK (Pin24) Internal BPCP R8b4 =1 HSYNC/BPCP (Pin23) Internal BPCP
4.5 ABL Control The TDA9209 includes an ABL (automatic beam limitation) input to attenuate the RGB Video signals depending on the beam intensity.
The operating range is 2 V (from 3 V to 1 V). A typical 15 dB maximum attenuation is applied to the output signal whatever the contrast adjustment is. (See Figure 2 ). When the ABL feature is not used, the ABL input (Pin 2) must be connected to a 5 V supply voltage.
4/22
TDA9209
Figure 2.
0 -2 -4 -6 -8 -10 -12 -14 -16 0 Attenuation (dB)
VABL (V) 1 2 3 4 5
4.6 Brightness Adjustment (8 bits) Brightness adjustment is controlled by the I2C Bus via Register 2. It consists of adding the same DC voltage to the three RGB signals, after contrast adjustment. When the blanking pulse equals 0, the DC voltage is set to a value which can be adjusted between 0 and 2V with 8mV steps (see Figure 3). The DC output level is forced to the "Infra Black" level (VDC) when the blanking pulse is equal to 1. 4.7 Drive Adjustment (3 x 8 bits) In order to adjust the white balance, the TDA9209 offers the possibility of adjusting separately the overall gain of each channel thanks to the I2C bus (Registers 3, 4 and 5). The very large drive adjustment range (48 dB) allows different standards or custom color temperatures. It can also be used to adjust the output voltages at the optimum amplitude to drive the CRT drivers, keeping the whole contrast control for the enduser only. The drive adjustment is located after the Contrast, Brightness and OSD switch blocks, so it does not affect the white balance setting when the BRT is adjusted. It also operates on the OSD portion of the signal. 4.8 OSD Inputs The TDA9209 allows to mix the OSD signals into the RGB main picture. The four pins dedicated to this function are the following: - Three TTL RGB inputs (Pins 9, 10, 11) connected to the three outputs of the corresponding OSD processor. - One TTL fast blanking input (Pin 12) also connected to the FBLK output of the OSD processor. When a high level is present on the FBLK, the IC acts as follows:
- The three main picture RGB input signals (IN1, IN2, IN3) are internally switched to the internal input clamp reference voltage. - The three output signals are set to the voltage corresponding to the three OSD input logic states (0 or 1). (See Figure 3). If the OSD input is at low level, the output and brightness voltages (VBRT) are equal. If the OSD input is at high level, the output voltage is VOSD, where V OSD = VBRT + OSD and OSD is an I2C bus-controlled voltage. OSD varies between 0 V to 4.9 V by 320 mV steps via Register 7 (4 bits). The same variation is applied simultaneously to the three channels providing the OSD contrast. The grey color can be obtained on output signals when: - OSD1 = 1, OSD2 = 0 and OSD3 = 1, - A special bit (bit 5 or 6) in Register 9 is set to 1. If R9b5 is set to 1, light grey is obtained on output. If R9b6 is set to 1, dark grey is obtained on output. In the case where R9b5 and R9b6 are set to 0, the normal operation is provided on output signals. 4.9 Output Stage The overall waveforms of the output signal are shown in Figure 3 and Figure 4. The three output stages, which are large bandwidth output amplifiers, are able to deliver up to 4.4 VPP for 0.7 V PP on input. When a high level is applied on the BLK input (Pin 24), the three outputs are forced to "Infra Black" level (VDC) thanks to a sample and hold circuit (described below). The black level (which is the output voltage outside the blanking pulse with minimum brightness and no Video input signals) is 400 mV higher than VDC. The brightness level (VBRT) is then obtained by programming register 2 (see I2C table 1). The sample and hold circuit is used to control the "Infra Black" level in the range of 0.5 V to 2.5 V via Register 6 (in case of AC coupling) or Registers 10, 11, 12 (in case of DC coupling) . This sampling occurs during an internal pulse (OCL) generated inside the blanking pulse window. Refer to "CRT cathode coupling" part for further details.
5/22
TDA9209
Functioning with 5 V Power VCC To simplify the application, it is possible to supply the power VCC with 5 V (instead of 8 V nominal) at the expense of output swing voltage. Functioning without Blanking Pulse If no blanking pulse is applied to the TDA9209, the internal BPCP can be connected to the sample Figure 3. Waveforms VOUT, BRT, CONT, OSD
and hold circuit (Register 8, bit 7 = 1 and BLK pin grounded) so that the output DC level is still controlled by I2C. To ensure the device correct behavior in the worst possible conditions, the Brightness Register must be set to 0.
HSYNC BPCP BLK Video IN FBLK OSD IN
V
(4) CONT (5) V OSD (3) VBRT (2) V BLACK VDC (1)
VOUT1 , VOUT2 , VOUT3 CONT BRT 0.4V fixed
OSD
Notes : 1. VDC 2. VBLACK 3. VBRT 4. VCONT 5. VOSD
= = = = =
0.5 to 2.5V V DC + 0.4V V BLACK + BRT (with BRT = 0 to 2V) V BRT + CONT = k x Video IN (CONT = 4.4VPP max. for VIN = 0.7V PP) V BRT + OSD (OSD max. = 4.9VPP , OSD min = 0VPP)
6/22
TDA9209
Figure 4. Waveforms (Drive adjustment)
HSYNC
BPCP BLK Video IN BFLK OSD IN VOUT1, VOUT2, VOUT3
VCONT V OSD VBRT
VBLACK VDC Two examples of drive adjustment (1)
Note : 1.Drive adjustment modifies the following voltages : VCONT, VBRT and V OSD. Drive adjustment doesn't modify the following voltages : VDC and VBLACK.
4.10 Bandwidth Adjustment A new feature: Bandwidth adjustment, has been implemented on the TDA9209. This function has several advantages: - Depending on the external capacitive load and on the peak-to-peak output voltage, the bandwidth can be adjusted to avoid any slew-rate phenomenon. - The preamp bandwidth can be adjusted in order to reduce electromagnetic radiation, since it is possible to slow down the signal rise/fall time at the CRT driver input without too much affecting the rise/fall time at the CRT driver output. - It is possible to optimize the ratio of the frequency response versus the CRT driver power consumption for any kind of chassis, as the preamp bandwidth adjustment also allows the adjustment of the rise/fall time on the cathode (through the CRT driver).
- In still picture mode, when a high Video swing voltage is of greater interest than rise/fall time, bandwidth adjustment is used to avoid any slewrate phenomenon at the CRT driver output and to meet electromagnetic radiation requirements. 4.11 CRT Cathode Coupling The powerfull multiplex capability of the TDA9209 allows to use the device with several kinds of CRT cathode coupling. 4.11.1 AC coupling with DC restore ( Figure 5) In this mode the output DC level (VDC) is adjusted simultaneously for the 3 channels from 0.5 V to 2.35 V via Register 6 (4 bits). The cut-off voltage is programmed independently for each channel from 0.17 V to 4.6 V using registers 10, 11, 12 (8 bits each, see I2C Table 1).
7/22
TDA9209
4.11.2 DC Coupling with cut-off controls on Video Amplifier (with TDA9533/ 9530, Figure 6) The functioning and programming of the TDA9209 are the same as for the previous mode, except for 4.11.3 DC Coupling Mode (Figure 7) This is the most commonly used configuration enabling to build a powerful video system on a small PCB Board and giving a substantial cost saving compared with any other solution available on the market. The preamplifier outputs control directly the cut-off levels. The output DC level (VDC) is adjusted independently for each channel from 0.5 V to 2.5 V via registers 10, 11 and 12. In DC coupling mode, bit 2 must be set to 1 and bit3 to 0 in Register 9. Figure 5. AC Coupling
TDA9209
the cut-off control which is now performed via the Video amplifier cut-off input . In AC coupling and DC coupling with cut-off control, bits 2, 3 and 4 in Register 9 must be set to 1. 4.11.4 DC Coupling with feedback mode (Fig. 8) In this mode, the feedback voltage issued from the cathode is sent to the TDA9209. This voltage is compared to a reference from the cut-off DC level DAC by the sample and hold circuit who also controls the DC voltage of the feedback input in a range of 0.5 V to 2.5 V. Each channel is independently controlled via Registers 10, 11 and 12. In DC coupling with feedback mode, bit 2 and bit 4 must be set to 0 in Register 9.
Pins 17-19-21
CRT Driver
CRT
DC LEVEL (4bits) 0.5V to 2.35V CUT-OFF 1,2,3 DC LEVEL 0.17V to 4.6V(8bits)
Pins15-16-22
Cut-off Control
Figure 6. DC Coupling with Cut-off Control
TDA9209
CRT Pins 17-19-21 TDA9533/9530
DC LEVEL (4bits) 0.5V to 2.35V CUT-OFF 1,2,3 DC LEVEL 0.17V to 4.6V (8bits)
Pins 15-16-22
8/22
TDA9209
Figure 7. DC Coupling
TDA 9209
Pins17-19-21 CRT Driver CRT
OUTPUT 1,2,3 DC LEVEL 0.5V to 2.5V (8bits)
Figure 8. DC Coupling with Feedback (LCD mode)
TDA 9209
Pins 17-19-21 CRT Driver Pins 15-16-22 CUT-OFF 1,2,3 DC LEVEL 0.5V to 2.5V (8bits) CRT
4.12 Stand-by Mode The TDA9209 has a stand-by mode. As soon as the VCC power (Pin 20) gets lower than 3V (typ.), the device is set in stand-by mode whatever the voltage on analog VCCA (Pin 7) is. The analog blocks are internally switched-off while the logic parts (I2C bus, power-on reset) are still supplied. In stand-by mode, the power consumption is below 20 mW. 4.13 Serial Interface The 2-wire serial interface is an I2C interface. The slave address of TDA9209 is DC hex.
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W 0
The host MCU can write into the TDA9209 registers. Read mode is not available. In order to write data into the TDA9209, after the "start" message, the MCU must send the following data (see Figure 9): - the I2C address slave byte with a low level for the R/W bit, - the byte to the internal register address where the MCU wants to write data, - the data. All bytes are sent with MSB bit first. The transfer of written data is ended with a "stop" message. When transmitting several data, the register addresses and data can be written with no need to repeat the start and slave addresses.
9/22
TDA9209
4.14 Power-on Reset A power-on reset function is implemented on the TDA9209 so that the I2C registers have a determined status after power-on. The Power-on reset Figure 9. I2C Write Operation
SCL SDA Start I2C Slave Address W A7 ACK A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop
threshold for a rising supply on VCCA (Pin 7) is 3.8 V (typ.) and 3.2V when the VCC decreases.
Register Address
Data Byte
4.15 Video detection (see Figure 10) The video detection consists of three fast comparators and a OR function. The positive input of each comparator is connected to the input video pin (R, G, or B). The negative inputs are connected together to a reference voltage. This voltage is the threshold of the comparators. The typical threshold voltage is 120 mV. The three comparator outputs are conFigure 10. Video Detection
IN1 1
nected to the OR inputs. Active Video output can be inhibited by using bit 7 in Register 13 : R13b7 = 0 R13b7 = 1 AV inhibited AV validated
When AV output is validated, the AV output reaches 5V when at least one of the 3 video inputs gets higher than 3.8V (typ.), and decreases to 0V if the 3 input voltages get lower than 3.2V (typ.).
IN2 3
8
IN3 5
AV
120mV
R13b7=0
10/22
TDA9209
5 - ABSOLUTE MAXIMUM RATINGS
Symbol VCCA Max. VCCP Max. Vin Max. VI Max. Tstg Toper Parameter Supply Voltage on Analog VCC Supply Voltage on Power VCC Voltage at any Input Pins (except Video inputs) and Input/Output Pins Voltage at Video Inputs Storage Temperature Operating Junction Temperature Pin 7 20 1, 3, 5 Value 5.5 8.8 5.5 1.4 +150 Units V V V V C C
6 - THERMAL DATA
Symbol R th(j-a) Tj Parameter Max. Junction-ambient Thermal Resistance Typ. Junction Temperature at Tamb = 25C Value 69 80 Units C/W C
7 - DC ELECTRICAL CHARACTERISTICS
T amb = 25C, VCCA = 5V, VCCP = 8V, unless otherwise specified.
Symbol VCCA VCCP ICCA ICCP VI Vo VIL VIH IIN RHS Parameter Analog Supply Voltage Power Supply Voltage Analog Supply Current Power Supply Current Video Input Voltage Amplitude Output Voltage Range Low Level Input Voltage High Level Input Voltage Input Current Input Resistor OSD, FBLK, BLK, HSYNC 2.4 OSD, FBLK, BLK HSYNC -1 40 1 0.5 Test Conditions Pin 7 Pin 20 VCCA = 5V VCCP = 8V Min. 4.5 4.5 Typ. 5 8 70 55 0.7 1 V CCP -0.5V 0.8 Max. 5.5 8.8 Units V V mA mA V V V V A k
11/22
TDA9209
8 - AC ELECTRICAL CHARACTERISTICS
Tamb = 25C, VCCA = 5V, VCCP= 8V, V i = 0.7 VPP, CLOAD = 5pF RS = 100, serial between output pin and CLOAD, unless otherwise specified.
Symbol Parameter Test Condit ions Min. Typ. Max. Units VIDEO INPUTS (PINS 1, 3, 5) VI GAM VOM VON CAR DAR GM tR, tF BW BW Video Input Voltage Amplitude Maximum Gain Maximum Video Output Voltage (Note) Nominal Video Output Voltage Contrast Attenuation Range Drive Attenuation Range Gain Matching Rise Time, Fall Time (Note) Large Signal Bandwidth Bandwidth Adjustment Range Max. Contrast and Drive Max Contrast and Drive (CRT = DRV = 254 dec) Max Contrast and Drive (CRT = DRV = 254 dec) Contrast and Drive at POR (CRT = DRV = 180 dec) From max. Contrast (CRT=254 dec) to min. Contrast (CRT = 1 dec) From Max. Drive (DRV = 254 dec) to min Drive (DRV = 1 dec) Contrast and Drive at POR VOUT = 2 VPP (BW = 15 dec) VOUT = 2 VPP (BW = 0 dec) VOUT = 2 V PP VOUT = 2 V PP Minimum bandwidth (BW = 0 dec) Maximum bandwidth (BW =15 dec) VOUT = 2 V PP @ f = 10 MHz @ f = 50 MHz 48
0.1
0.7 16 4.4 2.2 48
1
V dB V V dB dB dB ns ns MHz MHz MHz dB dB V V V mV
VIDEO OUTPUT SIGNAL (PINS 17, 19, 21) - GENERAL
2.7 4.3 130 80 130 60 35 2 0 0.4
CT
Crosstalk between Video Outputs
VIDEO OUTPUT SIGNAL -- BRIGHTNESS BRTmax BRTmin VIP BRTM Maximum Brightness Level Minimum Brightness Level Insertion Pulse Brightness Matching Brightness and Drive at POR Max. Drive (DRV = 254 dec) Max. OSD (OSD = 15 dec) Min. OSD (OSD = 0 dec) Max. DCL (DCL= 15 dec) Min. DCL (DCL = 3 dec) Max. Brightness (BRT = 255 dec) and Max. Drive (DRV = 254 dec) Min. Brightness (BRT = 0 dec) and Max. Drive (DRV = 254 dec)
10
VIDEO OUTPUT SIGNAL -- OSD OSDmax OSDmin DCLmax DCLmin DCLstep DCLmax DCLmin DCLstep Maximum OSD Output Level Minimum OSD Output Level Maximum Output DC Level Minimum Output DC Level Output DC Level Step Maximum Output DC Level Minimum Output DC Level Output DC Level Step Max. Cut-off (Cut-off = 255 dec) Min. Cut-off (Cut-off = 40 dec) 4.9 0 2.35 0.5 155 2.5 0.4 10 V V V V mV V V mV
VIDEO OUTPUT SIGNAL -- DC LEVEL (AC COUPLING MODE)
VIDEO OUTPUT SIGNAL -- DC LEVEL (DC COUPLING MODE)
Assuming that VOM remains within the range of Vo (between 0.5V and VCCP - 0.5V) tR, tF are calculated values, assuming an ideal input rise/fall time of 0ns (tR = tROUT2 + tRIN2 , tF = tFOUT2 + tFIN2
12/22
TDA9209
AC ELECTRICAL CHARACTERISTICS (continued)
Tamb = 25C, VCCA = 5V, VCCP= 8V, Vi = 0.7 VPP, C LOAD = 5 pF, unless otherwise specified Symbol Parameter Test Condit ions Min. CUT-OFF OUTPUTS (AC COUPLING MODE) - (Pins 15, 16, 22) COmax COmin COTD COHIin COLIin COstep Maximum Cut-off Output Level Minimum Cut-off Output Level Cut-off Output Voltage Drift Maximum Cut-off Output Voltage (linear region) Minimum Cut-off Output Voltage (linear region) Cut-off Output Step (linear region) Controlled Feedback Input Level Maximum Minimum Controlled Feedback Input Level Step input Current on Feedback inputs V 2.5V VABL 3.2 V Max. Cut-off (Cut-off = 255 dec) and Sourced Current = 200A Min. Cut-off (Cut-off = 0 dec) and Sinked Current = 2mA Tj Variation = 100C Cut-off =235dec (Sourced Current = 200A) Cut-off = 10 dec (Sinked current = 2mA) 4.7 0.1 0.5 4.6 0.17 20 V V % V V mV Typ. Max. Units
FEEDBACK INPUTS (DC WITH FEEDBACK MODE) VFBmax VFBmin VFBstep IFB ABL (PIN 2) GABLmin GABLmax VABL IABLhigh IABLlow ABL Mini Attenuation ABL Maxi Attenuation ABL Threshold Voltage High ABL Input Current Low ABL Input Current Max. Cut-off (Cut-off = 255 dec) Min. Cut-off (Cut-off = 1 dec) 2.5 20 10 50 V mV mV A
VABL = 1 V
For output attenuation
0 15 3 0 -2
dB dB V A A
VABL = 3.2V VABL = 1V
VIDEO DETECTION VTHAV DELAY PixAV Comparator Threshold Delay between Video Output and AV output Minimum pixel width 3pF load on AV out (Pin8) 120 10 10 mV ns ns
Vin = 0.7VPP
13/22
TDA9209
9 - I2C ELECTRICAL CHARACTERISTICS
T amb = 25C, VCCA = 5V, unless otherwise specified
Symbol VIL VIH IIN fSCL(Max.) VOL Parameter Low Level Input Voltage High Level Input Voltage Input Current (Pins SDA, SCL) SCL Maximum Clock Frequency Low Level Output Voltage SDA Pin when ACK Sink Current = 6mA 0.4 V < VIN < 4.5 V Test Conditi ons On Pins SDA, SCL 3 -10 200
+10
Min.
Typ.
Max. Units 1.5 V V A kHz V 0.25 0.6
10 - I 2C INTERFACE TIMING REQUIREMENTS
(see Figure 11)
Symbol tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tR, tF Parameter Time the bus must be free between two accesses Hold Time for Start Condition Set-up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set-up Time Data Rise and Fall Time of both SDA and SCL Min. 1300 600 600 1300 600 300 250 20 300 Typ. Max. Units ns ns ns ns ns ns ns ns
Figure 11. I2C Timing Diagram
t SDA t SCL t
HIGH HDS BUF
t
HDAT
t
SUDAT
t
SUP
t
LOW
14/22
TDA9209
11 - I 2C REGISTER DESCRIPTION
Register Sub-addressed - I2C Table 1
Sub-address Hex 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D Dec 01 02 03 04 05 06 07 08 09 10 11 12 13 Contrast (CRT) Brightness (BRT) Drive 1 (DRV) Drive 2 (DRV) Drive 3 (DRV) Output DC Level (DCL) OSD Contrast (OSD) BPCP & OCL Miscellaneous Cut Off Out 1 DC Level (Cut-off) Cut Off Out 2 DC Level (Cut-off) Cut Off Out 3 DC Level (Cut-off) Bandwidth Adjustment (BW) 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC 4-bit DAC Refer to the I2C table 2 Refer to the I2C table 3 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC Register Names POR Value Hex B4 B4 B4 B4 B4 09 09 04 1C B4 B4 B4 07 Dec 180 180 180 180 180 09 09 04 28 180 180 180 07 FF FF FF 0F 255 255 255 15 Max. Value Hex FE FF FE FE FE 0F 0F Dec 254 255 254 254 254 15 15
For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed. For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06). For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C).
BPCP & OCL Register (R8) - I2C Table 2 (see also Figure12)
b7 b6 b5 b4 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 b3 b2 b1 b0 0 1 Function Internal BPCP triggered by HSYNC Internal BPCP triggered by BLK Internal BPCP synchronized by the trailing edge Internal BPCP synchronized by the leading edge Internal BPCP Width = 0.33 s Internal BPCP Width = 0.66 s Internal BPCP Width = 1 s Internal BPCP Width = 1.33 s Internal BPCP = BPCP input (Pin 23) Normal Operation Reserved (Force BPCP to 1 in test) Normal Operation Reserved (Force OCL to 1 in test) Internal OCL pulse triggered by BLK (pin 24) Internal OCL pulse = Internal BPCP x x x x x POR Value x
15/22
TDA9209
Miscellaneous Register (R9) - I2C Table 3
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 1 x 0 0 0 0 1 0 1 0 1 0 0 1 0 x 1 1 0 Function Positive Blanking Polarity Negative Blanking Polarity Soft Blanking = OFF Soft Blanking = ON AC Coupling Mode or DC with Cut-off control DC Coupling Mode DC Coupling with Feedback Mode Light Grey on OSD Outputs = OFF Light Grey on OSD Outputs = ON Dark Grey on OSD Outputs = OFF Dark Grey on OSD Outputs = ON SOG Clipping = OFF SOG Clipping = ON x x x x x POR Value x
Bandwidth Adjustment (R13) - I2C Table 4
b7 b6 b5 b4 b3 1 0 0 0 0 1 0 1 0 0 0 1 0 b2 1 1 0 b1 1 1 0 b0 1 1 0 130 MHz 100 MHz 80 MHz Normal Operation BW DAC output connected to BLK input (for test) BW DAC complementary output connected to BLK input (for test) Active Video Output Inhibited Active Video Output Validated x x x Function POR Value
Figure 12. BPCP and OCL Generation
Source Selection R8b0 HS/BPCP (External) HS edge Selection R8b1 Width Selection R8b2b3 BPCP Source Selection R8b4 BPCP (Internal) Edge Selection Pulse Generation OCL (Internal) Polarity Selection Pulse Generation
23
Automatic Polarity
BLK (External)
24
BLK Polarity Selection R9b0
OCL Source Selection R8b7
16/22
TDA9209
12 - INTERNAL SCHEMATICS
Figure 13.
VCC5 VCCA 30k 7 (8V) LOGIC PART
Figure 16.
IN (Pins 1-3-5)
HIGH IMPEDANCE
GNDA
GNDA 6
Figure 14.
Figure 17.
VCCA
V CCA 1k ABL 2
200k AV 8
GNDA
GNDA
Figure 15.
VCCA
Figure 18.
VCCA OSD-FBLK-HS-BLK Pins 9-10-11 12-23-24 GNDA GNDA GNDL
GNDL
4
17/22
2
TDA9209
Figure 19. Figure 22.
VCCP 20 OUT Pins 17-19-21
HSYNC 23
(20V)
GNDA
GNDL
GNDA
GNDP
Figure 20.
30k SCL 13 4pF GNDA (8V) GNDL
Figure 23.
VCCP
GNDP
30k SCA 14 4pF GNDA GNDL
18
GNDA
Figure 21.
V CCA
CO/FB Pins 15-16-22 GNDA
18/22
TDA9209
Figure 24. TDA9209/9207 - TDA9533/9530 Demonstration Board: Silk Screen and Trace (scale 1:1)
19/22
Bi n
Rin
Gin
VSYNC HSYNC
1
2
3 4 5 6 7 8 9 10 11 12
20/22
B C D E
A
5V
5-8V 5V Jump J1 R3 R4 BLANK 2R7 2R7 2R7 R9 HSYNC I2C C1(1) R8 100pF C3(1) BLK 100nF U2 R13 14 C_OFF3 GND3 IN3 VCC IN2 GND2 GNDS OUT2 C_OFF2 VDD IN1 GND1 C_OFF1 OUT1 TDA9530/33 14 C14(1) 100nF 100nF 110V C18 100pF 100pF J4 GND_CRT S6 Jump J6 J7 S7 Jump 5V GND R29 10 R 8 J5 G2 7 C20 GND 1 OSD Supply G1 5 C25 G1 R28 150R 10nF / 400V
1
TDA9209
5V S1 2K7 110V SDA SCL
4
R1 2K7
R2
5V R5 R6 S2 2R7 100R 33R C24 4.7uF / 150V D1(2) FDH400 R19(2) 110V Jump R7 1 2 3 4
4
D2 33R 100R
1N4148 C4
100nF
R12 C2(1) 100nF U1 IN1 ABL IN2 GNDL IN3 9 7 5 Rout 3 1 D9(2) FDH400 Bout R26 120R / 0.5W L3 .33uH R27 100nF/250V 100nF GNDA VCCA VDDL/AV OSD1 OSD2 OSD3 FBLK C16 C17 KB 100nF/250V 12 11 B J3 10 H1 9 H2 HEAT F1(2) C19 10nF / 400V SCL 13 SCL SDA SDA C15(1) CUT3 15 CUT2 16 R24 2 100R OUT3 17 R20 4 15R/50R GNDP 18 R18 6 100R OUT2 19 8 VCCP 20 C8(1) 10 C12(1) C10(1) C11 D6(2) 47uF FDH400 R21 120R / 0.5W L2 .33uH R22 110V 100nF R16 15R/50R 11 OUT1 21 R14 12 15R/50R 13 CUT1 22 100R OUT3 15 Gout Hs/BPCP 23 C5(1) 100pF R10 120R / 0.5W 24 1 2 R15 3 33R
D3
75R
1N4148
transient response optimisation
L1 .33uH R11 150R / 0.5W
5V
100nF
C7
D4
12V
110V
1N4148 5 C6(1) 6 7 8 R23 9 10 S3 Jump 12 S4 Jump 11 33R 100nF
C9(1) 4
100nF
R17
D5
75R
5V
1N4148
3
3
D7
150R / 0.5W
1N4148
100nF
C13
R25
D8
75R
1N4148
AV
150R / 0.5W
OSD1
TDA9207/09
S5 Jump
OSD2
2
OSD3
2
FBLK
KR
G2
F2(2)
Figure 25. TDA9209/9207 - TDA9533/9530 Demonstration Board Schematic
12 11 10 9 8 7 6 5 4 3 2 1 AV OSD1 OSD2 OSD3 FBLK SDA SCL HSYNC HFly VFly
VFly HFly VSYNC 5-8V 5V HSYNC BLANK HEAT G1 110V 12V 1 2 3 4 5 6 7 8 9 10 11 12
G 6 KG
10nF / 2KV
F3(2)
J2
Video
5V
5-8V
12V
1
C21 C22 47uF 47uF C23
Notes: 1: All capacitorsfollowed by (1) are decoupling capacitors which must be connected as close as possible to the device 2: The purpose of all components followed by (2) is to ensure a good protection against overvoltage(arcing protection)
B C
47uF
Title
CRT4 TDA9207/09+TDA9533
Size A4 Date:
D
DocumentNumber Monday,January17, 2000 Sheet 1
E
Rev
of
1
A
TDA9209
PACKAGE MECHANICAL DATA
24 Pins -- Plastic Dip (Shrink))
E E1
A1
A2
Stand-off B B1 e e1 e2
L c D E 24 13 F
.015 0,38 Gage Plane
1
12 e3
SDIP24
A
e2
Millimeters Dimensions Min. A A1 A2 B B1 C D E E1 e e1 e2 e3 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10 6.40 1.778 7.62 10.92 1.52 3.30 0.46 1.02 0.25 22.86 4.57 0.56 1.14 0.38 23.11 8.64 6.86 Typ. Max. 5.08 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240 Min.
Inches Typ. Max. 0.20 0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30 0.430 0.060 0.180 0.0220 0.045 0.0150 0.910 0.340 0.270
21/22
TDA9209
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com
22/22
3

▲Up To Search▲

Price & Availability of TDA9209

	To Download TDA9209 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .