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| DISCRETE SEMICONDUCTORS DATA SHEET BF998; BF998R Silicon N-channel dual-gate MOS-FETs Product specification Supersedes data of April 1991 File under Discrete Semiconductors, SC07 1996 Aug 01 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs FEATURES * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz. APPLICATIONS * VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment. Top view handbook, halfpage BF998; BF998R 4 3 g2 g1 d 1 2 s,b MAM039 DESCRIPTION Depletion type field effect transistor in a plastic microminiature SOT143 or SOT143R package with source and substrate interconnected. The transistors are protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. Marking code: MOp. Fig.1 Simplified outline (SOT143) and symbol; BF998. handbook, halfpage d 4 g2 g1 3 PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION Top view 2 1 s,b MAM040 Marking code: MOp. Fig.2 Simplified outline (SOT143R) and symbol; BF998R. QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-s Crs F Tj drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure operating junction temperature f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS - - - 24 2.1 25 1 - TYP. MAX. 12 30 200 - - - - 150 V mA mW mS pF fF dB C UNIT 1996 Aug 01 2 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Ptot Tstg Tj Notes 1. Device mounted on a ceramic substrate, 8 mm x 10 mm x 0.7 mm. 2. Device mounted on a printed-circuit board. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation; BF998 up to Tamb = 60 C; see Fig.3; note 1 up to Tamb = 50 C; see Fig.3; note 2 total power dissipation; BF998R up to Tamb = 50 C; see Fig.4; note 1 storage temperature operating junction temperature CONDITIONS - - - - - - - -65 - BF998; BF998R MIN. MAX. 12 30 10 10 200 200 200 +150 150 V UNIT mA mA mA mW mW mW C C MLA198 MGA002 handbook, halfpage handbook, halfpage 200 Ptot max (mW) (2) (1) 200 Ptot max (mW) 100 100 0 0 100 Tamb (o C) 200 0 0 100 Tamb (C) 200 (1) Ceramic substrate. (2) Printed-circuit board. Fig.3 Power derating curves; BF998. Fig.4 Power derating curve; BF998R. 1996 Aug 01 3 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-a Notes 1. Device mounted on a ceramic substrate, 8 mm x 10 mm x 0.7 mm. 2. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VG2-S = VDS = 0; IG1-SS = 10 mA VG1-S = VDS = 0; IG2-SS = 10 mA VG2-S = 4 V; VDS = 8 V; ID = 20 A VG1-S = 0; VDS = 8 V; ID = 20 A PARAMETER thermal resistance from junction to ambient in free air; BF998 BF998; BF998R CONDITIONS note 1 note 2 VALUE 460 500 500 UNIT K/W K/W K/W thermal resistance from junction to ambient in free air; BF998R note 1 MIN. 6 6 - - 2 - - MAX. 20 20 2.0 1.5 18 50 50 UNIT V V V V mA nA nA V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage -V(P)G1-S -V(P)G2-S IDSS IG1-SS IG2-SS Note 1. Measured under pulse condition. gate 1-source cut-off voltage gate 2-source cut-off voltage drain-source current gate 1 cut-off current gate 2 cut-off current VG2-S = 4 V; VDS = 8 V; VG1-S = 0; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 5 V DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VDS = 8 V; VG2-S = 4 V; ID = 10 mA. SYMBOL yfs Cig1-s Cig2-s Cos Crs F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance reverse transfer capacitance noise figure f = 1 kHz f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BSopt f = 800 MHz; GS = 3.3 mS; BS = BSopt CONDITIONS MIN. 21 - - - - - - TYP. 24 2.1 1.2 1.05 25 0.6 1.0 MAX. - 2.5 - - - - - UNIT mS pF pF pF fF dB dB 1996 Aug 01 4 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R handbook, halfpage I 24 MGE813 D (mA) handbook, halfpage I 24 MGE815 VG1-S = 0.4 V 0.3 V 20 D (mA) 20 3V VG2-S = 4 V 2V 1V 16 0.2 V 0.1 V 0V 16 12 12 8 -0.1 V -0.2 V 8 0V 4 0 0 2 4 6 8 VDS (V) -0.3 V -0.4 V -0.5 V 10 4 0 -1 0 VG1 (V) 1 VG2-S = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C. Fig.5 Output characteristics; typical values. Fig.6 Transfer characteristics; typical values. handbook, halfpage I 24 MGE814 MGE811 D (mA) 20 handbook, halfpage 30 max typ |yfs| (mS) 24 4V 3V 2V 1V 16 18 12 min 12 8 6 VG2-S = 0 V 0 0 4 8 12 16 ID (mA) 20 0.5 V 4 0 -1600 -1200 -800 -400 0 VG1 (mV) 400 VDS = 8 V; VG2-S = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C. Fig.7 Drain current as a function of gate 1 voltage; typical values. Fig.8 Forward transfer admittance as a function of drain current; typical values. 1996 Aug 01 5 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGE812 MGE810 handbook, halfpage 30 |yfs| (mS) 24 VG2-S = 4 V handbook, halfpage 1.5 Cos (pF) 1.4 3V 18 1.3 12 2V 1.2 12 mA 6 1V 1.1 10 mA 8 mA 0V 0 -1 1.0 0 VG1 (V) 1 4 6 8 10 12 VDS (V) 14 VDS = 8 V; Tamb = 25 C. VG2-S = 4 V; f = 1 MHz; Tamb = 25 C. Fig.9 Forward transfer admittance as a function of gate 1 voltage; typical values. Fig.10 Output capacitance as a function of drain-source voltage; typical values. handbook, halfpage 2.3 Cis 2.1 MGE809 MBH479 handbook, halfpage 2.4 (pF) Cis (pF) 2.3 1.9 2.2 1.7 2.1 1.5 1.3 -2.4 -1.6 -0.8 2.0 0 0.8 VG1-S (V) 6 4 2 0 -2 VG2-S (V) VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C. VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C. Fig.11 Gate 1 input capacitance as a function of gate 1-source voltage; typical values. Fig.12 Gate 1 input capacitance as a function of gate 2-source voltage; typical values. 1996 Aug 01 6 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGC466 10 y is (mS) b is 1 10 3 y rs (S) 10 2 MGC467 10 3 rs (deg) rs y rs 10 2 10 1 g is 10 10 10 2 10 102 f (MHz) 10 3 1 10 1 102 f (MHz) 10 3 VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C. VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C. Fig.13 Input admittance as a function of the frequency; typical values. Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. 10 2 MGC468 10 2 MGC469 10 yos (mS) 1 y fs (mS) y fs fs (deg) bos 10 10 fs 10 1 gos 1 10 1 102 f (MHz) 10 3 10 2 10 102 f (MHz) 10 3 VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C. VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C. Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. Fig.16 Output admittance as a function of the frequency; typical values. 1996 Aug 01 7 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R handbook, full pagewidth VDD 47 F Vagc 1 nF 1 nF 47 k 1 nF 50 input C1 5.5 pF 1 nF 15 pF L1 140 k VDD 1 nF D1 BB405 330 k D2 BB405 330 k 360 10 pF 1.8 k L2 1 nF 20 H 1 nF 50 output 100 k Vtun input 1 nF Vtun output 1 nF MGE802 VDD = 12 V; GS = 2 mS; GL = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS. Fig.17 Gain control test circuit at f = 200 MHz. 1996 Aug 01 8 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R handbook, full pagewidth VDD Vagc 1 nF VDD 1 nF 140 k 100 k 1 nF 270 k L1 50 input 1 nF L2 1 nF C1 2 to 18 pF C2 0.5 to 3.5 pF 1.8 k 360 1 nF L3 L4 1 nF 50 output C3 0.5 to 3.5 pF C4 4 to 40 pF MGE801 VDD VDD = 12 V; GS = 3.3 mS; GL = 1 mS. L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane. Fig.18 Gain control test circuit at f = 800 MHz. 1996 Aug 01 9 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGE808 MGE807 handbook, halfpage 0 Gtr (dB) handbook, halfpage 0 Gtr (dB) -10 -10 IDSS = max typ min -20 -20 -30 -30 -40 IDSS = max typ min 0 2 4 6 8 Vagc (V) 10 -40 -50 -50 0 2 4 6 8 Vagc (V) 10 VDD = 12 V; f = 200 MHz; Tamb = 25 C. VDD = 12 V; f = 800 MHz; Tamb = 25 C. Fig.19 Automatic gain control characteristics measured in circuit of Fig.17. Fig.20 Automatic gain control characteristics measured in circuit of Fig.18. 1996 Aug 01 10 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs PACKAGE OUTLINES BF998; BF998R handbook, full pagewidth 0.75 0.60 0.150 0.090 4 0.1 max 10 max o 3.0 2.8 1.9 3 B A 0.2 M A B 10 max o 1.4 1.2 2.5 max 1 1.1 max o 2 0.1 M A B 30 max 0.88 0 0.1 1.7 0.48 0 0.1 MBC845 TOP VIEW Dimensions in mm. Fig.21 SOT143. handbook, full pagewidth 0.40 0.25 0.150 0.090 3 0.1 max 10 max o 3.0 2.8 1.9 4 B A 0.2 M A 10 max o 1.4 1.2 2.5 max 2 1.1 max 0.48 0.38 1.7 0.1 M B 1 0.88 0.78 30 max o MBC844 TOP VIEW Dimensions in mm. Fig.22 SOT143R. 1996 Aug 01 11 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values BF998; BF998R This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Aug 01 12 |
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