View HV9100_163328.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HV9100 HV9102 HV9103 High-Voltage Switchmode Controllers with MOSFET
Ordering Information
+VIN Min 10V 10V 10V Max 70V 120V 120V Feedback Voltage 1.0% 1.0% 1.0% Max Duty Cycle 49% 49% 99% MOSFET Switch BVDSS 150V 200V 200V RDS (ON) 5.0 7.0 7.0 Package Options 14 Pin Plastic DIP 20 Pin Plastic PLCC HV9100P HV9102P HV9103P HV9100PJ HV9102PJ HV9103PJ
Standard temperature range for all parts is industrial (-40 to +85C).
Features
10 to 120V input range 200V, 7.0 output MOSFET Current-Mode Control High Efficiency Up to 1MHz Internal Oscillator Internal Start-up Circuit
General Description
The Supertex HV9100 through HV9103 are a series of BiCMOS/ DMOS single-output, pulse width modulator ICs intended for use in high-speed high-efficiency switchmode power supplies. They provide all the functions necessary to implement a single-switch current-mode PWM, in any topology, with a minimum of external parts. Utilization of Supertex proprietary BiCMOS/DMOS technology results in a device with one tenth of the operating power of conventional bipolar PWM ICs, which can operate at more than twice their switching frequency. Dynamic range for regulation is also increased, to approximately 8 times that of similar bipolar parts. They start directly from any DC input voltage between 10 and 70VDC for the HV9100 or 10 to 120VDC for the HV9102 and HV9103, requiring no external power resistor. The output stage for the HV9100 is a 150V, 5.0 ohm MOSFET and for the HV9102 and HV9103 is a 200V, 7.0 ohm MOSFET. The clock frequency is set with a single external resistor. Accessory functions are included to permit fast remote shutdown (latching or nonlatching), and undervoltage shutdown.
Applications
DC/DC Converters Distributed Power Systems ISDN Equipment PBX Systems Modems
Absolute Maximum Ratings
+VIN, Input Voltage VDS VDD, Logic Voltage 120V 200V 15.0V
Input Voltage Logic, Linear, FB and Sense -0.3V to VDD+0.3V ID (Peak) Storage Temperature Power Dissipation, Plastic DIP Power Dissipation, PLCC 2.5A -65C to 150C 750mW 1400mW For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24.
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1
HV9100/HV9102/HV9103
Electrical Characteristics
(VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390K, ROSC = 330K,TA = 25C, unless otherwise specified)
Symbol Parameters Min Typ Max Unit Conditions
Reference
VREF Output Voltage HV9100/02/03 HV9102/03 ZOUT ISHORT VREF Output Impedance1 Short Circuit Current Change in VREF with Temperature 3.92 3.86 15 4.00 4.00 30 100 0.25 4.08 4.14 45 250 V V K A mV/C VREF = -VIN RL = 10M IN = VIN, RL = 10M TA = -55C to 125C
Oscillator
fMAX fOSC Oscillator Frequency Initial Accuracy2 1.0 80 160 Voltage Stability Temperature Coefficient 170 3.0 100 200 120 240 15 % ppm/C MHz KHz ROSC = 0 ROSC = 330K ROSC = 150K 9.5V < VDD < 13.5V
PWM
DMAX Maximum Duty Cycle HV9100/02 HV9103 Deadtime DMIN Minimum Duty Cycle Minimum Pulse Width Before Pulse Drops Out 1 110 HV9103 49.0 99.0 49.4 99.4 100 0 175 49.6 99.6 nsec % nsec %
Error Amplifier
VFB IIN VOS AVOL gbw ZOUT ISOURCE ISINK PSRR Feedback Voltage Input Bias Current Input Offset Voltage Open Loop Voltage Unity Gain Output Gain1 60 1.0 HV9100/02/03 3.96 4.00 25 nulled at trim 80 1.3 See Fig. 2 -2.0 0.12 0.15 See Fig. 1 -1.4 4.04 500 V nA mV dB MHz mA mA VFB = 3.4V VFB = 4.5V VFB Shorted to Comp VFB = 4.0V Except 9101
Bandwidth1
Impedance1
Output Source Current Output Sink Current Power Supply Rejection
Current Limit
VSOURCE Threshold Voltage td Delay to Output1
Notes: 1. Guaranteed by design. Not subject to production test. 2. Stray capacitance on OSC In pin 5pF.
1.0
1.2
1.4 150
V ns
VFB = 0V, RL = 100 VSOURCE = 1.5V, RL = 100
2
HV9100/HV9102/HV9103
Electrical Characteristics
Symbol Parameters
(Continued)
Min Typ Max Unit Conditions
(VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390K, ROSC = 330K,TA = 25C, unless otherwise specified)
Pre-Regulator/Startup
+VIN Allowable Input Voltage HV9100 HV9102/03 Input Leakage Current VTH VLOCK VDD Pre-regulator Turn-off Threshold Voltage Undervoltage Lockout 7.8 7.0 8.6 8.1 70 120 10 9.4 8.9 A V V VDD > 9.4V IPREREG = 10A RL = 100 from Drain to VDD V IIN = 10A
Supply
IDD IBIAS VDD Supply Current 0.60 0.55 Bias Current Operating Range 9.0 20 13.5 1.0 mA mA A V Shutdown = -VIN
Logic
tSD tSW tRW tLW VIL VIH IIH IIL Shutdown Delay Time1 Shutdown Pulse RESET Pulse Width1 50 50 25 2.0 7.0 1.0 -25 5.0 -35 50 100 ns ns ns ns V V A A VIN = 10V VIN = 0V VSOURCE = -VIN
Width1 Width1
Latching Pulse
Input Low Voltage Input High Voltage Input High Current Input Low Current
MOSFET Switch
BVDSS Breakdown Voltage HV9100 HV9102/03 RDS(ON) IDSS CDS Drain-to-Source On-resistance HV9100 HV9102/03 150 200 3.5 5.0 7.0 10 35 A pF VSOURCE = Shutdown = 0V, VDRAIN = 100V VDS = 25V, Shutdown = 0V V VSOURCE = Shutdown = 0V, ID = 100A, TA = -55C to 125C VSOURCE = 0V, ID = 100mA
OFF State Drain Leakage Current Drain Capacitance
Note: 1. Guaranteed by design. Not subject to production test.
Truth Table
Shutdown H H L L LH Reset H HL H L L Output Normal Operation Normal Operation, No Change Off, Not Latched Off, Latched Off, Latched, No Change
3
HV9100/HV9102/HV9103
Switching Waveforms
1.5V Source 0 td VDD Drain 0 90% VDD Drain 0 50% tR 10ns Shutdown 0 t SD 90% VDD 50% tF 10ns
t SW VDD Shutdown 50% 0 t LW VDD Reset 50% 0 t RW 50% 50% 50% tR, tF 10ns
Functional Block Diagram
FB 14 (20) COMP 13 (18) Discharge 9 (12) OSC OSC In Out 8 (11) 7 (10) OSC 2V 4V REF GEN + S + - 1 (2) Current Sources To Internal Circuits C/L Comparator - Current-mode Comparator T R Q 9103 V DD (5) 3 (8) 5 1.2V V DD - - + 8.1V 8.6V + Undervoltage Comparator Q R (17) 12 Reset (7) 4 (16) 11 -V IN Source Q 9100 9102 Drain
Error Amplifier -
10 (14) VREF
+
BIAS
VDD +VIN
6 (9) 2 (3) S
Shutdown
Pre-regulator/Startup
Pin numbers in parentheses are for PLCC pacage.
4
HV9100/HV9102/HV9103
Typical Performance Curves
Fig. 1
0 -10 -20 -30
PSRR - Error Amplifier and Reference
Fig. 3
80 70 60 50
Error Amplifier Open Loop Gain/Phase
180 120 60 0 -60 -120 -180
Gain (dB)
-40 -50 -60 -70 -80
10Hz 100Hz 1KHz 10KHz 100KHz 1MHz
30 20 10 0 -10 100Hz 1KHz 10KHz 100KHz 1MHz
Frequency
Fig. 2
106 105 104 103
Error Amplifier Output Impedance (Z0)
Fig. 4
1M
Output Switching Frequency vs. Oscillator Resistance
HV9103
fOUT (Hz)
()
102 10 1.0 0.1 .01
100Hz 1KHz 10KHz 100KHz 1MHz 10MHz
100k
HV9100, 9101, 9102
10k 10k
100 k
1M
ROSC ()
Test Circuits
Error Amp ZOUT
0.1V swept 10Hz - 1MHz
PSRR
+10V (VDD)
1.0V swept 100Hz - 2.2MHz 60.4K
-
100K1% 10.0V 100K1% 4.00V
- +
(FB) Reference GND (-VIN) 0.1F
+
V1
Tektronix P6021 (1 turn secondary)
V1
V2 40.2K
Reference 0.1F
V2
NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE 1mV before connecting transformer
5
Phase
(dB)
40
HV9100/HV9102/HV9103
Technical Description
Preregulator
The preregulator/startup circuit for the HV910x consists of a highvoltage N-channel depletion-mode DMOS transistor driven by an error amplifier to form a controlled current path between the VIN terminal and the VDD terminal. Maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source (generally the supply the chip is controlling) no current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external capacitor between VDD and VSS is generally required to store energy used by the chip during the time between shutoff of the high voltage path and the VDD supply's output rising enough to take over the powering of the chip. This capacitor generally also serves as the output filter capacitor for that output from the supply. 1F is generally sufficient to assure against double-starting. Capacitors as small as 0.1F can work when faster response from the VDD line is required. Whatever capacitor is chosen should have very good high frequency characteristics. Stacked polyester or ceramic capacitors work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off.
Reference
The reference consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier when connected in a gain of -1 configuration is as close to 4.000V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4V, the feedback voltage required for proper regulation will be 4V. A resistor of approximately 50K is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and NON-INVERTING input to the error amplifier). This allows overriding the internal reference with a lowimpedance voltage source 6V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. In general, because the reference voltage of the Supertex HV910x is not noisy, as some previous devices have been, overriding the reference should seldom be necessary. Because the reference is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1F.
Error Amplifier
The error amplifier is a true low-power differential input operational amplifier intended for around-the-amplifier compensation. It is of mixed CMOS-bipolar construction: a PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable.
Bias Circuit
An external bias resistor, connected between the bias pin and VSS is required to set currents in a series of current mirrors used by the analog sections of the chip. Nominal external bias current requirement is 15 to 20A, which can be set by a 390K to 510K resistor if a 10V VDD is used, or a 510K to 680K resistor if a 12V VDD is used. A precision resistor is NOT required; 5% is fine. For extremely low power operation, the value of bias current can be reduced to as low as 5A by further increases in the value of the bias resistor. This will reduce quiescent current by about a third, reduce bandwidth of the error amp by about half, and slow the current sense comparator by about 30%.
Current Sense Comparators
The HV910x uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction.
Clock Oscillator
The clock oscillator of the HV910x consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle versions, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out pins is required to set oscillator frequency (see Fig. 4). For the 50% maximum duty cycle versions the `Discharge' pin is internally connected to GND. For the 99% duty cycle version, `Discharge' can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One difference exists between the Supertex HV910x and competitive parts. The oscillator of the HV910x is shut off when a shutoff command is received. This saves about 150A of quiescent current, which aids in situations where an absolute minimum of quiescent power dissipation is required.
Remote Shutdown
The shutdown and reset pins can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used, they should be left open, or connected to VDD.
Main Switch
The main switch is a normal N-channel power MOSFET. Unlike the situation with competitive devices, the body diode can be used if desired without destroying the chip.
6
HV9100/HV9102/HV9103
Pinout
Shutdown COMP Reset VREF
14
18
17
16
BIAS +VIN Drain Source -VIN VDD OSC Out
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Feedback COMP Reset Shutdown VREF Discharge OSC In NC BIAS +VIN
1
NC Feedback
NC
15
19
13
NC Discharge OSC In OSC Out VDD
20
12
*
11
2
10
3
9
top view 14-pin DIP
4 5 6 7 8
Drain
top view 20-pin PJ Package
Source
-VIN
NC
NC
11/12/01
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
7
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

▲Up To Search▲

Price & Availability of HV9100

	To Download HV9100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .