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CMOS SyncFIFOTM 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
Integrated Device Technology, Inc.
IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240
FEATURES:
* * * * * * * * * * * * * * * * * * 64 x 8-bit organization (IDT72420) 256 x 8-bit organization (IDT72200) 512 x 8-bit organization (IDT72210) 1024 x 8-bit organization (IDT72220) 2048 x 8-bit organization (IDT72230) 4096 x 8-bit organization (IDT72240) 12 ns read/write cycle time (IDT72420/72200/72210) 15 ns read/write cycle time (IDT72220/72230/72240) Read and write clocks can be asynchronous or coincidental Dual-Ported zero fall-through time architecture Empty and Full flags signal FIFO status Almost-empty and almost-full flags set to Empty+7 and Full-7, respectively Output enable puts output data bus in high-impedance state Produced with advanced submicron CMOS technology Available in 28-pin 300 mil plastic DIP and 300 mil ceramic DIP For surface mount product please see the IDT72421/ 72201/72211/72221/72231/72241 data sheet Military product compliant to MIL-STD-883, Class B Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240 SyncFIFOTM are very high-speed, low-power First-In, FirstOut (FIFO) memories with clocked read and write controls. The IDT72420/72200/72210/72220/72230/72240 have a 64, 256, 512, 1024, 2048, and 4096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a write enable pin (WEN). Data is written into the Synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and a read enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output. These Synchronous FIFOs have two end-point flags, Empty (EF) and Full (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided for improved system control. The partial ( AE) flags are set to Empty+7 and Full-7 for AE and AF respectively. The IDT72420/72200/72210/72220/72230/72240 are fabricated using IDT's high-speed submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0 - D7
WEN
* INPUT REGISTER FLAG LOGIC * * RAM ARRAY 64 x 8 256 x 8 512 x 8 * *
* WRITE CONTROL LOGIC
EF AE AF FF
WRITE POINTER
READ POINTER
READ CONTROL LOGIC
OUTPUT REGISTER
*
RESET LOGIC RCLK
RS
OE
Q0 - Q7
REN
2680 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
NOVEMBER 1996
DSC-2680/6
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DIP TOP VIEW P28-2 C28-1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D5 D6 D7
RS WEN
WCLK VCC Q7 Q6 Q5 Q4 Q3 Q2 Q1
2680 drw 02
AF AE
GND RCLK
REN OE EF FF
Q0
PIN DESCRIPTIONS
Symbol D0 - D7 Name Data Inputs Reset I/O I I Description Data inputs for a 8-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up. Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written into the FIFO if the FF is LOW. Data outputs for a 8-bit bus. Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK. When AF is LOW, the FIFO is almost full based on the offset Full-7. WCLK.
RS
WCLK
Write Clock Write Enable Data Outputs Read Clock Read Enable Output Enable Empty Flag Almost-Empty Flag Almost-Full Flag Full Flag Power Ground
I I O I I I O O O O
WEN
Q0 - Q7 RCLK
REN OE EF AE AF FF
VCC GND
AF is synchronized to
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. One +5 volt power supply pin. One 0 volt ground pin.
2680 tbl 01
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Commercial Military -0.5 to + 7.0 Unit V Terminal Voltage -0.5 to + 7.0 with Respect to GND Operating 0 to + 70 Temperature Temperature -55 to + 125 Under Bias Storage -55 to + 125 Temperature DC Output 50 Current
RECOMMENDED OPERATING CONDITIONS
Symbol VCCM VCCC GND VIH VIH VIL Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Military Input Low Voltage Commercial & Military Min. 4.5 4.5 0 2.0 2.2 -- Typ. 5.0 5.0 0 -- -- -- Max. 5.5 5.5 0 -- -- 0.8 Unit V V V V V V
2680 tbl 03 2680 tbl 02
TA TBIAS TSTG IOUT
NOTE:
-55 to + 125 -65 to + 135 -65 to + 135 50
C C C mA
CAPACITANCE (TA = +25C, f = 1.0 MHz)
Symbol CIN (2) Parameter Input Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 10 Unit pF pF
2680 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
COUT(1, 2) Output Capacitance
NOTES: 1. With output deselected. (OE = HIGH) 2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
IDT72420 IDT72200 IDT72210 Commercial tCLK = 12, 15, 20, 25, 35, 50 ns Min. Typ. Max. -1 -10 2.4 -- -- -- -- -- -- -- 1 10 -- 0.4 80 IDT72420 IDT72200 IDT72210 Military tCLK = 20, 25,35, 50 ns Min. Typ. Max. -10 -10 2.4 -- -- -- -- -- -- -- 10 10 -- 0.4 100
Symbol ILI(1) ILO
(2)
Parameter Input Leakage Current (any input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current
Units A A V V mA
2680 tbl 05
VOH VOL ICC1(3)
Symbol ILI(1) ILO
(2)
Parameter Input Leakage Current (any input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current
IDT72220 IDT72230 IDT72240 Commercial tCLK = 15, 20, 25, 35, 50 ns Min. Typ. Max. -1 -10 2.4 -- -- -- -- -- -- -- 1 10 -- 0.4 80
IDT72220 IDT72230 IDT72240 Military tCLK = 25, 35, 50 ns Min. Typ. Max. -10 -10 2.4 -- -- -- -- -- -- -- 10 10 -- 0.4 100
Units A A V V mA
2680 tbl 06
VOH VOL ICC1(4)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3 & 4. Measurements are made with outputs unloaded. Tested at fCLK = 20 MHZ. (3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA (4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA fCLK = 1 / tCLK CL = external capacitive load (30 pF typical)
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C; Military: VCC = 5V 10%, TA = -55C to +125C)
Commercial Comm. & Mil. 72200L12 72200L15 72200L20 72200L25 72210L12 72210L15 72210L20 72210L25 72420L12 72420L15 72420L20 72420L25 Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tAF tAE Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z(2) Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Write Clock to Almost-Full Flag Read Clock to Almost-Empty Flag -- 83.3 2 12 5 5 3 0.5 3 0.5 12 12 12 -- 0 3 3 -- -- -- -- 5 22 8 -- -- -- -- -- -- -- -- -- -- 12 -- 7 7 8 8 8 8 -- -- -- 66.7 2 15 6 6 4 1 4 1 15 15 15 -- 0 3 3 -- -- -- -- 6 28 10 -- -- -- -- -- -- -- -- -- -- 15 -- 8 8 10 10 10 10 -- -- -- 2 20 8 8 5 1 5 1 20 20 20 -- 0 3 3 -- -- -- -- 8 35 50 12 -- -- -- -- -- -- -- -- -- -- 20 -- 10 10 12 12 12 12 -- -- -- 3 25 10 10 6 1 6 1 25 25 25 -- 0 3 3 -- -- -- -- 10 40 40 15 -- -- -- -- -- -- -- -- -- -- 25 -- 13 13 15 15 15 15 -- -- Comm. 72200L35 72210L35 72420L35 -- 28.6 3 35 14 14 8 2 8 2 35 35 35 -- 0 3 3 -- -- -- -- 12 42 20 -- -- -- -- -- -- -- -- -- -- 35 -- 15 15 20 20 20 20 -- -- Comm/Mil 72200L50 72210L50 72420L50 Min.Max. Unit -- 20 3 25 50 -- 20 -- 20 -- 10 -- 2 2 -- -- 10 -- 50 -- 50 -- 50 -- -- 50 0 3 3 -- 28 28 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-- 30 -- 30 -- 30 -- 30 15 -- 45 --
tSKEW1 Skew time between Read Clock & Write Clock for Empty Flag & Full Flag tSKEW2 Skew time between Read Clock & Write Clock for Almost-Empty Flag & Almost-Full Flag
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
2680 tbl 07
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C; Military: VCC = 5V 10%, TA = -55C to +125C)
Commercial 72220L12 72220L15 72230L12 72230L15 72240L12 72240L15 Min. Max. Min. Max. -- 2 12 5 5 3 .5 3 .5 12 12 12 -- 0 3 3 -- -- -- -- 5 83.3 8 -- -- -- -- -- -- -- -- -- -- 12 -- 7 7 8 8 8 8 -- -- 2 15 6 6 4 1 4 1 15 15 15 -- 0 3 3 -- -- -- -- 6 66.7 10 -- -- -- -- -- -- -- -- -- -- 15 -- 8 8 10 10 10 10 -- Commercial & Military 72220L20 72220L25 72230L20 72230L25 72240L20 72240L25 Min. Max. Min. Max. -- 2 20 8 8 5 1 5 1 20 20 20 -- 0 3 3 -- -- -- -- 8 50 12 -- -- -- -- -- -- -- -- -- -- 20 -- 10 10 12 12 12 12 -- -- 3 25 10 10 6 1 6 1 25 25 25 -- 0 3 3 -- -- -- -- 10 40 15 -- -- -- -- -- -- -- -- -- -- 25 -- 13 13 15 15 15 15 -- Comm. 72220L35 72230L35 72240L35 Min. Max. -- 3 35 14 14 8 2 8 2 35 35 35 -- 0 3 3 -- -- -- -- 12 28.6 20 -- -- -- -- -- -- -- -- -- -- 35 -- 15 15 20 20 20 20 -- Comm./Mil. 72220L50 72230L50 72240L50 Min. Max. -- 3 50 20 20 10 2 10 2 50 50 50 -- 0 3 3 -- -- -- -- 15 20 25 -- -- -- -- -- -- -- -- -- -- 50 -- 23 23 30 30 30 30 --
Symbol Parameter fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tAF tAE Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z(2) Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Write Clock to Almost-Full Flag Read Clock to Almost-Empty Flag
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSKEW1 Skew time between Read Clock & Write Clock for Empty Flag & Full Flag tSKEW2 Skew time between Read Clock & Write Clock for Almost-Empty Flag & Almost-Full Flag
22
--
28
--
35
--
40
--
42
--
45
--
ns
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
2680 tbl 08
5V
1.1K
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
2680 tbl 09
D.U.T. 680 30pF*
2680 drw 03
or equivalent circuit
Figure 1. Output Load *Includes jig and scope capacitances.
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS: Data In (D0-D7) -- Data inputs for 8-bit wide data. CONTROLS: Reset (RS -- Reset is accomplished whenever the Reset RS) (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The Full Flag (FF) and Almost Full Flag (AF) will be reset to HIGH after tRSF. The Empty Flag (EF) and Almost Empty Flag (AE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros. Write Clock (WCLK) -- A write cycle is initiated on the LOWto-HIGH transition of the write clock (WCLK). Data set-up and hold times must be met in respect to the LOW-to-HIGH transition of the write clock (WCLK). The Full Flag (FF) and Almost Full Flag (AF) are synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coincident. Write Enable (WEN -- When Write Enable (WEN) is LOW, WEN) data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. When Write Enable (WEN) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable (WEN) is ignored when the FIFO is full. Read Clock (RCLK) -- Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK). The Empty Flag (EF) and Almost-Empty Flag (AE) are synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). The write and read clocks can be asynchronous or coincident. Read Enable (REN -- When Read Enable (REN) is LOW, REN) data is read from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK).
When Read Enable (REN) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. Read Enable (REN) is ignored when the FIFO is empty. Output Enable (OE -- When Output Enable (OE) is enabled OE) (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-impedance state. OUTPUTS: Full Flag (FF -- The Full Flag (FF) will go LOW, inhibiting FF) further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256 writes for the IDT72200, 512 writes for the IDT72210, 1024 writes for the IDT72220, 2048 writes for the IDT72230, and 4096 writes for the IDT72240. The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK). Empty Flag (EF -- The Empty Flag (EF) will go LOW, EF) inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Almost Full Flag (AF -- The Almost Full Flag (AF) will go AF) LOW when the FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the Almost Full Flag (AF) will go LOW after 57 writes for the IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1017 writes for the IDT72220, 2041 writes for the IDT72230 and 4089 writes for the IDT72240. The Almost Full Flag (AF) is synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). Almost Empty Flag (AE -- The Almost Empty Flag (AE) will AE) go LOW when the FIFO reaches the Almost-Empty condition. If no reads are performed after Reset (RS), the Almost Empty Flag (AE) will go HIGH after 8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240. The Almost Empty Flag (AE) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Data Outputs (Q0-Q7) -- Data outputs for a 8-bit wide data.
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 1: STATUS FLAGS
Number of Words in FIFO IDT72420 0 1 to 7 8 to 56 57 to 63 64 IDT72200 0 1 to 7 8 to 248 249 to 255 256 IDT72210 0 1 to 7 8 to 504 505 to 511 512 IDT72220 0 1 to 7 8 to 1016 1024 IDT72230 0 1 to 7 8 to 2040 2048 IDT72240 0 1 to 7 8 to 4088 4096
FF
H H H H L
AF
H H H L L
AE
L L H H H
EF
L H H H H
2680 tbl 10
1017 to 1023 2041 to 2047 4089 to 4095
tRS
RS
tRSS tRSR
REN
tRSS tRSR
WEN
tRSF
EF, AE
tRSF
FF, AF
tRSF Q0 - Q7
OE = 1 OE = 0
(1)
2680 drw 04
NOTE: 1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH WCLK tDS tDH tCLKL
D0 - D7 DATAIN VALID tENS tENH NO OPERATION tWFF tWFF
WEN
FF
tSKEW1
(1)
RCLK
REN
2680 drw 05
NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the curent clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 3. Write Cycle Timing
5.12
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH RCLK tENS tENH NO OPERATION tCLKL
REN
tREF
tREF
EF
tA Q0 - Q7 tOLZ tOHZ tOE VALID DATA
OE
tSKEW1(1)
WCLK
WEN
2680 drw 06
NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the curent clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 4. Read Cycle Timing
5.12
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK tDS
D0 - D7
D0 (first valid write)
D1
D2
D3
tENS
WEN
tSKEW1 RCLK tFRL (1)
EF
tREF
REN
tA Q0 - Q7 tOLZ tOE D0 tA D1
OE
NOTE: 1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundry (EF = LOW).
2680 drw 07
Figure 5. First Data Word Latency Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO WRITE WCLK tDS tSKEW1 D0 - D7 DATA WRITE
NO WRITE
tDS tSKEW1 DATA WRITE
tWFF
tWFF
tWFF
FF
WEN
RCLK tENH tENS tENS tENH
REN
OE
LOW
tA
tA
Q0 - Q7
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2680 drw 08
Figure 6. Full Flag Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK tDS tDS
D0 - D7 tENS
DATA WRITE 1 tENH tENS
DATA WRITE 2 tENH
WEN
tFRL (1) tSKEW1 RCLK tSKEW1 tFRL (1)
tREF
tREF
tREF
EF
REN
OE
LOW
tA Q0 - Q7 DATA IN OUTPUT REGISTER DATA READ
NOTE: 1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundry (EF = LOW).
2680 drw 09
Figure 7. Empty Flag Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKH
tCLKL (2) tENH
WCLK tENS
WEN
tAF
AF
Full - 8 words in FIFO
Full - 7 words in FIFO
tSKEW2 (1) RCLK tENS tENH
tAF
REN
2680 drw 10
NOTES: 1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the curent clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge. 2. If a write is performed on this rising edge of the write clock, there will be Full - 6 words in the FIFO when AF goes LOW. Figure 8. Almost Full Flag Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKH
tCLKL
WCLK tENS tENH
WEN
Empty+8
AE
Empty+7 (1) tSKEW2 tAE tAE (2) tENH
RCLK tENS
REN
2680 drw 11
NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the curent clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge. 2. If a read is performed on this rising edge of the read clock, there will be Empty - 6 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - A single IDT72420/ 72200/72210/72220/72230/72240 may be used when the application requirements are for 64/256/512/1024/2048/4096 words or less. See Figure 10.
RESET (RS)
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) IDT 72420/72200/ 72210/ 72220/ 72230/ 72240
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) DATA OUT (Q0- Q7) EMPTY FLAG (EF) ALMOST EMPTY(AE)
DATA IN (D0-D7) FULL FLAG (FF) ALMOST FULL (AF)
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Figure 10. Block Diagram of Single 64 x 8/256 x 8/512 x 8/1024 x 8/2048 x 8/4096 x 8 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may be increased simply by connecting the corresponding input control signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF) The partial status flags (AE and AF) can be detected from any one
device. Figure 11 demonstrates a 16-bit word width by using two IDT72420/72200/72210/72220/72230/72240s. Any word width can be attained by adding additional IDT72420/72200/ 72210/72220/72230/72240s.
RESET (RS)
RESET (RS)
DATA IN (D)
16
8
8 READ CLOCK (RCLK)
WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE (OE) ALMOST FULL (AF) FULL FLAG (FF) #1 FULL FLAG (FF) #2 IDT 72420/ 72200/ 72210/ 72220/ 72230/ 72240 IDT 72420/ 72200/ 72210/ 72220/ 72230/ 72240 ALMOST EMPTY (AE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 8 DATA OUT (Q) 16
8
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Figure 11. Block Diagram of 64 x 16/256 x 16/512 x 16/1024 x 16/2048 x 16/4096 x 16 Synchronous FIFO Used in a Width Expansion Configuration
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFOTM 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION - The IDT72420/72200/72210/72220/ 72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1024/2048/4096 words. Depth expansion is possible by using expansion logic to direct the flow of data. A typical application would have the
expansion logic alternate data accesses from one device to the next in a sequential manner. Please see the Application Note "DEPTH EXPANSION IDT'S SYNCHRONOUS FIFOs USING RING COUNTER APPROACH" for details of this configuration.
ORDERING INFORMATION
IDT XXXXX Device Type XX XX X Power Speed Package X Process / Temperature Range
BLANK Commercial (0C to +70C) B Military (-55C to +125C) Compliant to MIL-STD-883, Class B
TP TC
Plastic THINDIP Sidebraze THINDIP
12 15 20 25 35 50
Commercial Only Commercial Only Commercial and Military Commercial and Military Commercial Only Commercial and Military
Clock Cycle Time (tCLK) Speed in Nanoseconds
L 72420 72200 72210 72220 72230 72240
Low Power 64 x 8 Synchronous FIFO 256 x 8 Synchronous FIFO 512 x 8 Synchronous FIFO 1024 x 8 Synchronous FIFO 2048 x 8 Synchronous FIFO 4098 x 8 Synchronous FIFO
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