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* Organization: 1,048,576 words x 16 bits * High speed
- 45/50/60 ns RAS access time - 20/20/25 ns hyper page cycle time - 10/12/15 ns CAS access time
* 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh Read-modify-write
* TTL-compatible, three-state DQ * JEDEC standard package and pinout
- 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP 2
* Low power consumption
- Active: 740 mW max (AS4C1M16E5-60) - Standby: 5.5 mW max, CMOS DQ
* 5V power supply
* Industrial and commercial temperature available
* Extended data out
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62Vcc DQ1 DQ2 DQ3 '4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 V66 DQ16 DQ15 DQ14 DQ13 V66 DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 V66 V&& DQ1 DQ2 DQ DQ4 V&& DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11
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50 49 48 47 46 45 44 43 42 41 40 V66 DQ16 DQ15 DQ14 DQ13 V66 DQ12 DQ11 DQ10 DQ9 NC
Pin(s) A0 to A9 RAS DQ1 to DQ16 OE WE UCAS LCAS VCC VSS
Description Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Power Ground
NC NC WE RAS NC NC A0 A1 A2 A3 V&&
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 V66
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Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum hyper page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tAA tCAC tOEA tRC tHPC ICC1 ICC5 -45 45 23 10 12 75 20 155 2.0 -50 50 25 12 13 80 20 145 2.0 -60 60 30 15 15 100 25 135 2.0 Unit ns ns ns ns ns ns mA mA
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The AS4C1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words x 16 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia and router switch applications. The AS4C1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The AS4C1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access. Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and xCAS going high. Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using: * RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence. * Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data. * CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). * Normal read or write cycles refresh the row being accessed. The AS4C1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP 2 packages, respectively. The AS4C1M16E5 device operates with a single power supply of 5V 0.5V and provides TTL compatible inputs and outputs.
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Refresh controller
VCC GND RAS
RAS clock generator
Column decoder Sense amp
Data DQ buffers
DQ1 to DQ16
UCAS LCAS
CAS clock generator
WE
WE clock generator
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
Address buffers
OE Row decoder 1024 x 1024 x 16 Array (16,777,216)
Substrate bias generator
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Parameter Supply voltage Input voltage Ambient operating temperature Commercial Industrial Symbol VCC GND VIH VIL TA Min 4.5 0.0 2.4 -0.5 0 -40
Nominal 5.0 0.0 - - - -
Max 5.5 0.0 VCC 0.8 70 85
Unit V V V V C
V min -3.0V for pulse widths less than 5 ns. IL
Recommended operating conditions apply throughout this document unless otherwise specified.
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Parameter Input voltage Input voltage (DQs) Power supply voltage Storage temperature (plastic) Soldering temperature x time Power dissipation Short circuit output current Symbol Vin VDQ VCC TSTG TSOLDER PD Iout Min -1.0 -1.0 -1.0 -65 - - - Max +7.0 VCC + 0.5 +7.0 +150 260 x 10 1 50
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Unit V V V C C x sec W mA
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Addresses Operation Standby Word read Lower byte read Upper byte read Word (early) write Lower byte (early) write Upper byte (early) write Read write 1st cycle EDO read 2nd cycle Any cycle 1st cycle EDO write EDO read write RAS only refresh CBR refresh 2nd cycle 1st cycle 2nd cycle RAS H L L L L L L L L L L L L L L L H to L LCAS H to X L L H L L H L H to L H to L L to H H to L H to L H to L H to L H L UCAS H to X L H L L H L L H to L H to L L to H H to L H to L H to L H to L H L WE X H H H L L L H to L H H H L L H to L H to L X H OE X L L L X X X L to H L L L X X L to H L to H X X tR X ROW ROW ROW ROW ROW ROW ROW ROW n/a n/a ROW n/a ROW n/a ROW X tC X COL COL COL COL COL COL COL COL COL n/a COL COL COL COL n/a X DQ0 to DQ15 High-Z Data out Lower byte, Upper byte, Data out Lower byte, Data out, Upper byte Data in Lower byte, Data in, Upper byte, High-Z Lower byte, High-Z, Upper byte, Data in Data out, Data in Data out Data out Data out Data in Data in Data out, Data in Data out, Data in High Z High Z 3 1,2 2 2 2 1 1 1,2 1,2 Notes
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-45 Parameter Input leakage current Output leakage current Operating power supply current TTL standby power supply current Average power supply current, RAS refresh mode or CBR EDO page mode average power supply current CMOS standby power supply current Output voltage CAS before RAS refresh current Symbol Test conditions IIL IOL ICC1 ICC2 ICC3 0V Vin VCC (max) Pins not under test = 0V DOUT disabled, 0V Vout VCC (max) RAS, UCAS, LCAS, Address cycling; tRC=min RAS = UCAS = LCAS VIH, all other inputs at VIH or VIL RAS cycling, UCAS = LCAS VIH, tRC = min of RAS low after XCAS low. RAS = VIL, UCAS or LCAS, address cycling: tHPC = min RAS = UCAS = LCAS = VCC - 0.2V, F=0 IOUT = -5.0 mA IOUT = 4.2 mA RAS, UCAS or LCAS cycling, tRC = min Min -5 -5 - - Max +5 +5 155 2.0 -50 Min -5 -5 - - Max +5 +5 145 2.0 -60 Min -5 -5 - - Max Unit Notes +5 +5 135 2.0
A A
mA mA
4,5
-
145
-
135
-
125
mA
4
ICC4 ICC5 VOH VOL ICC6
-
130
-
120
-
110
mA
4, 5
- 2.4 - -
2.0 - 0.4 155
- 2.4 - -
2.0 - 0.4 145
- 2.4 - -
2.0 - 0.4 135
mA V V
mA
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-45 Symbol tRC tRP tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tT tREF tCP tRAL tASC tCAH Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS hold time RAS to CAS hold time CAS to RAS precharge time Row address setup time Row address hold time Transition time (rise and fall) Refresh period CAS precharge time Column address to RAS lead time Column address setup time Column address hold time Min 75 30 45 8 15 8 10 40 5 0 8 1 - 8 25 0 8 Max - - 10K 10K 35 25 - - - - - 50 16 - - - - Min 80 30 50 8 15 9 10 40 5 0 8 1 - 8 25 0 8 -50 Max - - 10K 10K 35 25 - - - - - 50 16 - - - - Min 100 40 60 10 15 10 10 50 5 0 10 1 - 10 30 0 10 -60 Max - - 10K 10K 43 30 - - - - - 50 16 - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 7,8 6 9 10 Notes
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-45 Symbol tRAC tCAC tAA tRCS tRCH tRRH Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Min - - - 0 0 0 Max 45 10 23 - - - Min - - - 0 0 0 -50 Max 50 12 25 - - - Min - - - 0 0 0 -60 Max 60 15 30 - - - Unit ns ns ns ns ns ns 12 12 Notes 9 9,16 10,16
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-45 Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Min 0 10 10 10 8 0 8 Max - - - - - - - Min 0 10 10 10 8 0 8 -50 Max - - - - - - - Min 0 10 10 10 10 0 10 -60 Max - - - - - - - Unit ns ns ns ns ns ns ns 15 15 Notes 14 14
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-45 Symbol tRWC tRWD tCWD tAWD Parameter Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Min 105 65 30 40 Max - - - - Min 113 67 32 42 -50 Max - - - - Min 135 77 35 47 -60 Max - - - - Unit ns ns ns ns 14 14 14 Notes
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-45 Symbol tCSR tCHR tRPC tCPT Parameter CAS setup time (CAS-before-RAS) CAS hold time (CAS-before-RAS) RAS precharge to CAS hold time CAS precharge time (CBR counter test) Min 5 8 0 10 Max - - - - Min 5 8 0 10 -50 Max - - - - Min 5 10 0 10 -60 Max - - - - Unit ns ns ns ns Notes 6 6
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-45 Symbol tCPWD tCPA tRASP tDOH tREZ tWEZ tOEZ tHPC tHPRWC tRHCP Parameter CAS precharge to WE delay time Access time from CAS precharge RAS pulse width Previous data hold time from CAS Output buffer turn off delay from RAS Output buffer turn off delay from WE Output buffer turn off delay from OE Hyper page mode cycle time Hyper page mode RMW cycle RAS hold time from CAS Min 45 - 45 5 0 0 0 20 47 30 Max - 28 100K - 13 13 13 - - - Min 45 - 50 5 0 0 0 20 47 30 -50 Max - 28 100K - 13 13 13 - - - Min 52 - 60 5 0 0 0 25 56 35 -60 Max - 35 100K - 15 15 15 - - - Unit ns ns ns ns ns ns ns ns ns ns 16 Notes
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-45 Symbol tCLZ tROH tOEA tOED tOEZ tOEH tOLZ tOFF Parameter CAS to output in Low Z RAS hold time referenced to OE OE access time OE to data delay Output buffer turnoff delay from OE OE command hold time OE to output in Low Z Output buffer turn-off time Min 0 8 - 13 0 10 0 0 Max - - 13 - 13 - - 13 Min 0 8 - 13 0 10 0 0 -50 Max - - 13 - 13 - - 13 Min 0 10 - 15 0 10 0 0 -60 Max - - 15 - 15 - - 15 Unit ns ns ns ns ns ns ns ns 11,13 11 Notes 11
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1 2 3 4 5 6 Write cycles may be byte write cycles (either LCAS or UCAS active). Read cycles may be byte read cycles (either LCAS or UCAS active). One CAS must be active (either LCAS or UCAS). ICC1, ICC3, ICC4, and ICC6 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load as described in AC test conditions below. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS tWS (min) and tWH tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min), tCWD tCWD (min) and tAWD tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. These characteristics apply to AS4C1M16E5 5V devices.
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- Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.4V and VIL = 0.8V - Input rise and fall times: 2 ns Dout 100 pF* +5V R1 = 828 R2 = 295
GND Figure A: Equivalent output load
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Rising input Falling input Undefined output/don't care
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tRC tRAS tRCD tRSH tRP
RAS
tCSH tCRP tASC tRCS tCAH tCAS
UCAS LCAS
tRAD tASR tRAH Column address tRRH tRCH tRAL
Address
Row address
WE
tROH tROH
tWEZ
OE
tRAC tAA tOEA tCAC tCLZ tREZ Data out tOLZ tOEZ tOFF (see note 11)
DQ
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tRAS tRC tRP
RAS
tRCD tCSH tCRP tCAS tRPC tRSH tCRP
UCAS
tCRP
LCAS
tRAH tRAD tASR tASC Row tRCS Column tRCH tRRH tROH tRAL tCAH
Address
WE
tWEZ
OE
tRAC tAA tCAC tCLZ tOFF Data out tOLZ tOEA tOEZ tREZ
Upper DQ Lower DQ
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tRAS tRC tRP
RAS
tRCD tCSH tCRP tCAS tRPC tASC tRAL tCAH Row tRCS Column tRCH tRRH tROH tWEZ tRSH tCRP
LCAS
tCRP
UCAS
tRAH tRAD tASR
Address WE OE Upper DQ
tRAC tAA
tOLZ
tOEA tOEZ tCAC
tREZ
tCLZ
tOFF Data out
Lower DQ
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tRC tRAS tRP
RAS
tCSH tRSH tCRP tRCD tRAD tASC tASR tRAH tCAH Column address tCWL tRWL tWP tWCS tWCH tCAS tRAL
UCAS, LCAS
Address
Row address
WE
OE
tDS tDH Data in
DQ
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tRC tRAS tRP
RAS
tASR tRAH tRAD tRAL Column address tASC tRCD tCSH tCRP tCAS tRPC tCWL tWCS tWCH tRWL tWP tCRP tCAH tRSH Row address
Address
UCAS
tCRP
LCAS
WE OE
tDS tDH Data in
Upper DQ Lower DQ
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tRAS tRC tRP
RAS
tRAD tASR tRAH Column address tRPC tASC tRCD tCSH tCRP tRSH tRWL tCWL tWCS tWCH tWP tCRP tCAH tCAS tRAL
Address UCAS
Row address tCRP
LCAS
WE OE Upper DQ
tDS tDH Data in
Lower DQ
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tCSH tRSH tCRP tRCD tCAS tRAL tRAD tRAH tASC tCAH Column address tRWL tCWL tWP
UCAS, LCAS
tASR
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Row address
WE
tOEH
OE
tOED tDS tDH
DQ
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tRAD tASR tRAH Row address Column address tCSH tRCD tCRP tASC tRSH tCAH tCAS tCRP tRAL
Address
UCAS
tCRP tRPC tCWL tRWL tWP
LCAS
WE
tOEH
OE
tDS tDH Data in tOED
Upper DQ Lower DQ
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tRAD tASR tRAH tRAL Column address tRCD tCSH tCRP tACS tCRP tRSH tRPC tCWL tRWL tWP tCRP tCAH tCAS
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Row address
LCAS UCAS
WE
tOEH
OE Upper DQ
tDS tDH Data in
Lower DQ
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tRWC tRAS tRP tCAS tCRP tRCD tCSH tRSH
RAS
UCAS LCAS
tRAD tASR tRAH Row address
tAR tRAL tASC tCAH Column address tRWD tAWD tRCS tCWD tOEA tOEZ tOED tCWL tWP tRWL
Address
WE OE
tRAC
tAA tCAC tCLZ tDS tDH Data in
DQ
tOLZ
Data out
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tRWC tRAS tRP
RAS
tCSH tRCD tCRP tCRP tCAS tRSH tCRP tRPC tACS tRAH
UCAS LCAS
tASR tRAD
tRAL tCAH tCWL tRWL tCWD tOEA tWP
Address
Row
Column address tRWD tAWD tRCS
WE OE Upper input
tCLZ tCAC tAA tRAC tOLZ
tOED Data in tOEZ
tDS
tDH
Upper output
Data out tOED
Lower input Lower output
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tRWC tRAS tRP tRPC tCSH tRCD tCRP tCAS tRSH tRAL tACS tRAH Row tCAH tCRP
RAS
tCRP
UCAS
LCAS
tRAD tASR
Address
Column address tRWD tAWD tRCS tCWD tOEA tCWL tRWL tWP
WE OE Upper input Upper output Lower input
tRAC tAA tCAC tCLZ tOLZ tOED
tDH tOED tDS Data in tOEZ Data out
Lower output
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RAS
tCSH tCRP tRCD tCAS tCP tRHCP tHPC tRSH
UCAS, LCAS
tRAD tASR tRAH Row
tAR tRAL tASC Col address tRCS Col address tCAH Col address tRCH tOEA tOEA tCPA tCPA Data out tOLZ tOEZ tOEZ tOFF tRRH
Address WE OE
tRAC tCLZ tCAC tAA
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Data out tCLZ
Data out tCLZ
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tRASP tRP tRSH tCAS tHPC tHPC tCRP tCAS tRAH tRAD tASC Row Column 1 tRCS tCAH tCAH Column 2 tASC tCP tRAL tCAH tASC Column n tRCH tRPC tCRP
RAS
tCSH
UCAS
tCRP
tRCD tCP
tCAS
LCAS
tASR
Address
WE
tOEA tOEA tCAC tCLZ tAA tCPA tOEA tRRH
OE
tOLZ tOEZ Data out 2 tAA tRAC tCAC tCLZ tOLZ tCAC tCLZ tAA tCPA
Lower DQ
tOEZ Data out 1
tOFF tOEZ Data out n
Upper DQ
tOLZ
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RAS
tCRP tRCD
UCAS, LCAS
tASR tRAD Row address
tAR
Address
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tHDR tDS tDH Data in Data In Data in tOED
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tRASP tRP tRSH tCAS tCP tHPC tCRP tCAS tRAD tRAH tASR tASC Row Column 1 tRAL tCAH tASC Column 2 tCAH tCAH tASC Column n tRWL tWCH tWCS tWP tCWL tWCH tWCS tWP tCWL tWCS tWP tCWL tWCH tHPC tRPC tCP
RAS
tCSH tCRP tRCD tCAS tCRP
UCAS
LCAS
Address
WE OE
tDS tDH Data In 2 tDS tDH Data in 1 tDS tDH Data in n
Lower DQ Upper DQ
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RAS
tHPRWC tCSH tRCD tCAS tRAD tASR Row ad tRCS tRAH tASC tCAH Col ad tRWD tCWD tAWD tASC Col ad tCWL tCWD tCAH tASC tCP tCRP
UCAS, LCAS Address
tRAL tCAH tCPWD tCWD tAWD tWP tRWL tCWL
Col address
WE
tOEA tOEZ tDH tDS tCLZ tCAC Data in Data out Data in Data out tDS tCPA tCLZ tCAC Data in Data out tCLZ tCAC tOED tOEA
OE
tAA tRAC
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tASR Row address
tRAH
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RAS
tCSH tRCD tCRP tCAS tRSH tCAS
tCRP
UCAS
tCP tCAS tCP
LCAS
tRAL tRAD tRAH tASR tASC R C1 tAWD tCWD tRWD tWP C2 tCPWD tCWD tCWL tAWD tCPWD tCWL tWP tOEA tDH tDS tOED tDS tCPA tAA tCAC tCLZ Data out 1 Data out n tOEZ tOEA tDH tCAH tASC tCAH tAWD tASC Cn tAWD tCWD tCWL tWP tRWL tAWD tCAH
Address
tCAH
WE
tOEA
OE
tOED
Upper input
tRAC tAA tCAC tCLZ Data in 1 tOEZ Data in n
Upper output
tOED tDS tDH
Lower input
tCPA tAA tOEZ tCAC tCLZ Data in 2
Lower output
Data out 2
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RAS
tCRP
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tRAD tRAH tASR tASC Row tRCS Col address tRRH tOEA tAR tCAH
Address
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tRAC tAA tCAC tCLZ tOEZ Data out tOFF
DQ
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tRC tRAS tRP tCHR
RAS
tCRP tRCD tRSH
UCAS, LCAS
tRAD tRAH tASR tASC Row address tWCR tWP tWCS tWCH Col address tRWL tRAL tCAH tAR
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tDS tDHR tDH Data in
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RAS
tCSR tCPT tCHR
UCAS, LCAS
tCAS
tASC tCAH
tRAL
Address
Col address tAA tCAC tCLZ tOFF tOEZ Data out tRCS tRRH tRCH
DQ Read cycle
WE
tROH tOEA
OE
tRWL tCWL tWP tWCH tWCS
Write cycle
WE
tDH tDS
DQ OE
Data in
tRCS tCWD tAWD
tWP tCWL
tRWL
WE Read-Write cycle
tOEA tOED
OE
t AA tCLZ tCAC tOEZ tDS Data out Data in tDH
DQ
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Seating Plane
A A1 A2 B b c D E E1 E2 e
42-pin SOJ Min Max 0.128 0.148 0.025 0.105 0.115 0.026 0.032 0.015 0.020 0.007 0.013 1.070 1.080 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM
50 49 48 47 46 45 44 43 42 41 40
36 35 34 33 32 31 30 29 28 27 26
c
50-pin TSOP 2 Min (mm) Max (mm) 1.2 0.05 0.95 0.30 0.12 20.85 10.03 11.56 1.05 0.45 0.21 21.05 10.29 11.96
TSOP 2
E He
A A1 A2 b
1 2 3 4 5 6 7 8 9 10 11
15 16 17 18 19 20 21 22 23 24 25
c d l E He
d
A A1 b e
A2
0-5
e l
0.80 (typical) 0.40 0.60
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Parameter Input capacitance DQ capacitance Symbol CIN1 CIN2 CDQ Signals A0 to A9 RAS, UCAS, LCAS, WE, OE DQ0 to DQ15
| Vin = 0V Vin = 0V
0+] 7D Max 5 7 7
5RRP WHPSHUDWXUH Unit pF pF pF
Test conditions
Vin = Vout = 0V
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Package \ RAS access time
Plastic SOJ, 400 mil, 42-pin TSOP 2, 400 mil, 44/50-pin 45 ns AS4C1M16E5-45JC AS4C1M16E5-45TC 50 ns AS4C1M16E5-50JC AS4C1M16E5-50JI AS4C1M16E5-50TC AS4C1M16E5-50TI 60 ns AS4C1M16E5-60JC AS4C1M16E5-60JI AS4C1M16E5-60TC AS4C1M16E5-60TI
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AS4 DRAM prefix C C = 5V CMOS 1M16E5 Device number -XX RAS access time X X Package: Temperature range J = 42-pin SOJ 400 mil C=Commercial, 0C to 70 C T = 44/50-pin TSOP 2 400 mil I=Industrial, -40C to 85C
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