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CXP827P16
CMOS 8-bit Single Chip Microcomputer
Description The CXP827P16 microcomputer is composed of a CPU, ROM, RAM, and I/O ports. These chips feature many other high-performance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, fluorescent display panel controller/driver, remote control receiver, PWM output circuit and 32kHz timer/counter. This IC also includes sleep/stop functions which can be used to achieve low power consumption. CXP827P16 is the PROM-incorporated version of the CXP82716 with built-in mask ROM, and it is able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 64 pin SDIP (Plastic)
Structure Silicon gate CMOS IC
Features * Instruction set which supports a wide array of data types -- 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and Boolean bit operations. * Minimum instruction cycle 400ns at 10MHz 122s at 32kHz * On-chip PROM 16 Kbytes * On-chip RAM 448 bytes (Including fluorescent display data area) * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation system (conversion rate 32s/10MHz) -- Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer), 2 channels for 1 circuit -- Timers 8-bit timer 8-bit timer/counter 19-bit time-base timer 32kHz timer/counter -- Fluorescent display panel controller/driver High voltage drive output port of 24 pins (40V) Maximum of 144 segments display available 1 to 16-digit dynamic display Dimmer function On-chip pull-down resistor Hardware key scan function (Maximum of 8 x 8 key matrix available) -- Remote control receiver circuit On-chip 6-stage FIFO 8-bit pulse measurement counter -- PWM output 8-bit, 1-channel * Interrupts 13 factors, 13 vectors multi-interruption possible * Standby mode SLEEP/STOP * Package 64-pin plastic SDIP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E93Z22-ST
Block Diagram
INT0 INT1 INT2 INT3/NMI
AN0 to AN7 SPC700 CPU CORE CLOCK GENERATOR / SYSTEM CONTROL
8
A/D CONVERTER
2
TEX TX EXTAL XTAL RST VDD Vss VPP
T0 to T7 RAM
8
T8/S28 to T15/S21
8
S13 to S20 VFDP KR0 to KR7 RAM FIFO PROM 16KBYTES
8
KEY SCAN
INTERRUPT CONTROLLER
RAM 448 BYTES
PORT C
RMC
REMOCON
PORT B
8
FDP CONTROLLER/ DRIVER
PORT A
8
PA0 to PA7
8
PB0 to PB7
8
PC0 to PC7
PWM
8 BIT PWM
EC
8 BIT TIMER/COUNTER 0
PORT F
CS0 SI0 SO0 SCK0 CS1 SI1 SO1 SCK1 FIFO 2 PRESCALER/ TIME BASE TIMER
SERIAL INTERFACE UNIT
32kHz TIMER/COUNTER
PORT E
ADJ 2
PORT H
-2-
5 2
PE0 to PE4 PE5 to PE6
3
PF5 to PF7
TO
8 BIT TIMER 1
2
PH0 to PH1
CXP827P16
CXP827P16
Pin Configuration (Top View)
PH0/TX PH1/TEX VPP PE6/ADJ/TO PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD PE5/PWM PE4/RMC PE3/INT3/NMI PE2/INT2 PE1/INT1 PE0/EC/INT0 VFDP T0 T1 T2 T3 T4 T5 T6 T7 T8/S28 T9/S27 T10/S26 T11/S25 T12/S24 T13/S23 T14/S22 T15/S21 S20 S19 S18 S17 S16 PF7/S15 PF6/S14 PF5/S13
Note) 1. Vpp (Pin 3) is always connected to VDD. 2. PH0/TX (Pin 1) is input port during port selection; oscillation output during oscillation selection
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CXP827P16
Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions
PA0/AN0 to PA7/AN7
I/O/Analog Input
Analog inputs to A/D converter. (8 pins)
PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port C) 8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
Chip select input for serial interface (CH1). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).
PC0/KR0 to PC7/KR7
I/O/Input
Key return input for fluorescent display panel (FDP) segment signal which performs key scanning. (8 pins)
PE0/INT0/ EC PE1/INT1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5 PE6/ADJ/TO
Input/Input/ Input Input/Input Input/Input Input/Input/ Input Input/Input Output Output (Port E) 7-bit port. Lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins)
External interrupt requests. (4 pins)
External event input to timer/counter.
Non-maskable interruption request input. Input for remote control receiving circuit. 8-bit PWM output. Output for timer/counter rectangular waveform and 32kHz oscillation frequency division.
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CXP827P16
Symbol PF5/S13 to PF7/S15 S16 to S20 T8/S28 to T15/S21 T0 to T7 VFDP EXTAL XTAL PH1/TEX PH0/TX RST Vpp VDD Vss Input
I/O Output/Output Output Output/Output Output (Port F) 3-bit output port. (3 pins)
Functions Segment signal output for FDP. (3 pins)
Segment signal output for FDP. (5 pins) Output for FDP timing and segment signals. (8 pins) Timing signal output for FDP. (8 pins) FDP voltage supply when on-chip resistor is selected by mask option. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. (Port H) 2-bit input port. (2 pins) Crystal connectors for 32kHz timer/counter clock oscillation circuit. Connect a 32kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and leave TX open.
Output Input/Input Input/Output Input
System reset. Low-level active. RST is input pin. Positive power supply pin for writing of built-in PROM. Under normal operating conditions, connect to VDD. Positive power supply. GND
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CXP827P16
I/O Circuit Format for Pins Pin Port A
Pull-up resistor "0" when reset Port A data
Circuit format
*
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset A/D converter
Input multiplexer Pull-up transistors approx. 100k
8 pins Port B
Pull-up resistor "0" when reset Port B data
PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1
Data bus
Port B direction "0" when reset Schmitt input RD (Port B) CS0 CS1 SI0 SI1
IP
Hi-Z
Pull-up transistors approx. 100k
4 pins Port B
SI0 and SI1 are not schmitt input.
Pull-up resistor "0" when reset SCK OUT Serial clock output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset Schmitt input RD (Port B) IP
PB2/SCK0 PB5/SCK1
Hi-Z
Data bus
2 pins
SCK IN
Pull-up transistors approx. 100k
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CXP827P16
Pin Port B
Pull-up resistor "0" when reset SO Serial data output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset
Circuit format
When reset
PB4/SO0 PB7/SO1
IP
Hi-Z
Data bus
2 pins
RD (Port B)
Pull-up transistors approx. 100k
Port C
Pull-up resistor "0" when reset 2
PC0/KR0 to PC7/KR7
Port C data
Hi-Z
Port C direction "0" when reset Data bus RD (Port C) 1 Large current drive of 12mA possible 2 Pull-up transistors approx. 100k 1 IP
8 pins Port E PE0/EC/INT0 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC
Key input signal
Schmitt input IP
EC/INT0 INT1 INT2 INT3/NMI RMC Data bus RD (Port E)
Hi-Z
5 pins
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CXP827P16
Pin Port E
PWM Port E output selection "0" when reset
Circuit format
When reset
PE5/PWM
Port E data "1" when reset Output enable
High level
Data bus
1 pin Port E
RD (Port E)
Internal reset signal Port E data "1" when reset TO ADJ16K1 00 01 10 11 MPX 2
PE6/TO/ADJ
ADJ2K1
Port E output selection(upper) Port E output selection(lower) "00" when reset TO output enable 1 ADJ signal is a frequency dividing output for 32kHz oscillation frequency adjustment. ADJ2K can be used for buzzer output. 2 Pull-up transistor approx. 150k .
(
High voltage drive transistor
High level with approx. 150k resistor when reset
)
1 pin Port F
Segment output data
PF5/S13 to PF7/S15
Output selection control signal ("0" when reset) Port F data
Hi-Z
Data bus
3 pin
RD (Port F)
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CXP827P16
Pin
Circuit format
High voltage drive transistor
When reset
S16 to S20 T15/S21 to T8/S28 T0 to T7
Segment output data Output selection control signal ("0" when reset)
Low level
Pull-down resistor
21 pins
VFDP
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit construction for oscillation. * During STOP feedback resistor is disconnected, and XTAL becomes "H" level.
Oscillator
2 pins
XTAL
32kHz oscillation circuit control "1" when reset Data bus
PH1/TEX PH0/TX
PH1/TEX IP IP
RD (Port H) Data bus RD (Port H) Clock input
Oscillation halted prot input
2 pins
PH0/TX
Pull-up resistor
RST Low level 1 pin
IP Schmitt input
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CXP827P16
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Display output voltage Symbol VDD Vpp VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current IOH IODH IOL IOLC Low level total output current IOL Operating temperature Storage temperature Allowable power dissipation Topr Tstg PD Rating -0.3 to +7.0 -0.3 to +13.0 -0.3 to +7.01 -0.3 to +7.01 VDD - 40 to VDD + 0.3 -5 -15 -35 -40 -100 15 20 100 -10 to +75 -55 to +150 1000 Unit V V V V V mA mA mA mA mA mA mA mA C C mW Incorporated PROM Remarks
(Vss = 0V)
As P channel transistor is open drain, VDD voltage is determined as reference. Other than display putput pins2: per pin Display output S13 to S20: per pin Display output T0 to T7 T8/S28 to T15/S21: per pin Total of other than display output pins Total of display output pins Port 1 pin Large current port pin3 Total of all pins
1) VIN and VOUT must not exceed VDD+0.3V. 2) Specifies output current of general-purpose I/O ports. 3) The large current drive transistor is an N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
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CXP827P16
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Vpp VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 1) 2) 3) 4) Max. 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V C Remarks
(Vss = 0V)
Guaranteed operation range for high speed mode (1/2, 1/4 frequency dividing clock) Guaranteed operation range for low speed mode (1/16 frequency dividing clock) Guaranteed operation range with TEX clock Guaranteed data hold operation range during STOP 4 1 Hysteresis input2 EXTAL pin3 1 Hysteresis input2 EXTAL pin3
Supply voltage
VDD
Vpp = VDD 0.7VDD 0.8VDD VDD - 0.4 0 0 -0.3 -10 VDD VDD VDD +0.3 0.3VDD 0.2VDD 0.4 +75
All regular input port (PA, PB4, PB7, PC, PH). For pins RST, CS0, CS1, SI0, SI1 SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC. Specifies only for external clock input. Vpp should be the same voltage as VDD.
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CXP827P16
Electrical Characteristics DC Characteristics Item Symbol Pin Condition VDD = 4.5V, IOH = -0.5mA PA, PB, PC, VDD = 4.5V, IOH = -1.2mA PE5, PE6 VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA PC IIHE IILE IIHT Input current IILT IILR IIH IIL I/O leak current IIZ RST PA to PC1 TEX EXTAL VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIH = 4.0V VDD = 5.5V, VIL = 0.4V PA to PC1, VDD = 5.5V PE0 to PE4 VI = 0, 5.5V S13 to S20 Display IOH output current Open drain output leak current (P-CH Tr off state) Pull-down resistor S21/T15 to S28/T8, T0 to T7 VDD = 4.5V VOH = VDD -2.5V -8 -20 0.5 -0.5 0.1 -0.1 -1.5 -3.3 50 10 (Ta = -10 to +75C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A A A A mA mA
High level VOH output voltage Low level output voltage VOL
ILOL
S13 to S20, S21/T15 to VDD = 5.5V VOL = VDD - 35V S28/T8, VFDP = VDD - 35V T0 to T7 S16 to S20, S21/T15 to VDD = 5V S28/T8, VFDP = VDD - 35V T0 to T7 High-speed mode operation (1/2 frequency dividing clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF)
-20
A
RL
60
100
270
k
IDD1
20
40
mA
IDD2 Supply current2 VDD
VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) SLEEP mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode VDD = 5.5V, termination of 10 MHz and 32 kHz crystal oscillation.
400
1000
A
IDDS1
1.2
8
mA
IDDS2
9
30
A
IDDS3
30
A
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CXP827P16
Item
Symbol
Pin
Codition
Min.
Typ.
Max.
Unit
Input capacitance
CIN
PA to PC, 1MHz clock PE0 to PE4, 0V for pins other than the measured PH, EXTAL, pins XTAL, RST
10
20
pF
1) In each pin of PA to PC, the input current is specified when pull-up resistor has been selected; leakage current is specified when no resistor is selected. 2) All output pins are left open.
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CXP827P16
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tsys + 50
32.768
kHz
tTL, tTH tTR, tTF
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control registor (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HCO4
C1
C2
Fig. 3. Event count clock timing
TEX EC
0.8VDD 0.2VDD
tEH tTH
tEF tTF
tEL tTL
tER tTR
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CXP827P16
(2) Serial transfer Item CS0 SCK0 (CS1 SCK1) delay time CS0 SCK0 (CS1 SCK1) float delay time CS0 SO0 (CS1 SO1) delay time CS0 SO0 (CS1 SO1) float delay time CS0 (CS1) high level width SCK0 (SCK1) cycle time SCK0 (SCK1) High and Low level widths SI0 (SI1) input setup time (for SCK0 (SCK1 ) ) SI0 (SI1) input hold time (for SCK0 (SCK1 ) ) SCK0 SO0 (SCK1 SO1) delay time Note 1) Symbol Pin
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Min. Max. Unit
tDCSK
SCK0 Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) (SCK1) (SCK0 (SCK1) = output mode) SO0 (SO1) (SO1) (CS1) Chip select transfer mode Chip select transfer mode Chip select transfer mode
tsys + 200 ns tsys + 200 ns tsys + 200 ns tsys + 200 ns tsys + 200
2tsys + 200 16000/fc ns ns ns ns ns ns ns ns ns
tDCSKF SCK0 Chip select transfer mode tDCSO
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0 Input mode (SCK1) Output mode SCK0 Input mode (SCK1) Output mode SI0 (SI1) SI0 (SI1) SO0 (SO1) SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode
tsys + 100
8000/fc-5 0 100 200
tsys + 200
100 100
tsys + 200 ns
ns
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control clock registor (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF+1TTL.
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CXP827P16
Fig. 4. Serial transfer CH0 timing
tWHCS
0.8VDD CS0 (CS1) 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 (SCK1) 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 (SI1) Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 (SO1) Output data 0.2VDD
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CXP827P16
(3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = 0V Symbol Pin Condition
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Min. Typ. Max. 8 3 -10 4910 160/fADC3 12/fADC3 10 4970 70 5030 Unit Bits LSB mV mV s s VDD V
tCONV tSAMP
AN0 to AN7
Analog input voltage VIAN
0
Fig. 5. Definition of A/D converter terms
FFH FEH
Linearity error 01H 00H VZT Analog input VFT
1)V ZT : Value at which the digital conversion value changes from 00 H to 01H and vice versa. 2)V FT : Value at which the digital conversion value changes from FE H to FFH and vice versa. 3)f ADC indicates the below values due to the bit 6 (CKS) of A/D control registor (ADC: 00F9 H) and the bit 7 (PCK1) and bit 6 (PCK0) of clock control registor (CLC: 00FE H) CKS PCK1, 0 00 (= fEX/2) 01 (= fEX/4) 11 (= fEX/16) 0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
Digital conversion value
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CXP827P16
(4) Interruption, reset input Item Symbol
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Pin INT0 INT1 INT2 INT3 NMI RST Condition Min. Max. Unit
External interruption High and Low level widths
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
Fig 6. Interruption input timing
tIH tIL
INT0 INT1 INT2 INT3 NMI (NMI is specified only for the falling edge)
0.8VDD 0.2VDD tIL tIH
Fig. 7. RST input timing
tRSL
RST 0.2VDD
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CXP827P16
Appendix Fig. 8. Recommended oscillation circuit
(i) Main clock
(ii) Main clock
(iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd
C1
C2 C1 C2
C1
C2
Manufacturer
Model CSA4.19MG CSA8.00MTZ
fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19
C1 (pF)
C2 (pF)
Rd ()
Circuit example
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW
RIVER ELETEC CO., LTD.
HC-49/U03
8.00 10.00 4.19
12
12
0 (i)
27 20 50
27 20 22
KINSEKI LTD.
HC-49/U (-S)
8.00 10.00
0
P3
32.768kHz
1M
(iii)
The above model with an asterisk () includes the capacitors (C1, C2).
Selection Guide Option Item Package ROM capacitance Reset pin pull-up resistor High voltage drive output pin pull-down resistor Mask Product 64-pin plastic SDIP 12 Kbytes/16 Kbytes Existent/Non-Existent Existent/Non-Existent CXP827P16S-164-pin plastic SDIP PROM 16 Kbytes Existent Existent (T0 to T7, S16 to S28), Non-Existent (S13 to S15)
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CXP827P16
Characteristics Curves
IDD vs. VDD
(fc = 10MHz, Ta = 25C, Typical) 20.0 10.0 1/2 frequency dividing mode 20
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
IDD -- Supply current [mA]
5.0
IDD -- Supply current [mA]
1.0 0.5
1/16 frequency dividing mode 32kHz mode (instruction) SLEEP mode
15 1/2 frequency dividing mode
10
0.1 (100A) 0.05 (50A)
32kHz SLEEP mode
5
0.01 (10A) 2 3 4 5 6 7 0 VDD -- Supply voltage [V]
1/16 frequency dividing mode SLEEP mode 5 10 fc -- System clock [MHz] 15
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CXP827P16
Package Outline
Unit: mm
64PIN SDIP (PLASTIC) 750mil
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15
1 1.778
32
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g
- 21 -
3 MIN
0.5 MIN + 0.4 4.75 - 0.1

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