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Ordering number: EN 4952
Monolithic Linear IC
LA7578N IF Signal Processing (Super PLL-II VIF + SIF) Circuit for TVs and VCRs
Overview
The LA7578N is an intercarrier-type VIF + SIF IC that supports excellent sound quality and image quality. The pin assignment of the LA7578N is identical to that of the LA7577N, allowing the LA7577N to be used for split systems while the LA7578N is used for intercarrier systems. In addition, the LA7578N suppresses Nyquist buzz interference by using a PLL detection system with a buzz canceller in order to provide the best sound quality possible.
Package Dimensions
unit : mm
3067-DIP24S
[LA7578N]
Functions
. . . . . . [SIF Block] . Limiter amplifier [Mute] . Audio mute (pin 2) . IS-15 switch (pin 13)
Features
[VIF Block] VIF amplifier VCO APC filter B/W NC AFT IF AGC
. PLL detector . Equalizer amplifier . Lock detection . RF AGC . APC detector . Buzz canceller . FM quadrature detector . AV mute (pin 4)
SANYO : DIP24S
. Excellent buzz and buzz-beat characteristics due to PLL system . detectionAPC timewith buzz canceller. Built-in constant switch. . Duplicate time constant system suited for high-speed AGC. . Excellent DG and DP characteristics. . RF AGC adjustment is simple.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
81095HA (II)No.4952 - 1/18
LA7578N
Specifications
Maximum Ratings at Ta = 25 C
Parameter Maximum supply voltage Allowable power dissipation Circuit voltage Circuit current Symbol VCC max Pd max V3, V13 V14 I1 I17 I21 I10 Operating temperature Storage temperature Topr Tstg Note 1 Ta % 50 C Conditions Ratings 13.8 1200 VCC VCC -1 -10 -3 3 -20 to +70 -55 to +150 Unit V mW V V mA mA mA mA C C
Note : The current that flows into the IC is positive (no signal); the current that flows out of the IC is negative. Note 1 : -20 to +75 C at VCC = 9 V
Operating Conditions at Ta = 25 C
Parameter Recommended supply voltage Operating supply voltage range Symbol VCC VCC op Conditions Ratings 9 or 12 8.2 to 13.2 Unit V V
Note:
. Always turn on directly the IC . A capacitor withthe protective resistance when drawing a line used for out from(ex. OS at usage. (Pins 2, 11, 12, etc.) favorable humidity characteristics should be pin 13. capacitor) . Pin 8 (NC) should always be open.
Symbol I9 V21 V10H V10L V14 Vi GR Vi max VO (video) S/N V21 (tip) I920 fc DG DP V14H V14L VWTH VWCL VBTH VBCL Conditions V13 = 5 V, S1 = ON V13 = 5 V, S1 = ON V13 = 7 V, S1 = OFF V13 = 7 V, S1 = ON V13 = 5 V, S1 = ON S1 = OFF S1 = ON S1 = ON S1 = ON S1 = ON Vi = 10 mV, S1 = ON P = 0, C = -4 dB, S = -14 dB, S1 = ON P = 0, S = -14 dB Vi = 10 mV, 87.5% mod, fp = 58.75 MHz 11 0 8.9 5.3 3.4 5.3 min 42 6.6 10.6 3.0 33 60 100 1.95 49 4.15 37 6 typ 48 7 11 0 5.9 39 66 105 2.25 55 4.45 43 8 3 2 11.5 0.4 9.3 5.7 3.7 5.7 max 57 7.4 11.4 0.5 8.0 45 Unit mA V V V V dB/V dB dB/V Vp-p dB V dB MHz % deg V V V V V V
Operating Characteristics at Ta = 25 C, VCC = 12 V
Parameter [VIF Block] Circuit current No-signal video output voltage Maxinum RF AGC voltage Mininum RF AGC voltage No-signal AFT voltage Input sensitivity AGC range Maxinum allowable Input Video output amplitude Output S/N Sync signal tip voltage 920 kHz beat level Frequency characteristics Differential gain Differential phase Maxinum AFT voltage Mininum AFT voltage White noise threshold voltage White noise clamp voltage Black noise threshold voltage Black noise clamp voltage
2.55 4.75
S1 = ON S1 = ON
6 5 12 1.0 9.7 6.1 4.0 6.1
Continued on next page.
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Continued from preceding page.
Parameter AFT detection sensitivity VIF input resistance VIF input capacity APC pull-in range (U) APC pull-in range (L) VCO maximum variable range VCO control sensitivity SIF output signal voltage [SIF Block] : V13 = 5 V SIF limiting sensitivity FM detection output voltage AMR Distortion SIF S/N [Mute Defeat] AFT defeat start voltage AV mute FM mute AFT defeat voltage Symbol Sf Ri (VIF) Ci (VIF) fPU-2 fPL-2 fU fL VO (SIF) Vi (lim) VO AMR THD S/N (SIF) VD11 V4TH V2TH VD14 Conditions f = 58.75 MHz f = 58.75 MHz S1 = ON S1 = ON V18 = 3 V, S1 = ON V18 = 7 V, S1 = ON V18 = 5 V to 4.6 V P/S = 20 dB min 50 0.8 0.6 0.6 1.5 120 typ 70 1.3 3.0 1.6 -1.6 1.6 -1.6 3.1 170 33 600 49 0.5 78 2.3 1.9 2.0 6 max 100 1.75 6.0 -0.8 -0.8 6.2 240 39 790 1.0 Unit mV/kHz k pF MHz MHz MHz MHz kHz/mV mVrms dB/V mVrms dB % dB V V V V
400 40 60 0.5 0.5 0.5 5.4
6.6
Operating Characteristics at Ta = 25 C, VCC = 9 V
Parameter [VIF Block] Circuit current No-signal video output voltage Maxinum RF AGC voltage Mininum RF AGC voltage No-signal AFT output voltage Input sensitivity Video output amplifude Sync signal tip voltage Maximum AFT voltage Minimum AFT voltage White noise threshold voltage White noise clamp voltage Black noise threshold voltage Black noise clamp voltage AFT detection sensitivity SIF output signal voltage [SIF Block] FM detection output voltage [Mute defeat voltage] AFT defeat start voltage AV mute FM mute AFT defeat voltage Symbol I9 V21 V10H V10L V14 Vi VO (video) V21 (tip) V14H V14L VWTH VWCL VBTH VBCL Sf VO (SIF) VO VD11 V4TH V2TH VD14 Conditions V13 = 5 V, S1 = ON V13 = 5 V, S1 = ON V13 = 7 V, S1 = OFF V13 = 7 V, S1 = ON V13 = 5 V, S1 = ON S1 = OFF S1 = OFF Vi = 10 mV, S1 = ON min 36 5.0 7.6 2.6 37 1.5 3.25 8 6.8 4.0 2.5 3.7 30 90 400 0.5 0.5 0.5 3.9 typ 41 5.4 8 0 4.5 43 1.75 3.55 8.5 0.3 7.2 4.4 2.8 4.1 43 130 600 1.6 1.1 1.9 4.5 max 49 5.8 8.4 0.5 6.0 49 2.0 3.85 9.0 1.0 7.6 4.8 3.1 4.5 60 180 790 Unit mA V V V V dB/V Vp-p V V V V V V V mV/kHz mVrms mVrms V V V V
S1 = ON S1 = ON P/S = 20 dB V13 = 5 V
5.1
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LA7578N
Sample Application Circuit (JAPAN)
Unit (resistance : , capacitance: F) Pins 22 and 23 are grounded inside the IC.
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Sample Application Circuit (JAPAN)
When using no SIF, 1stSIF, AFT, RFAGC.
Unit (resistance : , capacitance : F)
1.
When using no SIF circuit: Pin1 = Open Pin2 = GND Pin24 = Open When using no AFT circuit: Pin11, 12 = GND Pin14 = Open When using no RFAGC circuit: Connect a capacitor of 0.01 F across Pin 4 and GND. Pin10 = Open
2.
3.
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LA7578N
LA7578N Interface Circuit
Unit (resistance : , capacitance : F)
No.4037-6/18
LA7578N
Buzz canceller
The LA7578N's PIF detector uses the PLL system. The PLL detection system has the following improved characteristics in comparison with the quasi-synchronous detection system. (1) Better waveform response characteristics in comparison with the quasi-synchronous detection system. (2) Harmonic components of the video signal are reduced. (3) Improved 1/2 IF signal suppression ratio. (4) Greatly reduced audio buzz. In general, in the PLL detection system, if the VCO power supply is affected by noise such as flyback pulses (FBP), the VCO oscillating frequency can be disturbed by the noise component, with a worsening of the buzz characteristics as a result. Therefore, in order to protect against the effects of VCO power supply fluctuations due to this type of noise in the LA7578N, the VCO power supply has been regulated to be constant. The explanation below concerns the PLL detector. A typical PLL detection system consists of the blocks shown in Fig. 1.
Fig. 1 PLL Detector
APC detection by the PLL detector shown in Fig. 1 is accomplished by multiplying the IF signal and the VCO signal by the phase difference /2, generating the VCO control voltage. Multiplying by the phase difference /2 makes it possible to suppress the AM component; in addition, because VCO is controlled through a low-pass filter (L.P.F), a carrier signal with a good C/N is obtained. As a result, by using the PLL detection system, the improved characteristics (1) through (4) listed above become possible. However, because television broadcasts are transmitted using the vestigial sideband system, simply using the PLL detection system will create the following problems in regard to the audio characteristics. The RF signal that is input from the antenna is converted to an IF signal by the tuner, and a Nyquist strobe generated by a SAW filter is passed through the corresponding vestigial sideband . At this point, because the sideband in the region of the picture carrier is eliminated as shown in Fig. 2, the vector amounts of the upper sideband and the lower sideband differ, generating a phase distortion () in the composite vector amount.
Sound carrier
Fig. 2
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If this phase distortion () appears, the PLL VCO will be modulated in synchronization with the error voltage, which causes the generation of a buzz. At Sanyo, this buzz generated by the phase distortion () is called ``Nyquist buzz.'' The LA7578N includes a new Nyquist buzz canceller circuit that suppresses this Nyquist buzz generated by the phase distortion () in an effort to greatly improve the buzz characteristics. Fig. 3 shows the PLL detection system in the LA7578N, which uses this Nyquist buzz canceller circuit.
Fig. 3 PLL Detector with Nyquist Buzz Canceller
In the PLL detection system with the Nyquist buzz canceller, even if phase distortion such as that shown in A is generated, the phase distortion in the APC detection output can be eliminated by generating and adding in a quasi-reverse phase buzz signal. Nyquist buzz Quasi-reverse phase buzz
Fig. 4 Nyquist Buzz Canceller Waveforms
The effect of this Nyquist buzz canceller circuit is to broadly suppress the buzz (fH harmonic ) generated as a sideband of the SIF beat signal (4.5 MHz). As a result, great improvements can be made in regard to the buzz beat generated during demodulation of Japan audio multiplexing (L-R) and the buzz characteristics during demodulation of U.S. MTS (Multichannel TV Sound) (L-R). Furthermore, because this Nyquist buzz cancellation method has no effect on the time constant of the PLL loop, it is also possible to try to improve various characteristics, by making it possible to, for example, design an APC filter that is not readily affected by flyback pulses (F.B.P), etc.
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Design Materials
Pin 1 (FM detector output) Pin 1 is the audio FM output pin. A 200 resistor is connected in series with the emitter follower. (1) Audio multiplexing applications Depending on the audio multiplexing decoder input application, the input impedance may be low, the L-R signals, etc., may be distorted, or the stereo characteristics may be degraded. In this type of situation, add a resistor between pin 1 and GND as shown in Fig. 6. R1 ^ 5.1 k (2) Monaural applications Add a de-emphasis circuit with external CR. t = CR2
Fig. 5
Fig. 6 De-emphasis
Pin 2 (FM discriminator) Pin 2 is the phase shifter pin for an FM quadrature detector. This pin generates the 90 deg phase shift signal needed for quadrature detection and adds it to the multiplier. (1) The detector band characteristics are primarily determined by the coil Q and coil damping resistance. Determine the damping characteristics in accordance with the output level and band characteristics. (2) When muting is applied, DC voltage (1 V or less) is applied to point A.
0.01F
Fig. 7
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Pins 3 and 13 (IF AGC pins) Pins 3 and 13 are the IF AGC filter pins. The signal for which the peak was detected by the AGC detector is smoothed by pin 13 (1st AGC) and pin 3 (2nd AGC) to generate the AGC voltage. A signal which has passed through an audio trap is used for the video signal that is input to this IF AGC detector. (1) These are typical AGC filter constants.
Single time constant C1 Pin 3 R1 C2 Pin 13 C3 R2 0.47 F 820 k 330 pF Double time constant 330 pF 2.2 k 0.47 F 0.068 F 820 k Double time constant 330 pF 1.8 k 0.1 F 0.047 F 820 k
Fig. 8
(2) Mute (IS-15 switch) The black noise canceller can be cut by setting pin 13 to 1 V or less. When doing so, the AGC voltage must be applied to pin 3 from an external source to drive the AGC system. ( IS-15 supported) (3) Ghost problems In a signal that produces ghosts, an interfering signal with a different phase overlaps with the desired signal, altering the video signal as shown in Fig. 9. The width of the sync signal narrows, making it impossible to maintain the IF AGC charge/discharge current ratio. If the phase change of the ghost interference wave increases, the symptom that appears is that the vertical sync portion rises as shown in Fig. 10. The countermeasure for alleviating this symptom is to insert a resistor (820 k to 1 M) between pin 13 and GND.
Normal video signal
Horizontal sync norrowed by ghost Fig. 9 Video Signal
Sync rises Fig. 10 Pin 4 (RF AGC VR) Pin 4 is the RF AGC adjusting pin. This pin sets the RF AGC operation point for the tuner. (1) Mute By setting this pin to 0.5 V or less, the FM output and the video output can be muted simultaneously.
Fig. 11
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Pins 5 and 6 (VIF input) These are the VIF amplifier input pins. The inputs must always have their DC components eliminated with capacitors. The inputs are equilibrium inputs. The input impedance is R 6 1.5 k, C 6 3 pF.
Fig. 12 Sanyo's SAW filter There are two types of filters, depending on the piezoelectric substrate material. (1) LiTaO3 (lithium tantalate) SAW filters: ...... TSF1xxx TSF2xxx While the LiTaO3 SAW filters offer excellent stability with a low temperature coefficient of -18 ppm/ C, the insertion loss is high. However, by using a coil, etc., for matching on the SAW filter output side (which does increase the number of external components), it is possible to suppress the insertion loss while at the same time making the level of the characteristics variable, which provides additional design freedom. (Refer to Fig. 13.) In addition, because the SAW (surface wave) reflection is small, ripple within the band can be kept low. (2) LiNbO3 (lithium niobate) SAW filter: ...... TSF5xxx While the LiNbO3 SAW filter has a high temperature coefficient of -72 ppm/ C, it has a lower insertion loss by about 10 dB compared to the LiTaO3 SAW filters. Therefore, matching on the output side of the SAW filter is not necessary. (Refer to Fig. 14.) In addition, because the insertion loss is low (although the ripple within the band is somewhat higher than in the case of the LiTaO3 SAW filter), the low impedance and small feedthrough diminish the effects of peripheral circuit components and the pattern layout, and make it possible to stabilize the trap characteristics outside of the band. From the above, it is clear that the LiTaO3 SAW filter is suitable for Japan and U.S. bands where the IF frequency is high, while the LiNbO3 SAW filter is suitable for PAL and U.S. bands where the IF frequency is low.
0.01F
Fig. 13
0.01F
Fig. 14
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Pin 8 (NC) This is an NC pin. When using the LA7577N, this pin becomes the 1st SIF input. Pin 10 (RF AGC output) Pin 10 is the RF AGC output pin. This pin controls the tuner RF AGC. As shown in Fig. 17, a protective resistor of 200 is connected in series with the emitter output. Determine the resistance bleeder value in accordance with the maximum gain of the tuner as shown in the diagram.
Fig. 15
Fig. 16
Fig. 17
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Pins 11 and 12 (AFT coil) Pins 11 and 12 are the AFT pins. In the quadrature detection system, a signal that has been phase-shifted 90 deg is generated by an external AFT tank, and phase detection is done by the multiplier. The IF signal has the band characteristics shown in Fig. (A) because of the SAW filter. Accordingly, even if the band characteristics of the AFT tank change, the AFT characteristics are extended in the low band as shown in Fig. C, which makes misoperation more likely. As a result, band restrictions are placed on the low band frequencies as shown in Fig. D by inserting C2 in series with the AFT tank. The ratio between C1 and C2 needed in order to suppress misoperation should be about 5:1 (C1:C2). In this case, insert either a resistor or an L in parallel with C2 so that the DC balance of the AFT circuit is not disrupted. (1) AFT DEFEAT To implement AFT defeat, connect these pins to GND through resistor R1. The resistance used in this case is 20 k or less.
AFT characteristics
AFT characteristics
Freq
Fig. 19
Carrier filter Also serves to protect IC.
AFT loop time constant
Fig. 18
Fig. 20
Pin 14 (AFT output) This is the AFT output pin. This pin controls AFT of the tuner. The AFT voltage is generated by an external bleeder resistor. The AFT loop time constant is determined by inserting a resistor (R3) and a capacitor as shown in the diagram between this output pin and the AFT input pin of the tuner. This resistor also serves to protect the IC. When the system of the selected station is the PLL system or the voltage synthesizer system, the variation of the no signal voltage of the AFT output becomes a problem. In this type of case, connecting a series resistor (R4) to the IC output as shown in Fig. 22 narrows the range over which AFT varies, making it possible to reduce the variation of the no signal voltage of the AFT output.
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Pins 15 and 16 (VCO tank) These pins are for the VCO tank circuit. The tank circuit capacitor is designed to be 20 to 27 pF. 24 pF is recommended. The VCO tank capacitor can be either built into the coil or a component in chip form. This circuit protects VCO from external influences.
Fig. 21
Pin 17 (composite video output) This is an output pin for the video signal including a 4.5 MHz component. Although this is an emitter output, a resistor should be connected between pin 17 and GND in order to attain satisfactory drive capability. VCC = 12 V R ^ 1.2 k VCC = 9 V R ^ 1 k
Fig. 22
Pin 18 (APC filter) This is the APC filter pin. APC time constant switching is performed within the IC. When locked, VCO is controlled by route A, and the APC loop gain decreases. When unlocked or when there is a weak electric field, VC is controlled by route B and the APC loop gain increases, broadening the pull-in range. The recommendations for this APC filter are: R = 47 to 150 ; C = 0.47 F. Fig. 23
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Series resonance
Fig. 24
Pins 19, 20, and 21 (EQ amplifier) These pins are for the equalizer amplifier. A signal that has passed through a 4.5 MHz trap is input to pin 19 and is output from pin 21. Pin 21 is of emitter follower. A resistor must be connected between pin 21 and GND in order to attain satisfactory drive capability. VCC = 12 V R ^ 2.7 k VCC = 9 V R ^ 2.2 k In addition, in order to draw the signal out externally, an external buffer transistor is required. (1) Equalizer amplifier design The equalizer amplifier consists of a voltage follower with a voltage gain of 0 dB. To compensate for the frequency characteristics, externally connect L, C, and R as shown in Fig. 26. Operation in this case is as follows: Assigning the input to vi and the output to vo, (R1/Z + 1) (vi + vin) = vo Assuming imaginary short state, if vin 6 0, then: Av = vo/vi = R1/Z + 1 If the application of pin 20 is as shown in Fig. 27, it can be used as a voltage amplifier. One point that requires caution, however, is the dynamic range of the equalizer amplifier. In short, the bleeder resistance ratio must be designed so that signals are not amplified excessively, and so that the leading edge voltage of the video signal sync signal is not too high or too low. In other words, the design must be such that the sync signal voltage does not change.
Fig. 25
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Designing the external bleeder resistance ratio so that the output DC voltage (V21) does not change when the voltage is amplified by the equalizer amplifier Assuming the desired gain is Av, then to make Vx 6 V21 so that the sync signal voltage does not change: Vx = VCC x R2/(R2 + R3) ................. : (1) From the desired voltage gain: Av = 1 + 1 k/Z1 .................................. : (2) Z1 = R2 x R3/(R2 + R3) .................... : (3) And then: R2 = 1 k x VCC/[(VCC - Vx) x (Av-1)] ............: (4) R3 = 1 k x VCC/[(Av - 1) x Vx] ........................: (5) These simple calculations can be used to design the ratio.
Fig. 26
Pin 22 (GND) Connected to GND within the IC. Pin 23 (GND) Connected to GND within the IC. Pin 24 (SIF input) This is the SIF input pin. The input impedance is approximately 1 k. If an interfering wave (video signal, etc.) flows into this input, it will generate a buzz or buzz beat; therefore, caution must be exercised in regard to the pattern layout for the input circuit. Fig. (B) below shows a bad example.
Fig. 27
Ceramic BPF pin 24
(A) Good example Ceramic BPF
Pin 24
BPF input and output are close to each other. (B) Bad example Fig. 28 No.4037-16/18
LA7578N
Coil Specifications
JAPAN f = 58.75 MHz VCO coil T1 US f = 45.75 MHz PAL f = 38.9 MHz
AFT coil T2
SIF coil T4
SAW Filter (SANYO)
Picture TSF1110M TSF1110P TSF1141P
M TYPE P TYPE P TYPE
Picture TSF1203M TSF1239P TSF1233P
M TYPE P TYPE P TYPE
Picture (MULTI)TSF5321 (BG) TSF5316U (38M MULTI) TSF5341U
K TYPE U TYPE U TYPE
( VCO tank circuit design considerations) a. VCO tank circuit with an internal capacitor When power is supplied to the IC, the heat from the IC is propagated to the PCB, and then to the VCO tank. In this instance, the legs of the tank coil substitute for a heat sink. Because the heat radiates from there, heat is not easily propagated to the VCO tank's internal capacitor, reducing the effect on VCO drift when the power is on. Accordingly, it is desirable for the design to basically seek to cancel out the temperature characteristics through the L and C. Basically, it is best to use an L with a core material that has small temperature characteristics, and also to use a capacitor with small temperature characteristics. VCO tank circuit with an external capacitor In the case of an external chip capacitor, the heat from the IC is propagated to the PCB, and then to the external chip capacitor. As a result, the chip capacitor is affected by the heat, and its capacitance changes. In this case, because the VCO coil is relatively unaffected, the end result is that the alignment point of the VCO tank changes. Accordingly, it is best to use an L with a core material that has small temperature characteristics, and also to use a capacitor with small temperature characteristics.
b.
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No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1995. Specifications and information herein are subject to change without notice.
No.4037-18/18

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